Common-Mode Filter for Transformer-Less Split-Phase Neutral Grounded Inverter ^†

Abstract

A three-leg full-bridge inverter is conventionally used to generate split-phase AC voltage. If the neutral phase of such an inverter is grounded, then parasitic currents of significant magnitude appear in the ground circuit. This issue arises primarily due to the presence of high-frequency common-mode voltage between the output AC terminals and the DC-bus terminals. In this paper, split DC-bus capacitors are introduced in the conventional inverter circuit to attenuate the common-mode switching voltage. The addition of the capacitive filter forms a second-order low-pass filter for common-mode voltage and attenuates the magnitude of the switching-frequency component of common-mode voltage by around 40 dB. The proposed inverter is thereby able to generate a transformer-less neutral grounded split-phase AC voltage supply for an off-grid application. The simulation and experimental results of a 12 kW lab prototype are presented for verifying the proposed converter circuit topology.

1. Introduction

Distributed energy resources (DERs), such as solar and wind energy, are steadily gaining a larger share among the mix of energy sources used in today’s power systems [1,2,3,4,5]. However, the intermittency of DERs poses a significant roadblock to their successful integration with the existing utility grid infrastructure. The intermittent nature of DERs directly impacts their availability and reliability [6,7,8]. These challenges are mitigated by energy storage systems (ESSs), which provide energy-buffering capabilities. The energy stored in an ESS is typically delivered to the loads as AC voltage [4,7,8,9]. Specifically, residential and commercial consumers are powered by low-voltage AC. However, the energy storage devices that are typically used in an ESS, such as batteries, store electrical energy in DC form. Thus, the stored energy in DC form needs to be converted into the AC format by using an inverter. Moreover, the AC voltage generated by the inverter must comply with the local and national electrical codes [10]. According to the electrical codes, a typical North American residential power supply architecture comprises split-phase 120 V/240 V, 60 Hz AC voltage with a grounded neutral terminal. Therefore, the AC voltage generated by the inverter of an ESS must support the electrical grounding of the neutral terminal.

Conventionally, the DC voltage of a battery is converted into split-phase AC voltage by using a single-phase inverter connected to a low-frequency transformer [11,12]. The transformer is connected at its primary winding to the single-phase inverter and generates two phases of output on its secondary windings. The secondary windings of the transformer are connected such that the two phases are ${180}^{\circ }$ apart and the common point becomes the neutral terminal. Since the split-phase voltage generated by a transformer is isolated from the inverter, the neutral terminal can be connected to ground without any significant parasitic ground currents affecting the inverter. However, a low-frequency transformer is undesirable in this application due to its bulky size and large weight, which lead to low power density of the inverter. The low-frequency transformer can be eliminated in this application by using a three-leg full-bridge inverter that is driven by using sinusoidal modulating signals [13,14,15,16,17,18,19,20]. Due to the switching action of the inverter, high-frequency common-mode (CM) voltage develops between the AC terminals and the terminals of the DC bus. When the neutral terminal of the AC is connected to earth ground, large currents flow through the insulation and isolation capacitance of various components of the inverter, which can lead to the failure of the inverter.

Grounding the neutral terminal brings significant complications in realizing the transformer-less split-phase inverter when used in off-grid energy storage applications. First, the battery is the only major energy source that can be used to generate auxiliary power supplies (APSs), which are necessary to powering the control systems and other electronic interfaces. Consequently, these auxiliary circuits are referenced to the negative terminal of the DC bus. However, the control system interfaces that are user-accessible need to be referenced to earth ground due to safety concerns. Such a power architecture requires isolated auxiliary power supplies that are connected on the primary side to the DC bus of the ESS and generate a voltage referenced to earth ground. The isolation barrier of this power supply experiences CM voltage at switching frequency. Consequently, switching-frequency current passes through the isolation capacitance. Depending on the power rating of the isolation transformers in these APSs, and other distributed isolation elements such as wire insulation, insulation of power MOSFETs, etc., the parasitic capacitance of the isolation barrier may be significantly high. Due to the presence of substantial isolation capacitance, current of significant magnitude flows through it, accelerating its degradation and potentially leading to failure.

On the other hand, the high-frequency CM voltage generated by the inverter by using silicon-carbide (SiC) devices has higher switching frequencies and faster switching transients compared with conventional silicon devices such as MOSFETs and IGBTs. The switching transients can range from 100 to 200 V/ns. Both the higher switching frequencies and high ${\displaystyle \frac{dV}{dt}}$ transitions contribute to ground currents that develop across the isolation barriers [21,22]. Moreover, the isolation capacitance of the APS itself should be able to sustain such fast voltage transients over the inverter’s lifetime. These types of specialty APSs with low isolation capacitance are bulky and expensive, if they exist at all. Even after using such specialized power supplies, EMI emissions and ground currents due to parasitic elements of the circuit remain big concerns. These issues lead to spurious system problems and even system failures, thereby not allowing for the use of transformer-less inverters in such applications [23].

Numerous works reported in the literature have attempted to deal with the issue of CM voltage attenuation by using active and passive filters [24,25,26,27,28,29,30,31,32,33,34]. The key applications of these studies have been grid-connected and off-grid standalone inverters or motor drive applications. In most of the literature, CM noise is mainly generated due to the switching action of semiconductor devices, which results in low-frequency steady-state voltage on the inverter terminals superimposed with the high ${\displaystyle \frac{dV}{dt}}$ transient voltage spikes. The magnitude of CM noise voltages due to switching transients is typically small (5–10 V), but they have a wide bandwidth. Therefore, active filters such as those reported in [24,25,26,27,28] use low-voltage semiconductor amplifiers that help attenuate low-voltage wide-bandwidth CM noise, whereas in the current application, the CM voltage that needs to be attenuated is the switching-frequency voltage that has the same peak-to-peak voltage as the battery voltage (450 V). For attenuating high-voltage CM signals, active filters consist of an additional power semiconductor leg, as was used in [33]. However, such active filtering solutions require special modulation techniques and are neither cheap nor high in density. On the other hand, multiple attempts utilizing passive filters have been reported in the literature to reduce the magnitude of CM noise at the output terminals, such as [30,31,32,34]. However, most of the works do not discuss the effects of CM voltage on the auxiliary circuits, as none of the output terminals is physically grounded. In the current work, the problem due to CM voltage is compounded by the fact that one of the output terminals of the inverter is solidly grounded, thus applying high-voltage switching-frequency CM voltage across multiple isolation barriers of auxiliary circuits. Therefore, the key objective of the current article is to significantly attenuate the CM voltage present between the inverter output terminals and the DC-bus terminals. The focus of this work is not to attenuate the CM switching noise appearing at the inverter terminals.

In this paper, we present an ESS utilizing a non-isolated split-phase inverter that is used to generate off-grid AC voltage with grounded neutral phase without the use of a low-frequency (LF) transformer. In the proposed inverter circuit, a passive filter comprising differential-mode inductors and split DC-bus capacitors is introduced to attenuate the high-frequency CM voltage. The common point of the split capacitor network is connected to the neutral phase of AC. The split DC-bus capacitors are the only addition to the conventional inverter circuit. These capacitors along with the differential-mode filter inductors form a second-order filter for the CM voltage, with corner frequency much lower than the switching frequency. Since the magnitude of the high-frequency component of the CM voltage is attenuated, the magnitude of the circulating ground currents is significantly reduced. The reduction in the magnitude of high-frequency currents due to the introduction of passive filters results in reduced EMI emissions, losses, longer life for the isolation components, etc.

2. Proposed Inverter Circuit and Its Analysis

The conventional three-leg inverter, as shown in Figure 1, is used for generating split-phase AC voltage and is driven by using the sinusoidal pulse width modulation (SPWM) technique. The modulating signals used for SPWM are shown in Figure 2. Leg-1 ($S_1$ and $S_2$) and Leg-3 ($S_5$ and $S_6$) of the inverter are switched with sinusoidal modulating signals that are ${180}^{\circ }$ apart. These two legs are responsible for generating the two phase voltages, whereas Leg-2 ($S_3$ and $S_4$) is switched with a constant duty cycle of $0.5$. The primary purpose of the high-frequency-switched neutral leg is to provide a path for the unbalanced current [18,19,20,33]. The switching voltages appear at switching nodes $S_A$, $S_B$, and $S_C$ with respect to the negative terminal of the DC bus (marked by point E). The voltage waveform between the neutral (denoted by A) and E (denoted by $v_{CM}$) has a common-mode switching component of the three legs [13,35,36]. This voltage waveform can typically have three voltage levels, as shown in Figure 3a. When the neutral point of the inverter is connected to earth ground, all the other circuits in the system that are referenced to earth ground, such as the control systems, gate drive circuits, APS, etc., experience the high-frequency switching component of the CM voltage. One of the main effects of this CM voltage appearing across any isolation barrier is that currents of significant magnitude flow in the ground loops. The leakage currents in the ground loop appear due to the high-frequency CM voltage appearing across the neutral and the negative terminal of the DC bus. The CM voltage has a quasi-square voltage waveform, as shown in Figure 3a, consisting of four levels. The four levels of the square waveform are 0 V, ${\displaystyle \frac{1}{3}}{V}_{DC}$, ${\displaystyle \frac{2}{3}}{V}_{DC}$, and $V_{DC}$, which appear for different time durations in a switching cycle throughout the line cycle. The average value of the CM voltage is ${\displaystyle \frac{V_{DC}}{2}}$ in each switching cycle. The switching-frequency component of the CM voltage is filtered by the addition of the proposed split DC-bus capacitors, $C_{s1}$ and $C_{s2}$, between the neutral and DC-bus terminals, as shown in Figure 3b. These capacitors, together with the filter inductors, form a second-order filter for voltage $v_{CM}$. The values of the capacitors are chosen such that this filter provides a significant decrease in the high-frequency component of voltage $v_{CM}$. As a result, this voltage contains an AC component of small magnitude and a significantly high DC component. Since the neutral leg is always switched with a duty cycle of $0.5$, the voltage of the middle point of the split capacitors is forced to remain at a voltage level of $0.5V_{DC}$. The middle point voltage of the split DC-bus capacitors does not drift over time, as there is no load across the split DC-bus capacitors. These capacitors are used for filtering high-frequency voltage $v_{CM}$. Therefore, the middle point of the capacitor ties earth ground to a DC voltage level with respect to point E, i.e., earth ground is tied to $0.5V_{DC}$. Consequently, the voltage across the isolation barrier is effectively DC voltage, thereby achieving a significant reduction in the magnitude of the switching-frequency current flowing through the isolation capacitance.

The conventional inverter of Figure 1 is operated with the SPWM technique (as shown in Figure 2), which generates AC voltages $v_{c1}$ and $v_{c2}$ across the load terminals. However, CM voltage $v_{CM}$ across points A and E is a quasi-square wave at the switching frequency, $f_s$. The duration of each level of this quasi-square wave depends on its position in the line cycle. The switching action of the inverter causes the instantaneous voltage, $v_{CM}$, to change. Thevenin’s equivalent of the CM circuit of the conventional inverter is shown in Figure 3c. Assuming that the inductance connected with all three legs is equal, i.e., $L_A=L_B=L_C=L$, the CM voltage is given by

$$v_{AE}=v_{CM}={\displaystyle \frac{S_A+S_B+S_C}{3}}{V}_{DC},$$

(1)

where $S_x\in \{0,1\}$ is the switching function of each inverter leg and $x\in \{A,B,C\}$. The function $S_x=1$ when the top switch is on, and $S_x=0$ when the bottom switch is on. Therefore, the voltage at the neutral point produces a quasi-square wave voltage, as shown in Figure 3a. The worst-case condition appears near the zero crossings of the AC voltage, where it is a square wave. The magnitude of this square wave is ${\displaystyle \frac{V_{DC}}{2}}$, and it has an offset voltage of ${\displaystyle \frac{V_{DC}}{2}}$. The magnitude of the fundamental component of the square wave is given by $2{\displaystyle \frac{V_{DC}}{\pi }}$. Thevenin’s impedance can be calculated by replacing all voltage sources with a short circuit and all current sources with an open circuit, and calculating the equivalent impedance in the remaining circuit. By doing so, the equivalent inductance is determined as

$$L_{CM}={\displaystyle \frac{L}{3}}.$$

(2)

The equivalent CM circuit of a conventional inverter is shown in Figure 3c. As shown by the dotted lines in this diagram, if the neutral point is grounded, the isolation capacitance appears in series with the CM inductance. The total impedance for the CM currents is thus given by

$$Z_{CM}=R_{esr}+j(L_{CM}{\omega }_s-{\displaystyle \frac{1}{{\omega }_s{C}_{iso}}}),$$

(3)

where $R_{esr}$ is the equivalent series resistance of the CM circuit (not shown in the circuit diagrams) and ${\omega }_s$ is the angular switching frequency. Since the inductance of the inverter is fixed, the magnitude of the impedance for the CM currents varies directly with the value of the capacitance, $C_{iso}$, until the natural resonant frequency, ${\omega }_r$, is greater than the switching frequency (i.e., ${\omega }_r>{\omega }_s$), where

$${\omega }_r=\sqrt{{\displaystyle \frac{1}{L_{CM}{C}_{iso}}}}.$$

(4)

The CM current, $i_{CM}$, is given by

$$i_{CM}={\displaystyle \frac{v_{CM}}{Z_{CM}}}.$$

(5)

The magnitude of the CM currents increases with the isolation capacitance when ${\omega }_r>{\omega }_s$. Therefore, there are two methods to reduce the magnitude $i_{CM}$: either reducing the capacitance of the isolation barrier significantly, which can be an expensive solution, or reducing the magnitude of the high-frequency voltage appearing across it. The latter solution is implemented by the introduction of the split DC-bus capacitors.

The integration of split DC-bus capacitors into the split-phase inverter circuit, as illustrated in Figure 4, introduces a large capacitor in parallel with the isolation capacitance. The CM equivalent circuit gets modified as shown in Figure 3d. The parallel combination of the capacitors, $C_{s1}$ and $C_{s2}$, is added in parallel with the isolation capacitance $C_{iso}$. The equivalent capacitance, $C_{eq}$, is the total capacitance that appears in the CM equivalent circuit of Figure 3d, and its value is given by

$$C_{eq}={\displaystyle \frac{C_{s1}{C}_{s2}}{C_{s1}+C_{s2}}}+C_{iso}.$$

(6)

The additional capacitors, $C_{s1}$ and $C_{s2}$, are selected large enough such that ${\omega }_r<<{\omega }_s$ and the CM impedance becomes inductive at the switching frequency of the inverter. The split DC-bus capacitors behave as a DC-blocking capacitor. In this case, the neutral point voltage $v_{CM}$ is governed by the voltage across capacitor $C_{s2}$. From an alternative point of view, the high-frequency CM voltage, $v_{CM}$, is filtered by the second-order filter formed by inductors $L_A$, $L_B$, and $L_C$, and the split DC-bus capacitors, $C_{s1}$ and $C_{s2}$, as shown in Figure 4. Moreover, the modified CM equivalent circuit shows that the second-order filter is formed by the common-mode inductance, $L_{CM}$, and the equivalent capacitance, $C_{eq}$, where the equivalent capacitance is much larger than the parasitic isolation capacitance of the conventional inverter, i.e., $C_{eq}>>C_{iso}$. Therefore, a significant decrease in the high-frequency component of voltage $v_{CM}$ is achieved. Assuming the value of the split DC-bus capacitors to be large enough such that the voltage ripple is negligible, the steady-state value of $v_{AE}$ (which is also the voltage across the equivalent capacitor $C_{eq}$ in the CM equivalent circuit) is given by

$$v_{AE}={\displaystyle \frac{\frac{1}{s{C}_{eq}}}{\frac{1}{s{C}_{eq}}+s{L}_{CM}}}{v}_{CM}$$

(7)

By simplifying the above expression, (7) becomes

$$v_{AE}={\displaystyle \frac{{\omega }_r^2}{s^2+{\omega }_r^2}}{\displaystyle \frac{(S_A+S_B+S_C)}{3}}{V}_{DC},$$

(8)

where

$${\omega }_r={\displaystyle \frac{1}{\sqrt{L_{CM}{C}_{eq}}}}.$$

(9)

The values of capacitors $C_{s1}$ and $C_{s2}$ are chosen such that the resonant frequency of the second-order filter, ${\omega }_r$, is at least a decade lower than the switching frequency, thereby providing a significant decrease in the switching-frequency component of the CM voltage. As a result, this voltage contains an AC component of small magnitude and a significantly high DC component. Consequently, when the neutral terminal is grounded, the voltage across the isolation capacitance of the power supplies is effectively DC voltage. Due to the reduced magnitude of the switching-frequency component of the voltage, $v_{CM}$, the high-frequency current flowing through the isolation capacitance also decreases. Moreover, only a fraction of the total CM current flows through the isolation capacitance, due to the presence of large split DC-bus capacitors.

2.1. Key Circuit Waveform for Additional Split DC-Bus Capacitance

The addition of a large capacitor at the neutral terminal of the inverter not only suppresses the switching-frequency component of the CM voltage but also generates a constant voltage source with a magnitude half that of the DC-bus voltage. Due to the presence of DC-bus voltage connected to the neutral terminal of the AC, the peak-to-peak value of current ripple through the three inductors is given by

$$\Delta i_{LA}={\displaystyle \frac{(V_{DC}-v_{AE}-v_{C1})}{L}}{D}_A{T}_s,$$

(10)

$$\Delta i_{LC}={\displaystyle \frac{(V_{DC}-v_{AE}-v_{C2})}{L}}{D}_C{T}_s,\mathrm{and}$$

(11)

$$\Delta i_{LB}={\displaystyle \frac{(V_{DC}-v_{AE})}{L}}{D}_B{T}_s.$$

(12)

Figure 5 shows the gate drive signals for the three legs and the corresponding current through the three inductors. The operation of the circuit can be further subdivided into six subsections. In each subsection, the slope of the current through one of the inductors changes. The current $i_{nn}$ flowing between the neutral terminal and the middle point of the split capacitor is the sum of the current ripple values in all three inductors. Consequently, the slope of current $i_{nn}$ changes in each sub interval. A typical waveform for current $i_{nn}$ is shown in Figure 5. The current ripple in all three inductors consist of a switching-frequency component, unlike the conventional inverter, where the current ripple in the inductors is at twice the switching frequency.

2.2. Voltage Ripple on Neutral Terminal

Even though the switching-frequency component of the voltage on the neutral terminal is significantly attenuated, it contains finite voltage ripple due to the presence of current ripple in $i_{nn}$. The maximum magnitude of the voltage ripple appears at the zero crossing of the line voltage, where the duty cycle of all three legs is $0.5$. The peak-to-peak value of the current through the inductor in the three legs is given by (10)–(12). Assuming the voltage ripple on capacitors $C_{s1}$, $C_{s2}$, $C_1$, and $C_2$ to be small compared with the DC component, the current, $i_{nn}$, in the neutral line from node A to node B can be given by

$$\Delta i_{nn}=\Delta i_N+\Delta i_{L1}+\Delta i_{L2}$$

(13)

Assuming the DC-bus capacitor to be large, such that the DC-bus voltage remains constant during a switching cycle, and $C_{s1}=C_{s2}=C$, the current through each capacitor is equal, i.e.,

$$C{\displaystyle \frac{d{v}_{AE}}{dt}}=-C{\displaystyle \frac{d(V_{DC}-v_{AE})}{dt}}={\displaystyle \frac{i_{nn}}{2}}.$$

(14)

The worst-case situation is near the zero crossings of the AC voltage where the duty cycle of all three legs is $0.5$. In this situation, the peak-to-peak value of current $i_{nn}$ during the time in which the top switches of the three legs are turned on is given by

$$i_{nn-pp}=3{\displaystyle \frac{V_{DC}{T}_s}{4L}}.$$

(15)

The total value of charge delivered to capacitor $C_{s2}$ is given by

$$q_{cs2}={\displaystyle \frac{1}{2}}\times {\displaystyle \frac{i_{nn-pp}}{4}}\times {\displaystyle \frac{T_s}{2}}=3{\displaystyle \frac{V_{DC}{T}_s^2}{64L}}.$$

(16)

Corresponding to charge $q_{cs2}$, the change in voltage on the capacitor is given by

$$\Delta v_{AE}=3{\displaystyle \frac{V_{DC}{T}_s^2}{64LC}}.$$

(17)

The value of $\Delta v_{AE}$ obtained above is negligible compared with the DC component of voltage $v_{AE}$ in the proposed circuit with split capacitors. Another source of CM currents is the coupling of the switching noise with the parasitic capacitance of the insulating materials.

On the other hand, a second-harmonic voltage ripple appears at the middle point of the split DC-bus capacitors in the case of heavy load at the inverter terminals. The split-phase load (balanced or unbalanced) consumes power that has a DC component superimposed by a second-harmonic component. This power is delivered by a DC voltage source. Consequently, the power delivered by the DC voltage source consist of a second-harmonic component which appears in its entirety in the current through it. A small portion of the DC-bus current, especially the second-harmonic component, passes through the split DC-bus capacitors due to their filtering action for DC-bus voltage. This second-harmonic current passing through the split capacitor branch develops a second-harmonic voltage at the middle point of the DC-bus capacitors. The presence of second-harmonic voltage on the neutral leg can cause it to also appear at the inverter output terminals. However, the second-harmonic voltage at the inverter terminals can be significantly attenuated by using closed-loop control incorporating a second-order generalized integrator (SOGI), a proportional–resonant (PR) controller, or other harmonic elimination algorithms.

2.3. Bode Plots and Insertion Loss Analysis

The bode plot of the proposed CM filter and the parasitic filter present in the conventional inverter circuit are shown in Figure 6. The plot characteristics are described by (8). In the case of the conventional inverter, only the parasitic capacitor ($1-20nF$) appears in the CM circuit, and as a result, the natural resonant frequency, ${\omega }_r$, of the CM filter is much higher than the switching frequency. The switching-frequency component of the CM voltage is not attenuated by this parasitic filter. Therefore, the parasitic capacitor, $C_{iso}$, experiences un-attenuated CM voltage at switching frequency, whereas when the split DC-bus capacitors are introduced, the ${\omega }_r$ of the CM filter is reduced significantly. The capacitance value of the split DC-bus capacitors is chosen such that the ${\omega }_r$ of the filter is approximately ten times lower than the switching frequency. In this scenario, the switching-frequency component is attenuated by approximately 100 times due to the filter being a second-order filter.

In order to quantify the quality of the proposed CM filter that utilized the DM inductors, insertion loss analysis is performed. The insertion loss due to the addition of the proposed passive filter is given by

$$IL=20lo{g}_{10}\left|{\displaystyle \frac{V_{CM}}{V_{AE}}}\right|.$$

(18)

Assuming the fundamental harmonic approximation, the insertion loss due to the parasitic capacitance of insulation is 0 dB, whereas by introducing the proposed filter, the insertion loss can be found by inserting the values of $V_{CM}$ and $V_{AE}$ from (1) and (8) into (18):

$$IL=20lo{g}_{10}\left|{\displaystyle \frac{s^2+{\omega }_r^2}{{\omega }_r^2}}\right|.$$

(19)

3. Simulation and Experimental Results

Simulation and experimental studies were conducted on a 12 kW three-leg full-bridge inverter prototype. A DC-bus voltage of around 400–500 V was used to generate a sinusoidal 240 V/120 V, 60 Hz AC voltage. The experiments were performed with balanced split-phase resistive loads ($R_{L1}$ and $R_{L2}$) connected to the inverter AC terminals. However, the type of load connected to the inverter, i.e., resistive, inductive, or capacitive, does not affect the CM voltage waveforms, as the load does not appear in the CM equivalent circuit (as shown in Figure 3b). Only those elements that are connected between the AC terminals and DC-bus terminals participate in the common-mode circuit. The major circuit parameters are listed in

Table 1. Converter parameters.

Parameter	Value	Units
DC-bus voltage, $V_{DC}$	450	V
Switching frequency, $F_{sw}$	$38.4$	kHz
Nominal power	12	kW
Inductors, $L_A$, $L_B$, and $L_C$	220	μF
Capacitance, $C_1$ and $C_2$	50	μF
Split capacitance $C_{s1}$ and $C_{s2}$	50	μF
DC-bus capacitance, $C_{DC}$	700	μF
Damping resistors, $R_{c1}$ and $R_{c2}$	$0.5$	Ω
Load resistors, $R_{L1}$ and $R_{L2}$	$2.4$	Ω

. The split capacitors used in the inverter were realized by using a bank of two parallel capacitors (part number MKP1848C62580JP4) for each $C_{s1}$ and $C_{s2}$. The issue regarding the CM voltage, $v_{CM}$, in the conventional full-bridge inverter of Figure 1 is illustrated in Figure 3c. Figure 7a shows a nearly square voltage waveform around the zero crossing of AC voltage. Similarly, Figure 7b shows a stepped voltage waveform near the peak of AC line voltage. The four levels of the waveform are 0 V, ${\displaystyle \frac{1}{3}}{V}_{DC}$, ${\displaystyle \frac{2}{3}}{V}_{DC}$, and $V_{DC}$. In both these waveforms, the current, $i_{nn}$ (pink), is zero, since there is no connection.

After adding the split capacitor with the middle point connected to the neutral of the AC to the conventional circuit, as shown in the circuit diagram of Figure 4, the switching-frequency component of voltage $v_{CM}$ is significantly attenuated. Figure 8a shows the experimental waveforms of the circuit near the zero crossings of the AC voltage. In this figure, the voltage on Ch-1 (dark blue), shows the voltage $v_{CM}$, which contains a DC component of around 225 V (which is $50\%$ of the DC-bus voltage). Ch-2 (pink) shows the current $i_{nn}$ that flows from points A to E. Similarly, Figure 8b shows the waveforms near the peak of AC voltage. In the proposed circuit, there is a switching-frequency CM current that flows through the neutral to the middle point of the split capacitors, while the switching-frequency component of voltage $v_{CM}$ is significantly attenuated.

The switching-frequency current that flows between the neutral terminal of the inverter and the middle point of the split DC-bus capacitors is a result of the CM voltage that appears across inductors $L_A$, $L_B$, and $L_C$. This current contains a negligible DC component and is mainly constituted by a switching-frequency component. Therefore, care must be taken while choosing the conductor to connect the neutral terminal to the DC-bus neutral terminal. In order to minimize the high-frequency losses, litz wire of appropriate size must be used. Furthermore, the capacitors used for implementing the split DC-bus capacitors must be selected such that they have low AC resistance at the switching frequency to keep the AC losses low due to the additional current. Moreover, this current circulates internally, remaining within the inverter; therefore, it does not contribute to the EMI emissions.

Figure 9 shows the comparison of the common-mode component of the conducted EMI as measured in the simulation study of the proposed inverter. The proposed filter provides a decrease of more than 40 dB in the switching-frequency component of the CM signal. The natural resonant frequency, ${\omega }_r$, of the CM filter in the simulation and experimental prototypes was calculated to be 2250 Hz. The value of ${\omega }_r$ is less than ten times that of ${\omega }_s$. Correspondingly, the insertion loss calculated with (19) is around 49.52 dB. Therefore, a significant decrease in the high-frequency common-mode voltage was achieved by introducing only split DC-bus capacitance in the split-phase inverter circuit. Compared to the solution presented in [33], a similar level of attenuation is achieved in the present technique. A key advantage of the proposed technique is that there is no requirement for special modulation techniques, extra power semiconductor devices, and their associated circuitry. On the other hand, the disadvantages of both techniques remain similar in that additional capacitive current appears in the neutral circuit.

Although an improvement in attenuating CM voltage is achieved in the simulation study presented here, the presence of parasitic elements in the inverter components will reduce the amount of attenuation achieved. Multiple parasitic elements were incorporated in the simulation study, such as the capacitance of wire and cable insulation, the parasitic capacitance of semiconductor packaging, and the equivalent series resistance (ESR) of the capacitors (2X capacitor part number R463W515050H7M; $ESR\le$ 5 mΩ) and the inductors (custom inductor with key parameters of 220 μH, 50A_rms, and $ESR$ = 8 mΩ was used). The parasitic capacitance of insulation and component packaging were modeled by a lumped capacitor, $C_{iso}$, as was shown in the Analysis section. The ESR values of the capacitors and the inductor were also modeled by using lumped resistance connected in series with the respective components. A few key parasitic elements that affect CM noise performance, which were neglected in this paper, are the inter-turn capacitance of the inductors, the inductance of the capacitors, the voltage and frequency dependence of the capacitance value of the capacitors, etc. [25].

4. Conclusions

The proposed integration of a split capacitor on the DC bus of a split-phase inverter significantly attenuates the switching-frequency component of CM voltage. As a result, the neutral phase of the proposed transformer-less inverter can be safely connected to earth ground. Since the switching-frequency component of the CM voltage is suppressed to a negligible amount, the magnitude of the ground currents leaking through the insulation and isolation barriers is nearly eliminated. A detailed theoretical analysis of inverter CM circuits with and without split DC-bus capacitors was presented in this paper. The performance of the proposed filter and theoretical analysis of the split DC-bus capacitors was verified by the experimental results of a 12 kW lab prototype.