FPGA Implementation of Nonlinear Model Predictive Control for a Boost Converter with a Partially Saturating Inductor

Abstract

Enhancing power density is a primary objective in electronic power converters. This can be accomplished by employing smaller inductors operating in partial magnetic saturation. In this study, an embedded digital controller is proposed, based on nonlinear model predictive control (NMPC), for the regulation of a DC–DC boost converter, exploiting a partially saturating inductor. The NMPC prediction model exploits a behavioral inductor model that accounts for magnetic saturation and losses and allows the converter regulation while enforcing constraints. The NMPC controller is implemented on a field programmable gate array (FPGA), demonstrating its real-time feasibility while successfully controlling a boost converter operating at switching frequencies up to 80 kHz. Hardware–software co-simulation results show accurate voltage regulation and constraint satisfaction, even under partial magnetic saturation.

1. Introduction

The magnetic saturation of inductor cores leads to a reduction in the material’s permeability as the magnetic field within the core increases. From the perspective of the inductor, this results in a decrease in inductance as current increases—either gradually (as in iron powder core inductors) or abruptly (as in ferrite core inductors). Research has demonstrated that utilizing partially saturated inductors can enhance the power density of power converters, albeit with a slight increase in power loss. The groundbreaking work in [1] illustrates how inductor saturation can be managed in power converters with minimal impact on power consumption. Further studies, including [2,3], provide a more detailed analysis, also considering temperature effects [4].

Designing, simulating, and controlling power converters with partially saturating inductors requires accurate models to predict their operational behavior. Several nonlinear behavioral inductor models are reviewed in [5,6,7]. The range of validity of these models has been extended in [8,9,10] where inductance and power losses are reproduced for different operating frequencies, applied waveforms, air-gap lengths, and core materials.

Model predictive control (MPC), which can be easily implemented on digital circuits [11], is frequently applied to power converters [12,13], offering superior performance compared to traditional model-free proportional–integral (PI) regulators. MPC allows enforcing input and state constraints, particularly important for current limitations (for safety reasons) in power converters. Applications include four-switch, three-phase rectifiers in balanced grids [14] and inverters in unbalanced grids [15,16]. For boost converters, linear MPC is applied in [17], and nonlinear MPC (NMPC) in [18].

Despite these advancements, few implementations consider nonlinear inductance. Various nonlinearities, including magnetic saturation, are addressed in [19], where the inductance of a powder iron core inductor is modeled using an exponential function, and the MPC problem is solved with a fast gradient algorithm, which does not allow imposing current constraints. For ferrite core inductors, ref. [20] introduces an explicit linear MPC controller for a buck converter, relying on a simplified inductor model with step-like inductance and no losses.

In a previous study [21], we exploited nonlinear MPC for the voltage regulation of a DC–DC boost converter by imposing current constraints and using a ferrite core inductor model [9], which represents inductance as an arctangent function of current while accounting for instantaneous losses. This model provides significantly greater accuracy than the simplified approach in [20]. The main limitation of [21] is that only simulation results are proposed, without checking if the technique can be applied to a power converter in real time.

The main novelty of this paper is the FPGA implementation of the technique proposed in [21], which relies on a nonlinear inductor model, for obtaining an embedded real-time controller. This requires the use of limited hardware resources with tight constraints on the circuit latency. Proper algorithms should be therefore adopted for both the nonlinear programming and the numerical integration of the system for prediction. Moreover, fixed-point data representation is mandatory to fulfill real-time constraints.

Several FPGA-based linear MPC implementations are surveyed in [22]. Concerning NMPC on FPGA, different algorithms have been applied, including particle swarm optimization [23,24], mesh adaptive direct search (MADS) [25], and gradient-based techniques [26,27,28]. To perform the optimizations required by the NMPC approach, we chose the MADS algorithm, a zero-order method that does not require the evaluation of derivatives of the cost function. As shown in [25,29,30], it is particularly suitable for microcontroller and FPGA implementations, especially for small-size problems, as considered in this work. Other optimization algorithms suitable for FPGA implementation could be exploited [23,24,26,27,28], possibly leading to lower latency and/or resource occupation. However, MADS proved to be successfully applicable, and comparing different optimization techniques in FPGA is out of the scope of this work. To the authors’ knowledge, a digital circuit for real-time control of a power converter that exploits a nonlinear inductor model for prediction is not available in the literature yet. The performances of the proposed circuit are validated through hardware–software co-simulations.

2. Materials and Methods

2.1. Boost Converter Model

We consider the DC–DC boost converter, whose circuit model is shown in Figure 1.

A pulse width modulation (PWM) signal s with frequency f (period $T=1/f$) and duty cycle u is applied to the gate of a MOS transistor that behaves like a switch: when $s=1$ the MOS conducts current (ON phase), through a resistance $R_{MOS}$ that models the conduction losses; when $s=0$ the transistor is an open circuit and the current flows through the diode, with forward voltage drop $v_D$ and conduction resistance $R_D$. A load is represented as a variable current source $I_{out}$, whereas the inductor (enclosed in a dashed rectangle) is modeled through a nonlinear lossless inductor (with differential inductance $L\left(i\right)$, flux linkage $\lambda$, and current i) and two resistors ($R_s$ and $R_p$), accounting for all power losses [21]. We are interested in controlling the converter also when the inductor operates in partial saturation, where the differential inductance $L={\displaystyle \frac{d\lambda }{di}}$ drops as the current increases:

$$L\left(i\right)=L_{sat}+{\displaystyle \frac{L_{nom}-L_{sat}}{2}}\left\{1-{\displaystyle \frac{2}{\pi }}ta{n}^{-1}\left[\sigma \left(\left|i\right|-I\right)\right]\right\},$$

(1)

where parameters $R_s$, $R_p$, $L_{nom}$, $L_{sat}$, $\sigma$, and I are identified starting from experimental measurements of $v_L$ and $i_L$. Specifically, a subset of these measurements is used for model identification, where the model parameters are determined by solving a nonlinear optimization problem. Another subset of the measurements is used for model validation to assess the accuracy of the identified parameters. All details regarding the measurement process, parameter identification, and validation methodology can be found in [21]. Once the model parameters have been identified, by assuming that the current i can be computed as $i=\mathrm{\Gamma }\left(\lambda \right)$, the flux linkage $\lambda$ in the lossless inductor can be evaluated as a function of the current i as

$$\lambda \triangleq {\mathrm{\Gamma }}^{-1}\left(i\right)=\int L\left(i\right){\displaystyle \frac{di}{dt}}dt=\int L\left(i\right)di.$$

(2)

Even if an analytical expression is available for ${\mathrm{\Gamma }}^{-1}$, its evaluation is time- and resource-consuming for an embedded implementation on FPGA. Therefore, 14 couples $(i_j,{\lambda }_j)$, $j=1,\dots ,14$ are stored in a look-up table (LUT), and functions $\mathrm{\Gamma }$ and ${\mathrm{\Gamma }}^{-1}$ are computed through linear interpolation.

Because of the fixed-point embedded implementation of the controller, it is convenient to refer to normalized dimensionless quantities. Therefore, we define $\widehat{v}={\displaystyle \frac{v}{V_{max}}}$, ${\widehat{V}}_{in}={\displaystyle \frac{V_{in}}{V_{max}}}$, ${\widehat{v}}_D={\displaystyle \frac{v_D}{V_{max}}}$, $\widehat{\lambda }={\displaystyle \frac{\lambda }{{\mathrm{\Lambda }}_{max}}}$, $\widehat{𝚤}={\displaystyle \frac{i}{I_{max}}}={\displaystyle \frac{\mathrm{\Gamma }\left(\lambda \right)}{I_{max}}}={\displaystyle \frac{\mathrm{\Gamma }\left({\mathrm{\Lambda }}_{max}\widehat{\lambda }\right)}{I_{max}}}\triangleq \widehat{\mathrm{\Gamma }}\left(\widehat{\lambda }\right)$, ${\widehat{𝚤}}_L={\displaystyle \frac{i_L}{I_{max}}}$, ${\widehat{I}}_{out}={\displaystyle \frac{I_{out}}{I_{max}}}$. Coefficients $V_{max}$, $I_{max}$, and ${\mathrm{\Lambda }}_{max}$ are set so that the normalized variables never exceed 1 during the converter operation.

Unlike [21], where i was considered a state variable, here we set the system state as $x=[\widehat{\lambda },\widehat{v}]$. The input is u, whereas the vector of measurable parameters is $p=[{\widehat{V}}_{in},{\widehat{I}}_{out}]$. According to these choices, the continuous-time normalized equations of the boost converter (see Appendix A for the details) are:

$${\displaystyle \frac{dx}{dt}}=F(x,u,p)=\left\{\begin{array}{c}\left[\begin{array}{c}{\displaystyle \frac{R_p{V}_{max}({\widehat{V}}_{in}-{\widehat{v}}_D-\widehat{v})-(R_s+R_D)R_p{I}_{max}\widehat{\mathrm{\Gamma }}\left(\widehat{\lambda }\right)}{(R_s+R_D+R_p){\mathrm{\Lambda }}_{max}}}\\ {\displaystyle \frac{V_{max}({\widehat{V}}_{in}-\widehat{v}-{\widehat{v}}_D)+I_{max}[-(R_s+R_D+R_p){\widehat{I}}_{out}+R_p\widehat{\mathrm{\Gamma }}\left(\widehat{\lambda }\right)]}{C(R_s+R_D+R_p)V_{max}}}\end{array}\right],\mathrm{if}s\left(u\right)=0\hfill \\ \left[\begin{array}{c}{\displaystyle \frac{R_p{V}_{max}{\widehat{V}}_{in}-R_p(R_s+R_{MOS})I_{max}\widehat{\mathrm{\Gamma }}\left(\widehat{\lambda }\right)}{\left(R_s+R_p+R_{MOS}\right){\mathrm{\Lambda }}_{max}}}\\ {\displaystyle \frac{-I_{max}{\widehat{I}}_{out}}{C{V}_{max}}}\end{array}\right],\mathrm{if}s\left(u\right)=1\hfill \end{array}\right.$$

(3)

and the normalized current $i_L$ is

$${\widehat{𝚤}}_L=G(x,u,p)=\left\{\begin{array}{c}{\displaystyle \frac{R_p{I}_{max}\widehat{\mathrm{\Gamma }}\left(\widehat{\lambda }\right)+V_{max}({\widehat{V}}_{in}-{\widehat{v}}_D-\widehat{v})}{(R_s+R_D+R_p)I_{max}}},\mathrm{if}s\left(u\right)=0\hfill \\ {\displaystyle \frac{R_p{I}_{max}\widehat{\mathrm{\Gamma }}\left(\widehat{\lambda }\right)+V_{max}{V}_{in}}{(R_s+R_p+R_{MOS})I_{max}}},\mathrm{if}s\left(u\right)=1\hfill \end{array}\right.$$

(4)

Figure 2 shows time plots of the normalized voltage across the lossless inductor (upper panel), $\widehat{\lambda }$ (middle panel), and $\widehat{𝚤}$ (lower panel) at steady state. The curves have been obtained by simulating the boost converter model of Figure 1 with the parameters specified in Section 3 using Simulink and the Simscape Electrical library. The k-th PWM period starts at time $t_k=kT$, when s switches from 0 to 1, and ends at time $t_{k+1}=t_k+T$. The duty cycle $u\left(t\right)$ is assumed to be piecewise constant, with value $u\left(t_k\right)\triangleq u_k$ in the k-th period ($t_k\le t<t_{k+1}$). If losses were neglected, the inductor voltage would be a square wave, and the flux linkage would be its integral over time, resulting in a triangular wave. The presence of losses introduces small distortions in both curves. By contrast, current i may be strongly distorted when the inductor operates in partial saturation, due to the nonlinear behavior of the inductance, as shown in the bottom panel.

2.2. Nonlinear MPC

The aim of the NMPC controller is to keep the average (over a period) output voltage v to a reference value $v_{ref}$, while satisfying constraints on the duty cycle and on the inductor current [21], namely $u_{low}\le u\le u_{high}$ and $i_{low}\le {\widehat{𝚤}}_L\le i_{high}$. The distance between the normalized reference voltage ${\widehat{v}}_{ref,k}$ and the average (within the k-th PWM period) output voltage ${\widehat{v}}_{avg,k}={\displaystyle \frac{1}{T}}{\int }_{t_k}^{t_{k+1}}\widehat{v}\left(t\right)dt$ is defined as $\Delta {\widehat{v}}_k={\widehat{v}}_{avg,k}-{\widehat{v}}_{ref,k}$. We also define $\Delta u_k=u_k-u_{k-1}$.

With NMPC, a nonlinear constrained optimization problem must be solved at each PWM period. The cost function to minimize is computed based on a prediction of the system states over a prediction horizon N. The inputs are optimized up to a control horizon $N_u\le N$. Many algorithms are available for nonlinear optimization. Among them, zero-order methods (not requiring the evaluation of derivatives) are the most suitable for an embedded implementation. Here we exploit the MADS algorithm, adapted for a digital implementation [25]. This MADS implementation only requires performing operations whose computation is efficient with fixed-point hardware architectures: sums/subtractions, multiplications, shifts, rounding operations, and comparisons. Of course, the computational complexity and latency of the overall optimization algorithm strongly depend on functions F and G (see Equations (3) and (4)), which are evaluated several times at each algorithm iteration.

At time $t_k$, we use as inputs the measurements of $\widehat{v}\left(t_k\right)$, ${\widehat{𝚤}}_L\left(t_k\right)$, ${\widehat{V}}_{in}\left(t_k\right)$, ${\widehat{I}}_{out}\left(t_k\right)$, the optimal input $u_k^{*}$ predicted by the MPC at the previous step, and the reference voltage ${\widehat{v}}_{ref,k}$. This means that we assume that p remains constant within the interval $NT$ of the prediction horizon. At the beginning, $u_0^{*}=u_{low}$. Current $\widehat{𝚤}=\widehat{\mathrm{\Gamma }}\left(\widehat{\lambda }\right)$ can be computed by rearranging Equation (4),

$$\widehat{𝚤}=\left\{\begin{array}{c}{\displaystyle \frac{(R_s+R_D+R_p)I_{max}{\widehat{𝚤}}_L+V_{max}(-{\widehat{V}}_{in}+{\widehat{v}}_D+\widehat{v})}{R_p{I}_{max}}},\mathrm{if}s\left(u\right)=0\hfill \\ {\displaystyle \frac{(R_s+R_p+R_{MOS})I_{max}{\widehat{𝚤}}_L-V_{max}{V}_{in}}{R_p{I}_{max}}},\mathrm{if}s\left(u\right)=1\hfill \end{array}\right.$$

(5)

Therefore, $\widehat{\lambda }\left(t_k\right)={\widehat{\mathrm{\Gamma }}}^{-1}\left(\widehat{𝚤}\left(t_k\right)\right)$. The $\left(N_u-1\right)$ optimization variables are gathered in a vector $U=[u_{k+1},\dots ,u_{k+N_u-1}]$.

The MADS algorithm is run for $N_{it}$ iterations. The reader is referred to [25] and references therein for a detailed explanation of the MADS algorithm. A summary, for ease of reference, is reported in the following. At each iteration, $2\left(N_u-1\right)$ poll vectors $U^{\left(m\right)}$, $m=1,\dots ,2\left(N_u-1\right)$, are generated, containing entries within bounds $u_{low}$ and $u_{high}$. The poll vectors lie on a mesh, inside a frame [31] (see Figure 3). Each poll vector contains the system inputs within the control horizon, i.e., $u_{k+1},\dots ,u_{k+N_u-1}$. The remaining inputs, up to the prediction horizon, are set as $u_{k+j}=u_{k+N_u-1},j=N_u,\dots ,N-1$. The input sequence can be applied for the integration of system (3), thus obtaining $\widehat{\lambda }\left(t\right)$, $\widehat{v}\left(t\right)$, and ${\widehat{𝚤}}_L\left(t\right)$ (through Equation (4)) up to the prediction horizon. For control purposes, only the values of $\widehat{v}$ and ${\widehat{𝚤}}_L$ at the PWM switching times are relevant. After computing terms $\Delta u_{k+j}$ and $\Delta {\widehat{v}}_{k+j}$, the following cost function J can be evaluated, which penalizes both deviations of $\widehat{v}$ from its reference value and fast variations of u:

$$J=P\Delta {\widehat{v}}_{k+N}^2+\sum _{j=1}^{N-1}\left[R\Delta u_{k+j}^2+Q\Delta {\widehat{v}}_{k+j}^2\right]$$

(6)

Since a progressive barrier approach [32] is exploited, a constraint violation function V must also be computed that is equal to 0 when the current $i_L$ is within $i_{low}$ and $i_{high}$, and grows when the current exceeds the constraints:

$$V=\sum _{t\in \mathcal{T}}\left[{\left(max\left\{0,-{\widehat{𝚤}}_L\left(t\right)+{\displaystyle \frac{i_{low}}{I_{max}}}\right\}\right)}^2+{\left(max\left\{0,{\widehat{𝚤}}_L\left(t\right)-{\displaystyle \frac{i_{high}}{I_{max}}}\right\}\right)}^2\right]$$

(7)

Here, $\mathcal{T}$ is the set of all switching instants within the prediction horizon.

After evaluating all poll points, based on the cost and violation functions, the MADS iteration can be declared successful or not. In the first case, the frame is enlarged and the mesh becomes coarser. In the second case, the opposite happens. A graphical representation (with $N_u=$ 3) of a MADS iteration is shown in Figure 3.

At the end of the optimization, after $N_{it}$ iterations, an optimal solution

$$U^{*}=[u_{k+1}^{*},\dots ,u_{k+N_u-1}^{*}]$$

is obtained. Input $u_{k+1}^{*}$ is applied to the converter at time $t_{k+1}$. A new optimization problem is solved through MADS at time $t_{k+1}$ in a receding horizon fashion, by using $u_{k+1}^{*}$ as a starting input. A timeline of the controller’s operation is shown in Figure 4: analog measurements are acquired at time $t_k$ and converted to digital signals with a certain latency (orange rectangle). The optimization problem is then solved (the latency is indicated with the green rectangle) leading to optimal control $u_{k+1}^{*}$, which is then applied at time $t_{k+1}$. This is different from what was done in [21], where the latency was neglected and the output of the optimization at time $t_k$ was $u_k^{*}$, applied instantaneously to the boost at time $t_k$. We remark that the total latency does not affect the control performance, provided that it remains lower than the system sampling time.

2.3. Numerical Integration of the Model

In [21], system (3) was solved through the ode45 MATLAB R2023b function, with high accuracy. For a real-time embedded implementation, where the execution time is a major constraint, we have to find an alternative solution.

Consider a generic nonlinear dynamical system ${\displaystyle \frac{dx}{dt}}=\mathcal{F}(t,x)$. The explicit midpoint method [33] estimates the state at time $t+h$ as

$$x(t+h)=x\left(t\right)+h\mathcal{F}\left(t+{\displaystyle \frac{h}{2}},x\left(t\right)+{\displaystyle \frac{1}{2}}h\mathcal{F}(t,x\left(t\right))\right)$$

(8)

This requires the evaluation of function $\mathcal{F}$ at two different points.

We applied the midpoint method to the boost converter with $h=uT$. In our case, the function $\mathcal{F}$ is the function $F(x,u,p)$ defined in Equation (3), under the assumption that both u and p are constant within a period, which is consistent with the discussion presented in Section 2.2. Four function evaluations are necessary within a PWM period. For comparison purposes, we exploit both Equations (3), with $\widehat{\lambda }$ as a state variable, and the equations used in [21], where the state variable was $\widehat{𝚤}$. Figure 5 shows voltage $\widehat{v}\left(t\right)$ (top panel) and current $\widehat{𝚤}\left(t\right)$ (bottom panel) obtained with ode45 (black curves) and with midpoint methods by exploiting flux linkage $\widehat{\lambda }$ and current $\widehat{𝚤}$ as state variables (see legend). The integration diverges if state $\widehat{𝚤}$ is used, but good accuracy is obtained with state variable $\widehat{\lambda }$. This is because, as shown in Figure 2, the flux linkage is approximately a triangular wave, whereas the current has a cusp-like behavior. Therefore, within two consecutive integration instants, ${\displaystyle \frac{d\widehat{\lambda }}{dt}}$ is approximately constant, unlike ${\displaystyle \frac{d\widehat{𝚤}}{dt}}$. This is the reason why we chose $\widehat{\lambda }$ as a state variable instead of $\widehat{𝚤}$ as in [21]. Better performance is obtained using more points, at the cost of a higher computation time. The implementation of the midpoint method for the boost converter is detailed in Appendix B.

For solving the optimization problem, the evaluation of the cost function J is the most computationally expensive task, due to numerical integration. Using the midpoint method, the most demanding operation is computing F. The FPGA hardware resources and control algorithm latency strongly depend on the control horizon N, the prediction horizon $N_u$, and the number of MADS iterations $N_{it}$. At each iteration, MADS evaluates the cost function at $2\left(N_u-1\right)$ poll points (see Figure 3), and F is computed $4N$ times for each call to the cost function. In summary, at each sampling time, $N_F$ calls to the function F are required, where

$$N_F=8N_{it}N(N_u-1).$$

(9)

These parameters also affect the control performance, as detailed in the following sections.

2.4. FPGA Implementation

The control algorithm is described in C language through AMD Vitis HLS 2024.2, a high-level synthesis (HLS) tool [34,35], which converts an algorithm coded in C into a fully timed hardware implementation. The workflow consists of the following standard key steps:

• Compilation;
• C simulation through a testbench;
• Register–transfer level (RTL) generation, where the C code is translated into an RTL description, by scheduling operations, binding resources, extracting control logic, and defining external communication;
• RTL synthesis, which converts the RTL description into a gate-level netlist;
• RTL simulation through a testbench;
• Implementation, where the netlist is placed and routed onto device resources, within the logical, physical, and timing constraints.

Directives can be applied to guide the RTL synthesis process starting from the C code. In particular, in most loops we applied pipelining, which is a common practice in digital design to increase the throughput by overlapping sequential arithmetic operations, at the cost of additional resources. Since the J calculation is the algorithm’s most computationally demanding part, we unrolled all loops inside the cost function, thus performing arithmetic operations in parallel. This potentially reduces the latency but requires additional resources. Moreover, we used the directive

• #pragma HLS allocation operation instances = mul limit = Nmul

to control the hardware resources. This directive limits the number of multipliers generated in the RTL description. Multipliers are implemented in dedicated digital signal processing slices, which are a limited resource on the FPGA. Therefore, increasing their number can reduce the computation time required by the algorithm, at the cost of using more hardware resources.

A fixed-point data representation is used, through data type <ap_fixed>. Normalized inputs $\widehat{𝚤}$, $\widehat{v}$, ${\widehat{V}}_{in}$, ${\widehat{I}}_{out}$ and output u are represented as unsigned 12-bit numbers with 0 bit of integer part. All internal variables are signed numbers with a variable number of bits for integer and decimal parts, to avoid overflow problems.

We use a Zynq-7000 XC7Z020-1CLG484C FPGA, with a clock frequency of 100 MHz, embedded in a Digilent Zedboard. With the board being equipped with 18-bit multipliers, all multiplications are performed between 18-bit numbers.

3. Results

3.1. Hardware–Software Co-Simulations

The block scheme of the complete system is shown in Figure 6. Measurements of $v,i_L,V_{in}$, and $I_{out}$ collected on the boost converter are scaled to the voltage range of the analog-to-digital (ADC) converters through, e.g., an analog printed circuit board. The scaling should be such that the maximum voltages $V_{max}$ and current $I_{max}$ map into the maximum ADC voltage value. This way, the digital output of the ADC converters can be interpreted as a fixed-point number with all bits dedicated to the decimal part, leading to the normalized values $\widehat{v},{\widehat{𝚤}}_L,{\widehat{V}}_{in}$, and ${\widehat{I}}_{out}$. These signals enter the NMPC block running the MADS algorithm. The reference voltage ${\widehat{v}}_{ref}$ can be provided as a digital input through, e.g., a serial port. The resulting optimal duty cycle value u is provided to a PWM generator and brought to the gate of the MOS transistor (through a proper driver).

In our implementation, only the NMPC block (green) is implemented in the Zynq FPGA. All the other components in Figure 6 are simulated through Simulink R2023b. AMD Vitis Model Composer [36] is exploited to perform this hardware–software co-simulation. Figure 7 shows the adopted setup, with the Zedboard connected to a PC running Model Composer, through a USB cable.

The boost converter is modeled using the Simscape Electrical library (see Figure 6). The models of semiconductor devices are based on real components: the Infineon MOSFET IAUC60N04S6L039 [37] and the Infineon diode IDW30E65D1 [38]. A model of the gate driver for the transistor is also included. The MOSFET is modeled using the SPICE netlist provided by the manufacturer, whereas the diode is modeled based on the forward current-voltage curve provided in the datasheet. These models are more accurate than the ones used for MPC prediction, only accounting for conduction resistances $R_{MOS}$ and $R_D$ (see Figure 1).

All considered parameters are listed in

Table 1. System parameters.

Circuit Params.		NMPC Params.
$I_{max}$	5 $\mathrm{A}$	P	128
$V_{max}$	6 $\mathrm{V}$	Q	128
${\mathrm{\Lambda }}_{max}$	80 $\mathrm{\mu }$$\mathrm{Wb}$	R	1
C	100 $\mathrm{\mu }$$\mathrm{F}$	N	5
$R_{MOS}$	4 $\mathrm{m}$$\mathrm{\Omega }$	$N_u$	2
$v_D$	$0.7$$\mathrm{V}$	$u_{low}$	0.2
$R_D$	$0.08$$\mathrm{\Omega }$	$u_{high}$	0.8
$L_{nom}$	$35.9848$$\mathrm{\mu }$$\mathrm{H}$	$i_{low}$	0 $\mathrm{A}$
$L_{sat}$	$0.5340$$\mathrm{\mu }$$\mathrm{H}$	$i_{high}$	3 $\mathrm{A}$
${\sigma }_L$	$1.1704$${\mathrm{A}}^{-1}$	MADS Params.
$I_L$	$2.0973$$\mathrm{A}$	$N_{it}$	7
$R_s$	$0.0462$$\mathrm{\Omega }$	RTL Params.
$R_p$	$1.7722$$\mathrm{k}$$\mathrm{\Omega }$	$N_{mul}$	40
f	50 $\mathrm{k}$$\mathrm{Hz}$

, whereas the piecewise-linear function $\mathrm{\Gamma }\left(\lambda \right)$ is shown in Figure 8, blue curve. The black dashed curve represents the characteristics of a linear inductor. Notice that, as i approaches the maximum value ($i_{high}=$ 3 $\mathrm{A}$), the inductor works in partial saturation and its characteristic drifts apart from the ideal one.

The values of P, Q, and R, as well as the control horizon $N_u$ and prediction horizon N, are selected through a heuristic process of trial and error, as there is no standard method for determining these values [39]. We remark that P, Q, and R have been chosen as powers of 2 for an efficient hardware implementation. The choice of $N_{it}$ and $N_{mul}$ is discussed later in this section.

The digital circuit performance in terms of latency, used digital signal processors (DSPs), flip flops (FFs), and look-up-tables (LUTs) are listed in

Table 2. Circuit performance.

	Synthesis	Place and Route
latency	$16.59$$\mathrm{\mu }$$\mathrm{s}$
$f_{max}$	$60.2$$\mathrm{k}$$\mathrm{Hz}$
DSP	53 (24 %)	53 (24 %)
FF	17,387 (16 %)	8791 (8 %)
LUT	25,802 (48 %)	10,655 (20 %)

, both after the RTL synthesis and the place and route.

We tested the controller in three different scenarios. In the first test, $V_{in}$ is brought from 0 to $1.8$ $\mathrm{V}$ in 1 $\mathrm{m}$$\mathrm{s}$ (converter startup). Then, it is increased to $2.1$ $\mathrm{V}$ and decreased again to $1.5$ $\mathrm{V}$. The HIL simulation results are shown in Figure 9. The four panels, from top to bottom, show v, $i_L$, u, and $V_{in}$, respectively. Notice that v correctly tracks its reference value (black dashed line) and the transients due to the change in $V_{in}$ last about $1.3$ $\mathrm{m}$$\mathrm{s}$ (see inset). The current and the duty cycle never exceeds the constraints (red dashed lines).

In the second test (Figure 10), $I_{out}$ is changed from $0.5$ $\mathrm{A}$ to $0.8$ $\mathrm{A}$, and than back to $0.4$ $\mathrm{A}$. In response to these changes, voltage v exhibits a transient (the first one lasts about $0.5$ $\mathrm{m}$$\mathrm{s}$), after which it returns to its reference value. The inductor current hits both the maximum and minimum values, without exceeding them. The constraint $i_L>0$ prevents the converter from operating in discontinuous conduction mode. The inset shows a cusp-like current waveform, indicating the operation in partial magnetic saturation.

In the last test $v_{ref}$ (black dashed line in the top panel of Figure 11) is changed from $3.3$ $\mathrm{V}$ to 5 $\mathrm{V}$ and then back to $2.7$ $\mathrm{V}$. The output voltage is regulated to its reference value in less than 1 $\mathrm{m}$$\mathrm{s}$. The transient time depends on the fact that the current hits the imposed constraints, in both transitions.

3.2. Comparisons

The NMPC technique used in this paper was already compared to standard proportional–integral controllers in [21], as well as to MPC where the inductor is modeled as a linear component. Here we compare the performance of the controller proposed in [21], with the one implemented in this paper. We remark that this comparison is not between FPGA implementations. Instead, it shows how the changes made specifically for the FPGA implementation—the MADS optimization algorithm, the application of the control action at the next step (see Figure 4), the simplified numerical integration, and the fixed point representation—affect the control performance. The main differences are listed in

Table 3. Main differences between this paper and [21].

	[21]	This Paper
data representation	floating point (64 bit)	fixed point (up to 36 bits)
optimization algorithm	Interior Point (fmincon)	MADS
system integration	ode45	midpoint (ord. 2)
latency	0	$16.59$$\mathrm{\mu }$$\mathrm{s}$
implementation	Simulink	FPGA

.

Figure 12 shows the simulation results in response to a change in $v_{ref}$ obtained in [21] as a benchmark, and the new results obtained with the hardware–software co-simulation, with a different number $N_{it}$ of iterations of the MADS algorithm (see legend). The delay with respect to the benchmark case is mainly due to the fact that the control obtained based on measurements at time $t_k$ is applied at time $t_{k+1}$. Therefore, the control response to a change in $v_{ref}$ is delayed with respect to sampling time. If $N_{it}$ decreases, a suboptimal control is applied, resulting in a larger delay. With $N_{it}=2$, the stationary steady state is not reached, whereas for $N_{it}>7$ there is no significant improvement. With $N_{it}=7$, the delay in v to reach the setpoint is about 100 $\mathrm{\mu }$$\mathrm{s}$.

Increasing $N_{it}$, on the other hand, impacts the circuit latency, as detailed in the next section.

3.3. Circuit Performance

In this section, we show the digital circuit performance in response to changes in some parameters. Figure 13 shows, from top to bottom, the latency of the control algorithm, the percentage of used DSPs, FFs, and LUTs versus value $N_{mul}$ applied to the #pragma directive (see Section 2.4). The latency decreases and the resource occupation increases with $N_{mul}$, as expected. However, for $N_{mul}>40$, the resources continue to grow, but the latency remains constant to about $16.5$ $\mathrm{\mu }$$\mathrm{s}$. For this reason, we chose $N_{mul}=40$ in our implementation.

With $N_{mul}=40$, the RTL synthesis was performed for several combinations of N, $N_u$, and $N_{it}$. For each of them, the latency and the FPGA resource occupation are listed in

Table 4. Latency and FPGA resource utilization for different values of N, $N_u$, and $N_{it}$. The bold line refers to the parameters used in Section 3.1.

N	${\mathit{N}}_{\mathit{u}}$	${\mathit{N}}_{\mathit{it}}$	Latency (µs)	DSP (%)	FF (%)	LUT (%)
4	2	3	6.00	68 (31%)	18,203 (17%)	24,252 (48%)
4	2	5	9.86	68 (31%)	18,205 (17%)	24,254 (48%)
4	2	7	13.72	68 (31%)	18,205 (17%)	24,254 (48%)
4	3	3	7.52	65 (29%)	19,349 (18%)	25,991 (48%)
4	3	5	12.28	65 (29%)	19,351 (18%)	25,993 (48%)
4	3	7	17.04	65 (29%)	19,351 (18%)	25,993 (48%)
5	2	3	7.23	53 (24%)	17,389 (16%)	25,800 (48%)
5	2	5	11.91	53 (24%)	17,391 (16%)	25,802 (48%)
5	2	7	16.59	53 (24%)	17,837 (16%)	25,802 (48%)
5	3	3	8.72	72 (32%)	21,639 (20%)	29,090 (54%)
5	3	5	14.28	72 (32%)	21,641 (20%)	29,092 (54%)
5	3	7	19.84	72 (32%)	21,641 (20%)	29,092 (54%)
6	2	3	8.43	65 (29%)	20,765 (19%)	29,981 (56%)
6	2	5	13.91	65 (29%)	20,767 (19%)	29,983 (56%)
6	2	7	19.39	65 (29%)	20,767 (19%)	29,983 (56%)
6	3	3	10.04	74 (33%)	24,192 (22%)	33,609 (63%)
6	3	5	16.48	74 (33%)	24,194 (22%)	33,611 (63%)
6	3	7	22.92	74 (33%)	24,194 (22%)	33,611 (63%)
7	2	3	9.66	79 (35%)	24,316 (22%)	34,597 (65%)
7	2	5	15.96	79 (35%)	23,418 (22%)	34,599 (65%)
7	2	7	22.26	79 (35%)	23,418 (22%)	34,599 (65%)
7	3	3	11.33	64 (29%)	23,569 (22%)	34,801 (65%)
7	3	5	18.63	64 (29%)	23,571 (22%)	34,803 (65%)
7	3	7	25.93	64 (29%)	23,571 (22%)	34,803 (65%)
10	2	3	13.41	73 (33%)	27,179 (25%)	41,218 (77%)
10	2	5	22.21	73 (33%)	27,181 (25%)	41,220 (77%)
10	2	7	31.01	73 (33%)	27,181 (25%)	41,220 (77%)
10	3	3	15.02	75 (34%)	28,058 (26%)	42,719 (80%)
10	3	5	25.08	75 (34%)	28,058 (26%)	42,719 (80%)
10	3	7	34.96	75 (34%)	28,060 (26%)	42,721 (80%)
13	2	3	17.10	75 (34%)	30,191 (28%)	49,552 (93%)
13	2	5	28.36	75 (34%)	30,193 (28%)	49,554 (93%)
13	2	7	39.62	75 (34%)	30,193 (28%)	49,554 (93%)
13	3	3	19.13	71 (32%)	31,090 (29%)	50,886 (95%)
13	3	5	31.63	71 (32%)	31,092 (29%)	50,888 (95%)
13	3	7	44.13	71 (32%)	31,092 (29%)	50,888 (95%)
15	2	3	19.44	72 (32%)	31,770 (29%)	53,657 (100%)
15	2	5	32.36	72 (32%)	31,772 (29%)	53,659 (100%)
15	2	7	45.08	72 (32%)	31,774 (29%)	53,661 (100%)
15	3	3	21.83	78 (35%)	34,931 (32%)	57,180 (107%)
15	3	5	36.13	78 (35%)	34,933 (32%)	57,182 (107%)
15	3	7	50.43	78 (35%)	34,933 (32%)	57,182 (107%)

. The bold line refers to the parameters used in Section 3.1. Latency increases linearly with $N_{it}$, while resource occupation remains roughly constant. By increasing N and $N_u$, the latency also increases, and the resource occupation tends to grow as well, especially LUT usage, which reaches 100% in the Zynq FPGA for $N=15$. This is due to the number $N_F$ of evaluations of the F function, which is directly proportional to $N_{it}$, N, and $N_u$ (see Equation (9)). We remark that not all parameters’ combinations listed in the table lead to good control performances, as shown in the next section. A unified design of both the control algorithm and the digital circuit is then necessary to meet all specifications.

The effect on control when varying $N_{it}$ has already been discussed in Section 3.2. Here, the controller is tested by varying N and $N_u$. Figure 14 shows some simulation results when $N_{it}=5$, $N_u=2$, and $v_{ref}$ changes as shown in Section 3.1, for both $N=4$ and $N=5$. When $N=4$, the prediction horizon is too short, and the controller is ineffective; i.e., v does not reach $v_{ref}$. If N is sufficiently large—in particular, for $N>4$—the controller is effective. It has been verified that increasing N beyond 5 does not further improve controller performance. Similarly, increasing $N_u$ from 2 to 3 does not impact control performance.

Some latencies in Table 4 are sufficiently low to allow an increase in the converter switching frequency f over 50 $\mathrm{k}$$\mathrm{Hz}$. For example, let us consider the case with $N=7$, $N_u=2$, and $N_{it}=3$, corresponding to a latency of $9.66$ $\mathrm{\mu }$$\mathrm{s}$. In Figure 15, the scenario where $v_{ref}$ changes is shown for converters operating at switching frequencies of 50 $\mathrm{k}$$\mathrm{Hz}$, 60 $\mathrm{k}$$\mathrm{Hz}$, 80 $\mathrm{k}$$\mathrm{Hz}$, and 100 $\mathrm{k}$$\mathrm{Hz}$. Up to 80 $\mathrm{k}$$\mathrm{Hz}$, the controller behavior is almost unchanged, with only a slight difference in the settling time of the converter output voltage (see the inset). At 100 $\mathrm{k}$$\mathrm{Hz}$, the controller is ineffective. In all simulations, the prediction horizon is $N=7$, whereas the sampling time changes with the frequency. With $f=$ 50 $\mathrm{k}$$\mathrm{Hz}$, the controller makes a prediction for the next $N/f=$ 140 $\mathrm{\mu }$$\mathrm{s}$; with $f=$ 100 $\mathrm{k}$$\mathrm{Hz}$, this interval becomes shorter ($N/f=$ 70 $\mathrm{\mu }$$\mathrm{s}$). Although the algorithm latency would allow operation up to $f=$ 100 $\mathrm{k}$$\mathrm{Hz}$, the prediction horizon N is not long enough to ensure acceptable control performance.

4. Discussion

Traditionally, in power converters, inductor saturation is avoided by assuming a constant inductance, enabling straightforward predictions of power losses and current ripple. Under these conditions, both PI (model-free) regulators and model-based controllers, such as MPC, are effective for converter control. When the model is sufficiently accurate, MPC typically outperforms PI controllers by inherently enforcing state and input constraints.

To enhance power density in power converters, smaller inductors and higher switching frequencies can be employed to reduce current ripple and prevent saturation. In such cases, MPC requires an accurate inductor model to predict behavior near saturation. The technique proposed in [21] demonstrates that the nonlinear behavioral inductor model [9] can be effectively integrated into NMPC for voltage regulation in switching converters, even when inductors operate in partial saturation, by enforcing constraints and outperforming standard PI regulators. Conversely, using a conventional inductor model with constant inductance leads to constraint violations. This work makes a step forward with respect to [21], by implementing the NMPC controller on an FPGA and testing it through hardware–software co-simulations. This allows including the effect of data quantization, fixed-point representation, and latency, as well as the possibility to exploit simpler integration methods (e.g., the explicit midpoint) and derivative-free optimization algorithms (e.g., MADS).

This paper provides a proof of concept about the possibility of applying NMPC up to PWM frequencies of about 80 $\mathrm{k}$$\mathrm{Hz}$. It should be noted that the presented results are valid for the specific converter used in this work. When employing a different converter, its dynamics may vary, so the maximum achievable switching frequency may vary. Therefore, the selection of the parameters N, $N_u$, and $N_{it}$ must be evaluated case by case.

The next step will be to apply the embedded controller to a real boost converter.

5. Conclusions

In this work, an NMPC technique for the control of a boost converter with a nonlinear inductor is implemented on an FPGA. The hardware–software co-simulation results show that the embedded controller is able to regulate the converter’s output voltage by fulfilling current constraints, even when the inductor operates at partial magnetic saturation, up to PWM frequencies of about 80 $\mathrm{k}$$\mathrm{Hz}$. Further work will be concerned with the real-time control of a real boost converter, thus assessing its robustness against measurement noise and model inaccuracies.