Designing and Optimizing a 2.4 GHz Complementary Metal–Oxide-Semiconductor Class-E Power Amplifier Combining Standard and High-Voltage Metal–Oxide-Semiconductor Field-Effect Transistors

Abstract

The advent of CMOS power amplifiers has enabled compact and cost-effective solutions for RF applications. Among the available options, switching amplifiers are the most competitive due to their superior efficiency. In this paper, we present the design of a fully integrated 130 nm CMOS class-E RF power amplifier optimized for 2.4 GHz ISM band operations that is compliant with the Bluetooth Low Energy (BLE) standard. The amplifier is based on a cascode configuration with charging acceleration capacitance and a combination of standard and high-voltage (HV) MOSFETs, ensuring optimal performance while maintaining device reliability. To identify the best configuration for the proposed circuit, we first provide an overview of basic class-E amplifier operations and critically review optimization techniques proposed in the scientific literature. This review is complemented by a numerical analysis of the potential advantages of using a combined standard-HV MOSFET structure. Post-layout simulations with parasitic parameter extraction demonstrated that the amplifier achieves 40.85% Power Added Efficiency and 20.52 dBm output power.

1. Introduction

The design of Radio-Frequency (RF) power amplifiers (PAs) is subject to several constraints, including low supply voltages, limited device breakdown voltages, and non-negligible parasitic effects. However, the most critical challenge remains the demand for high efficiency [1]. Among the various technologies available, CMOS has gained prominence in recent years due to its ability to integrate the power amplifier with other system blocks, enabling compact and cost-effective solutions. Yet, this advantage comes at the cost of stringent voltage limitations, which become increasingly severe as technology scales down. These constraints have driven research toward alternative design approaches, leading to the adoption of switching active elements instead of traditional linear ones. This paradigm shift offers the potential for significantly higher efficiency, which, in battery-powered devices, directly translates into extended battery life.

PAs are distinguished into linear and switching amplifiers.

Table 1. Summary of linear and switching PA classes with their main characteristics.

Class	$\mathit{\alpha }$	Max DE	Linearity	Complexity
A	360°	50%	Very high	Low
AB	$[180,360]$°	78.5%	High	Low
B	180°	78.5%	Medium	Low
C	<180°	100%	Medium	Low
D	N.A.	100%	Non-linear	Medium
E	N.A.	100%	Non-linear	Medium
F	N.A.	100%	Non-linear	High

provides a summary of the different PA classes and the key properties that characterize each category.

Classes A, AB, B, and C are linear PAs [2]. Their main feature is that the output transistor is used as a voltage-dependent current source. Therefore, the output signal depends on the input signal envelope. The transistor operates completely or partially in the linear region, between cutoff and saturation (or between cutoff and triode region for MOS devices), and the output waveforms are sinusoids or portions of a sinusoid. Linear PAs are classified according to the angle of conduction $\alpha$ of the active device. In class-A amplifiers $\alpha =360$°, allowing for the best performance in terms of linearity, but not in terms of efficiency, since the device is always on [3,4]. For this reason, class-A amplifiers cannot reach a drain efficiency (DE) higher than 50%. All the other linear PA classes are characterized by a lower conduction angle, i.e., by turning off the device for a portion of the RF cycle. This allows for improved efficiency. However, the linearity is compromised because, when the device is off, the output signal is no longer sensitive to the input signal. If we decrease the conduction angle to 180°, the amplifier is classified as class-B and can achieve up to 78.5% DE [5,6]. Class-B amplifiers are often used in a push–pull configuration [7]. Class-AB amplifiers are characterized by a conduction angle between 360° and 180° [8,9]. Their maximum efficiency is between 50% and 78.5%, depending on $\alpha$. The class-C amplifier is characterized by $\alpha <180$°, and it can achieve a higher DE than the class-B, but at the expense of lower output power and the need for heavy input driving signal [10,11]. However, the large negative swing of the input voltage is a troublesome condition for reverse breakdown, and this is one of the reasons why class-C amplifiers are not the best solution for higher RFs [1].

In switching amplifiers, the transistor operates as an on–off switch rather than as a controlled current source. Theoretically, the active element needs to be driven by a constant amplitude signal like a square wave. The main types of switching amplifiers in the literature are classes D, E, and F. Class-D amplifiers consist of an LCR resonator that is switched between the supply voltage and the ground for alternate half-cycles [12,13]. Therefore, the circuit involves two switching devices, which are often problematic at higher frequencies in terms of parasitic reactances and driver requirements. Therefore, class-D PAs are not very appealing for RFs. Class-E amplifiers call for very simple load networks, composed only of reactive components, and present a single switching device, making it one of the best candidates for high efficiency even for RF applications. Instead, class-F PAs have the voltage across the switch approaching a rectangular waveform, reducing the power loss in the transistor [14]. The load network of a class-F amplifier is usually implemented with two LC tanks that resonate at the second and third harmonics of the working frequency. This configuration is highly complex as it involves a minimum of three inductors, which leads to high power losses and occupies a large die area.

In this paper, we present a detailed overview of the design of a fully integrated 130 nm CMOS class-E RF power amplifier optimized for 2.4 GHz ISM band operations, utilizing a combination of high-voltage (HV) and standard MOS transistors. We begin with a critical review of the fundamental and optimized circuit architectures, with particular emphasis on cascode configurations. This review is followed by an analysis of the circuit’s performance, focusing on the use of standard, HV, and hybrid standard-HV MOSFETs. Based on these considerations, we propose a hybrid standard-HV MOS design that offers the best compromise between performance and reliability. The design is aimed at Bluetooth Low Energy (BLE) standard compliance, with a target output power of 20 dBm, a Power Added Efficiency (PAE) greater than 35%, and a compact layout area. The target amplifier bandwidth is 100 MHz, which is compliant with the BLE standard.

This paper is organized as follows. In Section 2, we offer an overview of the basic class-E operations and the main problems to face during its design, focusing on cascoded configurations. Therefore, we propose a comprehensive and critical revision of the main techniques proposed in the literature to overcome these problems. In Section 4, we discuss the circuit implementation, and we propose an analysis of the use of standard or HV MOSFETs. Section 5 discusses the results of post-layout simulations. Finally, the Conclusions close this work.

2. Class-E RF Power Amplifiers: Basics and Optimization

The architecture of class-E PAs was introduced by Sokal et al. in [15] and then further developed by Raab in [16]. The theoretical efficiency is 100%, therefore converting all the DC power into RF power. However, its practical implementation differs from the ideal results due to the low quality factor of the components, and, in particular, of the inductors, and the non-zero switching time of the transistor. Both aspects cause non-negligible power losses that reduce efficiency [17]. The ideal class-E circuit is shown in Figure 1. The output network is composed of an LC resonator ($L_2$ and $C_2$) tuned at the operating frequency and a shunt capacitor ($C_1$). $L_1$ is an RF choke inductor.

The circuit operation may be described as follows. A square wave with frequency $f_0$ and duty cycle 50% is applied at the input $V_{in}$. When the value of $V_{in}$ becomes high the switch $S_1$ closes, while when the value of $V_{in}$ becomes low, $S_1$ opens, so the switch is repeatedly triggered between on and off states. The opening and closing of the switch that connects the supply to the LC resonator force a sinusoidal current into the load network. The current can only flow through $S_1$ when it is closed, so the capacitor $C_1$ is placed in parallel, giving a path to the current flow also during the off-time of the switch. The theoretical 100% efficiency is due to the fact no parasitic dissipation is introduced by the active element. In fact, during the on-time, the voltage across the switch is zero, while, during the off-time, no current flows through it. Therefore, since power dissipation occurs when both voltage and current are present at the same time, this circuit theoretically does not dissipate any power in the switching device. Figure 2 shows a transient analysis of the switch voltage $V_{sw}$ and current $I_{sw}$ in a circuit with ideal components.

The highest probability of power dissipation is in correspondence of the switch transitions. In the ideal case, those transitions instantly happen, so the voltage and current waveforms do not overlap. In practical applications, however, the switching time is a non-negligible fraction of each period, leading to a larger time window in which voltage and current can be simultaneously present.

According to [15], minimizing power dissipation in this time frame requires tuning the load network so that (i) during switch turn-off, $V_{sw}$ remains low until $I_{sw}$ is reduced to zero, (ii) at switch turn-on, $V_{sw}$ has returned to zero when current starts flowing into the switch, and (iii) the first derivative of $V_{sw}$ is approximately zero at switch turn-on. This tuning prevents major voltage variations in case of a slight mistuning of the load network. Due to these requirements, the values for the components of the class-E load network are found with Sokal’s equations [15]:

$$\begin{array}{cc}\hfill R_L& =0.577{\displaystyle \frac{V_{DD}^2}{P_{out}}}\hfill \\ \hfill L_2& ={\displaystyle \frac{Q_L{R}_L}{2\pi f_0}}\hfill \\ \hfill C_1& ={\displaystyle \frac{1}{5.447·2\pi f_0{R}_L}}\hfill \\ \hfill C_2& =C_1\left({\displaystyle \frac{5.447}{Q_L}}\right)\left(1+{\displaystyle \frac{1.42}{Q_L-2.08}}\right)\hfill \end{array}$$

(1)

where $V_{DD}$ is the supply voltage of the amplifier, $P_{out}$ is the desired output power, and $Q_L$ is the output network loaded quality factor. These equations provide approximate nominal values. Therefore, some tuning is still necessary to achieve the best performance.

The main constraint in designing a class-E PA is the maximum voltage across the switching device. In the literature, the maximum voltage, $V_{pk}$, across the switch is estimated as follows [15,17,18]:

$$V_{pk}=3.56V_{DD}$$

(2)

This is higher than twice the supply voltage, which is the common value for PA circuits. In many practical cases, this voltage is higher than the transistor’s breakdown voltage, limiting the supply voltage value and, consequently, the output power. To keep the same output power level with a single device, from (1) we deduce that we have to lower $R_L$. However, a lower $R_L$ usually leads to a higher impedance transformation ratio of the PA’s load-matching network. A higher impedance transformation ratio negatively impacts the matching network complexity and losses.

2.1. Cascoded Class-E Configurations

The most common solution to the previously described problems is the use of a cascode configuration [19,20,21,22,23,24,25]. Cascoding allows the voltage to be divided by the two MOS devices instead of a single one. In this way, the stress on each transistor is decreased. The cascode configuration allows the device to use almost twice the supply voltage of a normal class-E. According to (1), this means that the load resistance can be four times higher than the single-device case. The bias voltage $V_{bias}$ of the Common Gate (CG) stage becomes another design parameter that affects the performance of the amplifier as it allows a higher current through the stage. This suggests controlling $V_{bias}$ from outside the chip to correct any Process, Voltage, and Temperature (PVT) variations, which may affect the threshold voltage of the transistor.

Despite how this configuration brings many advantages, it has some drawbacks, which are analyzed in detail in [17].

First, the channel ON-resistance $r_{ON}$ is doubled because there are two devices. The losses caused by the channel resistance ($P_{LOSS,r_{on}}$) are related to the load resistance $R_L$ according to the following expression [17,21]

$${\displaystyle \frac{P_{LOSS,r_{ON}}}{P_{out}}}=1.365{\displaystyle \frac{r_{ON}}{R_L}}$$

(3)

Hence, despite the channel resistance being doubled, by increasing $R_L$ by four times, the power losses of the channel resistance are halved compared to the single device topology.

Secondly, another power dissipation mechanism is triggered in the presence of two active devices. Such dissipation is associated with parasitic capacitance, $C_p$, between the drain of $M_1$ and ground, as shown in Figure 3. This capacitor incorporates the effects of the drain–bulk and drain–gate parasitic capacitances of $M_1$, as well as the source–bulk and gate–source parasitic capacitances of $M_2$. The impact of the associated power on efficiency makes the amplifier less efficient compared to the case of a single device, partly nullifying the advantage provided by the increased supply voltage. This power dissipation mechanism occurs when $M_1$ is turned off. When $M_1$ opens, $C_p$ begins charging through $M_2$, which is still on but operating in the triode region. As a result, the current flowing through the switch is low but not zero. When the drain–source voltage of $M_2$ increases, the dissipated power becomes significant.

In addition to the non-ideal switching transitions of the amplifier, the other major cause of power dissipation is the parasitic resistance of the inductors in the circuit. Inductor integration allows for chip compactness and usability in SoC. Nevertheless, it leads to a much lower inductor quality factor Q compared to their discrete off-chip counterparts. Thus, in many cases, some inductors are implemented with off-chip components or with wire bonds, which exhibit higher quality factors.

2.2. Related Works on Cascoded Class-E PAs Optimization

The power dissipation mechanisms described in the previous section reduce the efficiency of class-E PAs. Therefore, there are several solutions aiming to optimize the circuit to minimize losses and increase efficiency. The general trend is trying to turn off $M_2$ when $M_1$ turns off. However, since the $M_2$ gate voltage $V_{bias}$ is fixed, we can only act on $V_{S2}$, which has to increase rapidly after $M_1$ is turned off. In this way, $V_{GS2}$ becomes lower than the threshold voltage of $M_2$ and the transistor turns off. In this section, we briefly explore some state-of-the-art solutions aimed at enhancing overall PA efficiency. Most of them act on the charging of the parasitic capacitance $C_p$, but there are also works that use other methods to improve the PAE of the amplifier.

In [17], Mazzanti et al. proposed adding an inductor, $L_p$, in parallel to $C_p$. By tuning $L_p$ to resonate with $C_p$ at the operating frequency, the impedance from the drain of $M_1$ to ground at $f_0$ is reduced. As a result, $C_p$ charges more rapidly, and $M_2$ turns off faster. This technique also requires a DC blocking capacitor in series with $L_p$. In this case, the quality factor of the inductor is not critical because the power dissipated by the parasitic resistance of $L_p$ is much smaller than the power dissipated by $M_2$. This solution enabled the authors to achieve a 6% improvement in PAE compared to a conventional cascode. However, the disadvantage of this approach is the need for an additional inductor, which presents challenges due to the die area it occupies and the associated resistive losses. Furthermore, the use of the resonator leads to a more limited bandwidth.

Another solution involves introducing an additional current path to accelerate the charging of $C_p$. This approach was proposed in the works of Lee et al. [19], Yamashita et al. [26], and Rumyancev et al. [27]. The additional path consists of a capacitor, $C_a$, placed between the drain and the source of $M_2$, referred to as the charging acceleration capacitor. The value of this capacitance is determined using the following equation:

$$C_1=C_p\left|\right|C_a+C_{p2}$$

(4)

Moreover, Lee et al. proposed to connect the bulk of $M_2$ to its source (BS–cascode) rather than to ground (BG–cascode) [19]. In this way, the same charging acceleration function of $C_a$ is now performed by the drain–bulk parasitic capacitance, without adding another component.

Sowlati et al. [28] proposed a self-biased cascode solution. This topology allows for RF signal swing at the gate of $M_2$, enabling both transistors to experience the same maximum drain–gate voltage. Consequently, the gate voltage of $M_2$ partially tracks the fluctuations of the drain voltage, thereby reducing the peak drain–gate voltage. This reduction allows for a larger signal swing at the drain, leading to improved performance. The DC bias voltage for the gate of $M_2$ is provided by an RC network, which also attenuates the RF power from the drain to some extent. While this configuration results in a reduction in gain performance, it does not impact the output power or the PAE. Additionally, the authors propose an alternative version of the self-biased cascode, incorporating a diode-connected MOSFET at the gate of $M_2$. This configuration enhances the positive swing relative to the negative swing, further lowering the drain–gate voltage. The inductors are implemented using wire bonding to minimize power losses. This amplifier achieves 42% PAE and 23 dBm output power at 2.4 GHz.

Many studies employ a differential configuration, since it allows one to improve the output power and reduce the harmonic distortion [29]. Specifically, Li et al. [21] proposed a three-stage power amplifier (PA) consisting of two driver stages and an output stage. In this work, Dynamic Supply (DS) and Dynamic Cascode Bias (DCB) techniques are combined to enhance drain efficiency, even at low output power levels. A switch is placed at the Common Gate (CG) node to improve isolation when the PA is off. Some of the inductors are implemented on-chip, while others are realized with a combination of wire-bonding and off-chip components. This amplifier achieves a PAE of 43.6% and 20 dBm output power. Despite such advantages, a differential structure requires doubling the majority of the components, therefore leading to a larger die area. Moreover, to use a differential amplifier in a single-ended system, an integrated transformer is usually employed, but in some cases, it can lead to higher power losses [30].

In [22], Du et al. proposed a class-E PA with a current-injection (CI) branch in the output network, implemented via a current mirror to inject a periodic current at the input frequency. This enhances output power without increasing transistor stress. However, two challenges arise: (i) the CI branch requires a supply voltage higher than the drain voltage, which is addressed by using an independent voltage source, and (ii) the injected current may flow toward the supply instead of the load, mitigated by an additional MOSFET between the RF choke and $V_{DD}$. The circuit, comprising driver, power, and CI stages, derives the injection signal from the input with opposite phases. Simulations show that, for equal output power, the PA exhibits a lower maximum drain voltage than a conventional class-E amplifier. With two on-chip inductors, it achieves 38.4% PAE and 14.12 dBm output power, improving PAE and $P_{out}$ but reducing drain efficiency (DE).

Dehqan et al. [23] proposed the floating bulk (FB) technique for class-E power amplifiers. This approach connects the bulk of $M_2$ to ground through a resistor, effectively placing the parasitic capacitances $C_{DB2}$ and $C_{SB2}$ in series. As a result, an additional current path is created during the charging phase of $C_p$, bypassing the drain–source resistance $r_{DS2}$, which is responsible for the slow charging of $C_p$. Consequently, $C_p$ charges more rapidly, leading to a faster turn-off of $M_2$. Additionally, the floating bulk configuration increases the threshold voltage of $M_2$, thereby reducing its drain–source voltage. This reduction mitigates power losses, improving overall efficiency. The inductors in this design are fully integrated on-chip.

In recent years, more advanced processes were able to achieve greater performance. For instance, the design by Liu et al. [31] is able to achieve over 60% PAE. The design is based on a differential configuration. Additionally, in [32], the authors proposed a multi-mode class-E PA, which uses the outphasing technique through multiple branches, switching them on and off to improve efficiency at low power levels.

3. Impact of Standard and HV-NMOS Technologies on Class-E Amplifier Design

In modern circuits, low breakdown voltage is a common limitation. Many IC technologies offer MOSFET variants with higher breakdown thresholds than standard devices. High-voltage (HV) capability is typically achieved through a thicker gate oxide, a longer channel, or both [33,34], as in the technology used in this work. Specifically, this process mandates a minimum channel length of 450 nm for HV-NMOS, exceeding that of standard NMOS, which degrades frequency performance. The breakdown voltage is 2 V for standard NMOS and 5 V for HV-NMOS. In cascoded class-E PA design with HV-MOSFET technology, a key decision is selecting standard or HV-NMOS for the Common Source (CS) and Common Gate (CG) stages. Ref. [17] employs two HV-NMOS to maximize $V_{DD}$, while [28] uses standard NMOS for better RF performance. Ref. [23] adopts a hybrid approach, placing HV-NMOS in the CG stage and standard NMOS in the CS stage.

This work proposes a class-E design using a hybrid NMOS approach, placing HV-NMOS in the CS stage and standard NMOS in the CG stage. To validate this choice, we analyze its benefits by optimizing a baseline class-E configuration and simulating all four transistor–stage combinations. The circuit employs a cascode topology with a charging acceleration capacitor $C_a$ to mitigate losses from parasitic capacitance $C_p$. Additionally, $V_{bias}$ is designed for external control, providing an extra tuning parameter and compensating for PVT variations. We chose to use a single-ended configuration to keep the device compact. To compare the different configurations, we relied on metrics like the PAE and the output power. Linearity analysis was not considered as the class-E PA output stage alone is not responsible for the linearity of the whole system, since it is non-linear by its own definition. In fact, the PA is usually part of a more complex transmission system in charge of restoring the dependence on the input signal envelope [32,35].

The PA was designed according to what was described in Section 2. First, the value of the RF choke $L_1$ was selected through a trade-off between the corresponding reactance at the operating frequency and the resistive losses. A higher-value inductance can block the RF signal more effectively, but larger inductors lead to a larger die area occupation. Moreover, the conductive track must be longer, causing higher resistive losses. Therefore, an initial configuration for the PA is found by calculating the components from (1), by making the hypothesis of dealing with an ideal switch. Hence, the $L_2$-$C_2$ resonator values can be adjusted by reducing $L_2$ and increasing $C_2$. This is useful as the inductor is typically the main source of power losses, as previously discussed. Then, the ideal switch is replaced with a cascade of two MOSFETs, whose dimensions are determined in order to support the maximum current flowing in the switch. Lastly, the capacitance value $C_a$ is added according to (4). It is important to underline that all these steps are performed in parallel with parametric simulations, which allow for the optimization of those values to obtain the least amount of power losses and maximize the PAE and output power. The maximum voltage on the switch $V_{sw}$ needs to be constantly monitored to verify that it is lower than the sum of the breakdown voltages of $M_1$ and $M_2$.

We first analyzed the use of HV-NMOS in both CS and CG stages, which enables the highest supply voltage. The transistors had a channel width W = 10 μm, a channel length L = 450 nm, and a multiplicity = 60. Simulation results are shown in Figure 4. In Figure 4a, it is clear that the output power increases nearly linearly with $V_{DD}$, while the PAE peaks at 3.6 V before declining. Figure 4b shows that transistor voltages remain below the breakdown threshold for $V_{DD}<4.25$ V. However, despite supporting up to 4.25 V, optimal PAE is achieved at 3.6 V, limiting the HV-NMOS advantage.

The standard NMOS, with its shorter channel, offers better performance than HV-NMOS, despite having a lower breakdown voltage. In particular, the simulated standard MOSFETs had the same channel width and multiplicity, but with a channel length L = 130 nm. For the same supply voltage, a class-E amplifier with standard NMOS outperforms one with HV-NMOS. However, the breakdown limit often forces the designer to use a lower supply voltage. For this analysis, the circuit has been configured for a lower supply voltage. Simulation results for a class-E amplifier with two standard NMOSs are shown in Figure 5a,b.

We can observe that the breakdown threshold allows for a maximum supply voltage of 1.3 V. For this value of $V_{DD}$, a higher PAE is achieved compared to the previous case, but the output power is significantly lower. Thus, this configuration also has significant limitations.

Based on these results, the optimal solution is a hybrid amplifier that combines the benefits of both configurations, leveraging each transistor type’s strengths while maintaining reliability. This can be achieved using a hybrid configuration with one standard NMOS and one HV-NMOS. Two possible arrangements are standard NMOS in the CS stage and HV-NMOS in the CG stage, referred to as Hybrid Combination 1 (HC1), and HV-NMOS in the CS stage and standard NMOS in the CG stage, referred to as HC2.

Reducing the $r_{ON}$ of the CG stage is expected to decrease the amplifier’s power loss. To verify this, we conducted a time domain analysis of the power dissipated by the two devices in both configurations, with results shown in Figure 6. From Figure 6b,c, we observe that during the turn-on phase, both configurations show similar behavior, with the HV-NMOS dissipating more power due to the higher $r_{ON}$, regardless of its position in the CS or CG stage. The critical difference occurs during the initial turn-off phase, where $V_{D2}\simeq V_{G2}$, causing $M_2$ to operate in the triode region and increase its channel resistance. In this phase, the size difference between the two channels becomes more impactful. Specifically, while the power dissipated by $M_1$ remains similar in both configurations, $M_2$ dissipates more power in the initial part of the turn-off phase in HC1. However, as shown in Figure 6d, the total power dissipation is higher in HC1 during the turn-off phase.

Based on this analysis, we conclude that HC2 performs better in terms of dissipated power. To utilize this transistor configuration, it is essential to control the voltage distribution ratio across the switch, $V_{sw}$, to prevent breakdown issues in the standard NMOS. This ratio can be controlled by adjusting the bias voltage on the CG stage gate and the capacitance $C_a$. A higher $V_{bias}$ shifts more voltage across $M_1$ rather than $M_2$, while a higher value of $C_a$ increases the voltage distribution over $M_1$ instead of $M_2$.

The impacts of these two variables are shown in Figure 7a–d, which show the performance of the device with variation in $C_a$ and $V_{bias}$, respectively. From the simulations, we deduce that, in our case, a configuration that keeps the voltage on each transistor below the breakdown threshold requires $C_a$ = 1.2 pF and $V_{bias}$ = 3 V.

In Figure 8 is shown a performance comparison between the two hybrid configurations.

We can notice that while the output power is similar, the PAE is about 2% higher for HC2. We chose $V_{DD}$ = 3.5 V as supply voltage because it allows us to obtain a PAE close to the maximum while keeping both $V_{M1,MAX}$ and $V_{M2,MAX}$ below the breakdown thresholds.

4. Description of the Proposed Circuit

The final circuit is sketched in Figure 9. The values of the discrete components ($R_L$, $C_1$, $C_2$, $L_1$, $L_2$) were defined by performing several optimizations starting from the values obtained from Sokal’s equations.

The MOS dimensions, instead, must be large enough to support the maximum value of the switch current $I_{sw,MAX}$, which has been evaluated to 173 mA. To handle such a current, all MOSFETs were dimensioned using the maximum channel width W and the minimum channel length L allowed by the technology for each transistor type. Specifically, we used W = 10 μm with L = 130 nm for the standard NMOS transistor and W = 10 μm with L = 450 nm for the high-voltage NMOS transistor. However, setting the maximum width and minimum length in both stages to maximize the current was insufficient to support $I_{sw,MAX}$. Therefore, a multiplicity of 60 for both stages was also required. The final circuit parameter values are summarized in

Table 2. Final values of the parameters of the class-E amplifier.

Parameter	Value
$V_{DD}$	$3.5$ V
$V_{bias}$	3 V
$R_L$	30 $\Omega$
$V_p$	3 V
$C_1$	$0.2$ pF
$C_2$	$2.5$ pF
$C_a$	$1.2$ pF
$L_1$	10 nH
$L_2$	3 nH
$W_{MOS}$  1	10 μm
$L_{MOS,CS}$	450 nm
$L_{MOS,CG}$	130 nm
Multiplicity  1	60

¹ The value is the same for both CS and CG stages.

.

The circuit layout is shown in Figure 10. The process has seven metal layers, and the topmost two have an increased thickness for lower resistivity. The inductors were designed on those layers to reduce the parasitic resistance and improve the quality factor. Two capacitances have been added close to supply lines to provide additional filtering. The dimensions of the chip are 816.5 μm × 804.4 μm, for a total die area of 0.657 mm². The inductors’ design was brought out using electromagnetic simulations.

5. Simulation Results

We performed an electromagnetic simulation of the circuit layout, including parasitic element extraction, with a focus on resistive and capacitive parasitics. This simulation is able to produce results able to predict the behavior of the fabricated chip. The main deviations may impact the MOSFETs threshold voltage due to process, voltage, and temperature (PVT) variations. Nevertheless, those effects can lowered by acting on the CG bias voltage $V_{bias}$ from outside the chip.

Since this work refers to the class-E output stage alone, the simulations assume a square wave input signal at 2.4 GHz with a 3 V amplitude, to emulate the signal coming from a driver stage. The circuit is loaded with a 30 $\Omega$ resistor, identified as the optimal load for maximizing amplifier performance. This load can be matched to the desired value using an external matching network.

To characterize the behavior of the proposed design, we performed Transient simulations and Harmonic Balance (HB) simulations. The PAE was calculated from the HB results as follows. The output power $P_{out}$ is obtained by extracting the first harmonic (f = 2.4 GHz) of the spectral power on the load resistor. The input power $P_{in}$ is obtained by extracting the first harmonic of the spectral power on the input source. The DC supply power $P_{DC}$ is obtained by extracting the DC component (f = 0 Hz) from the spectrum on the DC power supply source. Then, the PAE is calculated as follows:

$$PAE={\displaystyle \frac{P_{out}-P_{in}}{P_{DC}}}$$

(5)

Figure 11a presents PAE and output power as functions of the supply voltage $V_{DD}$, showing that at $V_{DD}=3.5$ V, the amplifier achieves approximately 40.85% PAE and 20.52 dBm output power. Figure 11b illustrates the amplifier’s performance versus the CG gate voltage $V_{bias}$, revealing a decrease in PAE as $V_{bias}$ increases, while output power peaks at $V_{bias}\approx 2.9$ V before declining. A temperature analysis was also carried out, and the results are shown in Figure 11c. It is possible to observe that the PAE and the output power suffer only of a 1.3% and 0.34 dBm change, respectively, in a range from −40 °C to 40 °C. The impact of input square wave amplitude $V_p$ is shown in Figure 12a,b for different $V_{DD}$ values. The performance as a function of frequency is shown in Figure 12c,d, for different values of $C_a$. We can observe that the PAE remains above 40%, and the $P_{out}$ above 20 dBm, in the entire BLE frequency band. Lastly, the time domain waveforms of the input signal $V_{in}$, the output signal $V_{out}$, and the switch voltage $V_{sw}$ are shown in Figure 13a, Figure 13b and Figure 13c respectively, for different values of the supply voltage.

The main parameters by which class-E amplifiers are compared in the literature are PAE, output power, chip area, and supply voltage. Information about the operating frequency and the process must be considered as well.

Table 3. Performance comparison with different class-E implementations.

Ref.	CMOS Process [nm]	Frequency [GHz]	PAE [%]	${\mathit{P}}_{\mathbf{out}}$ [dBm]	Supply Voltage [V]	Chip Area [mm2]	Results Mode	Inductors Type
This work	130	2.4	40.9	20.5	3.5	0.657	Simulated	On-chip
[27]	180	1.9	44	21	3	1.1	Simulated	On-chip and off-chip
[36]	130	2.2	45	28.5	3.3	1.619	Simulated	Off-chip
[17]	280	1.7	67	23	2.5	0.9	Measured	Wire-bond and on-chip
[21]	180	2.45	43.6	20	2.4	2.24	Measured	On-chip, wire-bond and off-chip
[22]	65	1.8	38.4	14.1	1.8	0.95	Measured	On-chip
[23]	180	1.8	52	27	3.3	1.9	Measured	On-chip
[28]	180	2.4	49	24.5	2.4	0.46	Measured	Wire-bond
[37]	180	1.8	51	31.5	3.5	1.0	Measured	On-chip and off-chip

presents a performance comparison between this work and other CMOS class-E PAs operating at similar frequencies, including both simulated and measured results. While the proposed amplifier achieves performance only slightly lower than some of the existing designs, it stands out for its high integration level, incorporating all components on-chip and minimizing die area.

6. Conclusions

In this paper, we analyzed and proposed an architecture for a class-E PA in 130 nm CMOS technology that uses the combination of standard and HV NMOSs. After having presented an overview of the state of the art of class-E PAs, describing the limitations in their design, we discussed the main problems associated to the cascode configuration and the proposed solutions to maximize the performance. Therefore, we demonstrated that a combination of standard and HV-MOSFETs leads to better performance when compared to the use of two transistors of the same type. Moreover, we proved that placing the HV-NMOS in the CS stage is more beneficial than placing it in the CG stage. The simulations showed that the proposed design achieves 40.85% PAE and 20.52 output power at 2.4 GHz, with a 3.5 V supply voltage. The proposed amplifier has a very compact area of only 0.657 mm² and integrates all the required components on the die, except for the output matching network.