A Control Technique for Galvanically Isolated DC–DC Converters with a Single Channel

Abstract

This paper presents an on–off power control technique for galvanically isolated dc–dc converters, which implements a feedback control loop for power regulation on the same isolation transformer used for power transfer. To this aim, the power oscillator is controlled with a PWM scheme, and the control signal is transmitted through the galvanic barrier by using an ASK modulation that acts on the secondary winding of the isolation transformer. The key building block of the proposed architecture is a PLL that allows the reconstruction of the PWM control signal when the power oscillator is turned off and data transmission is disabled. The effectiveness of the proposed power control architecture is validated by designing an isolated dc–dc converter based on a thick polyimide transformer. It complies with reinforced isolation while addressing the power requirements of applications such as low-power sensor interfaces, medical devices, and housekeeping power, e.g., gate drivers or controllers for power converters. At a 20 V output voltage, 110 mW isolated output power is delivered. The dc–dc converter also provides PWM power regulation against PVT variations.

1. Introduction

Galvanic isolation drastically reduces the risk of electric shock to human beings, preventing injuries and ultimately saving human lives. Moreover, it increases reliability for electronics operating in harsh environments, from industry to automotive [1,2,3]. For a decade, semiconductor-based isolation devices, such as isolation capacitors [4] and transformers [5,6], have been widely adopted to implement data/power transfer in highly integrated system in package (SiP) solutions [7]. State-of-the-art isolated dc–dc converters are based on transformers, which exploit the inductive coupling between stacked metal coils to transfer power between a galvanic barrier while preserving efficiency [8,9,10,11,12]. Increasing levels of isolation from basic to reinforced [13] (i.e., from 5 kV to 10 kV) can be provided by using dielectric layers with proper thickness, such as silicon dioxide or polyimide [14,15]. Differently from transformers, isolation capacitors are mainly exploited to implement isolation data channels for bidirectional communications, guaranteeing good area efficiency [16,17,18,19,20].

The traditional architecture of integrated isolated systems, which are widely adopted in commercial products, consists of at least four physical isolation links (i.e., four isolation components) [9,21]. Specifically, for a gate driver application, an isolation link is used to create an isolated power supply, and it is implemented by an isolation transformer, enabling wireless power transfer. Three isolation devices (transformers or capacitors) are used to implement a link for the PWM signal that drives an isolated power switch, a link for the feedback path for power regulation, and a bidirectional data link for diagnostics.

In the last few years, several works have proposed alternative architectures to reduce the number of physical isolation channels with the aim of decreasing the overall size and cost. Data and control signals can be multiplexed and transmitted on the same isolation transformer, as in the triple-transformer architecture proposed in [22]. A further reduction in the number of the physical isolation links is achieved by sharing the signal transformer for output voltage/power regulation and bidirectional half-duplex data communication, as proposed in [23]. Obviously, single-transformer architectures are very attractive for isolated dc–dc converters. A single isolation transformer can be used to transfer both power and data by exploiting an amplitude shift keying (ASK) modulation of the power signal, as proposed in [24]. Unfortunately, this solution is not compatible with output regulation. The work in [25] proposes a galvanically isolated low-power dc–dc converter with multi-channel communication that makes both regulated power and data functionalities compliant on the same isolation transformer link. On the other hand, such a solution is compatible only with continuous time regulation rather than the on/off control scheme typically adopted in dc–dc converters that is mandatory for power efficiency at high power levels. An isolated dc–dc converter enabling full-duplex communication with a single pair of transformers by using 4 frequency shift keying (FSK) communication and secondary side 1X/2X rectification is proposed in [26,27]. However, no closed-loop power regulation is implemented despite the converter being designed for high-power applications.

This paper presents a single-transformer architecture for a galvanically isolated dc–dc converter that enables simultaneous power transfer and output voltage/power regulation using the traditional PWM control scheme for the first time. The proposed power control architecture has been experimentally validated by means of a reinforced isolated dc–dc converter for low-power applications.

This paper is organized as follows. The dc–dc system description is reported in Section 2 and the circuit design is detailed in Section 3. Section 4 describes the experimental validation and compares the results with the state of the art. Finally, Section 5 summarizes the main achievements and conclusions.

2. System Description

The block diagram of the proposed galvanically isolated dc–dc converter is sketched in Figure 1. It is based on a novel architecture patented by the authors with a single isolation link that is simultaneously used for power transfer and output voltage/power regulation. Specifically, the converter is composed of a transformer-based power oscillator (TPO) and a rectifier (Rect), which carry out power transfer across the galvanic isolation barrier from domain A to domain B. On the other hand, the transmission of the control signal in the opposite direction (i.e., from domain B to domain A) is achieved by means of a voltage-to-time converter (VTC) and a transmitter (TX) that performs an ASK modulation on the power signal into domain B, according to the feedback control signal. Conversely, a receiver (RX) along with a control signal reconstruction circuit (CSRC) are implemented into domain A to recover the control signal and properly drive the TPO.

The operating principle of the proposed dc–dc converter is disruptive with respect to traditional control methods despite its simplicity. Looking at the simplified block diagram in Figure 1, the dc output power, P_L, is delivered to the external load, R_L-C_L, thanks to the rectifier. The dc output power is regulated by means of a feedback control loop, which adopts the PWM control scheme, traditionally exploited to maximize power efficiency regardless the power level to be set (i.e., the TPO operates at its maximum drain voltage). Given that a PWM scheme is used, the key point is to guarantee the proper operation of the power regulation when the power signal is off, and no control data can be transmitted. To this aim, the dc output voltage, V_ISO, that determines the power on the load resistance, R_L, is attenuated by a proper factor, k, and compared with a reference voltage, V_REF, thus producing an error signal, V_ε. The VTC converts V_ε after amplification into a PWM control signal, V_{CTR_B}, whose positive time slot, τ, is proportional to V_ε and then strictly related to P_L. An external reference clock, V_{CK_B}, is used to set the frequency of the control signal (i.e., f_{CTR_B} = f_{CK_B}/N) while acting on TX to perform the ASK modulation and hence transmit the bitstream related to V_{CTR_B} across the isolation transformer. Into domain A, the RX recovers both the data, V_{CTR_A}, and clock, V_{CK_A}, signals, which drive the CSRC, turning on and off the power oscillator. The core of the CSRC is a PLL, which performs a sample and hold operation on the recovered clock frequency, f_{CK_A}, thus continuously providing the reference clock in domain A even when the power oscillator is turned off and no data transmission occurs (i.e., V_{CTR_A} and V_{CK_A} are not available). Specifically, during the on phase of the power oscillator, the PLL operates in the closed-loop condition, performing at its output a square wave signal, $\widehat{V}$_{CK_A}, whose frequency is equal to f_{CK_A}. When the power oscillator is turned off, the PLL switches to the open-loop condition, thus holding f_{CK_A} regardless V_{CK_A}. Accordingly, the locked signal $\widehat{V}$_{CK_A} is at first the frequency divided by a factor of N and then exploited as reference clock, V_{CK_FF}, of a positive edge-triggered D flip-flop, D₁, which provides the control signal, $\widehat{V}$_{CTR_A}, to the TPO. Specifically, the D-flip flop is set to V_{DD_A} at the positive edge of V_{CK_FF} and is reset to GND_A at the falling edge of V_{CTR_A}. Therefore, the resulting square wave voltage at the D-flip flop output, $\widehat{V}$_{CTR_A}, is a replica of the original control signal, V_{CTR_B}, thus performing a PWM control of the power oscillator.

The proposed architecture implements for the first time both power transfer and isolated power regulation using the same physical channel. For this purpose, it exploits both ASK modulation on the oscillation power signal to transmit the PWM power control signal from domain B to domain A and a PLL to perform clock recovery in domain A.

3. System Design

The dc–dc converter was designed to deliver an isolated output power of about 100 mW with a 18/20 V output voltage, by exploiting a 5 V power supply, V_{DD_PO}, thus addressing typical gate driver applications. The voltage step-up is achieved by exploiting the turn ratio of the isolation transformer, while output power regulation is implemented thanks to a digital data transmission of the control signal that is performed by means of ASK modulation of the power oscillation, as mentioned before. Power and control signals are transferred from domain A to domain B and vice versa, respectively, using the same isolation link, thus getting rid of an additional isolation channel and reducing system size and cost. In the following, both the power and control functional links are individually detailed by using the related schematics.

3.1. Power Link and Isolation Transformer

The power link is a key function for system operation since it performs power transfer through the galvanic isolation barrier and determines the power conversion efficiency (PCE) of the overall system. A simplified schematic of the power link is shown in Figure 2.

It is basically composed of a transformer-based power oscillator and a full-bridge rectifier, which perform efficient dc–ac and ac–dc conversion, respectively. The power oscillator was fabricated in 0.18 µm BCD technology, which provides high-voltage laterally diffused metal oxide semiconductor (LDMOS) transistors for high power and high frequency operation. Specifically, the power oscillator is operated in class D at 300 MHz to improve power efficiency [28,29] and consists of cross-coupled LDMOS transistors, M_1,2, the LC-resonant tank made up of poly-poly capacitor, C_OSC, and an isolation transformer. Furthermore, the gate terminals of M_1,2 are connected to on–off switches, which are driven by the PWM control signal, $\widehat{V}$_{CTR_A}, thus allowing output power regulation to be achieved by properly turning on and off the power oscillator.

The isolation transformer was implemented in a post-processed polyimide technology [25]. It takes advantage of an Au metal back-end in order to lower transformer winding resistance while reducing losses due to substrate currents (i.e., magnetically induced and vertical displacement currents) thanks to a high-resistivity substrate. Moreover, the thickness of the polyimide layer is as high as 30 μm to guarantee reinforced isolation [7,25,30]. The scanning electron microscope (SEM) cross-section of the polyimide-based transformer is depicted in Figure 3a and its geometrical structure is shown in Figure 3b.

The transformer has a differential stacked configuration that maximizes the coupling factor, k_T, between primary and secondary coils, which is essential to avoid PCE degradation. A high transformer turn ratio was used to step-up the output voltage and, therefore, the geometrical parameters were chosen with the aim of maximizing the overlap between primary and secondary windings.

Table 1. Geometrical parameters of the isolation transformer.

Parameters	Primary Coil	Secondary Coil
Number of turns (n)	3.75	10
Metal width (w) [µm]	37	9.8
Metal spacing (s) [µm]	9.5	9.5
Internal diameter (dIN) [µm]	300	300
Outer diameter (dOUT) [µm]	676	686

presents the geometrical parameters of half of the transformer coils.

Finally, center-tap connections were made available only for primary winding to allow power supply connections of the power oscillator in domain A, while the center-tap bonding wire for the secondary coil was avoided by exploiting a full-wave bridge topology for the rectifier, which allows ground connection in case of undesired electrical discharges. The rectifier chip was fabricated in a 0.13 μm standard CMOS process, providing high-voltage Schottky diodes with sub-GHz operation capability.

The power link was optimized by means of an iterative co-design between the oscillator core and the transformer, which was properly modeled with a lumped scheme [31]. For the sake of completeness, Figure 2 also contains an inset table with the design parameters of the power link.

3.2. Control Link

A simplified schematic of the control link with the main building blocks is reported in Figure 4.

The resistive divider, R₁-R₂, is used to obtain a proper fraction of the isolated voltage, V_ISO, which is compared with the reference voltage, V_REF, thus driving an operational transconductance amplifier (OTA) with the error signal, Vε. A voltage ramp is then produced by injecting the amplifier output current, I_OTA, into the integration capacitor, C_I. This voltage ramp drives a comparator (COMP) that resets a D flip-flop. The duration of the positive time slot, τ, of control signal V_{CTR_B} and hence the on phase of the power oscillator is set by the slope of the voltage ramp. An external clock, V_{CK_B}, drives a divider that imposes the frequency of V_{CTR_B} at f_{CK_B}/N. Time slot τ is here intended as the VTC output signal. It is given by Equation (1):

$$\tau ={\displaystyle \frac{V_{COMP}·C_I}{G_m·V_{\epsilon }}}$$

(1)

where V_COMP is the comparator reference voltage and G_m is the OTA transconductance. As already explained, the TX transmits the control signal across the isolation barrier. To this aim, TX performs PWM coding of V_{CTR_B} by means of an encoder, ENC. The obtained bitstream is then transmitted by exploiting impedance mismatch at the isolation transformer secondary winding through capacitors, C_TX1,2, and MOS switches, M_TX1,2.

The RX block consists of a demodulator, DEM, and decoder, DEC. After the galvanic barrier, it recovers both the data (i.e., V_{CTR_A}) and sampling clock (i.e., V_{CK_A}). The demodulator, which is detailed in Figure 4, is made up of an envelope detector, a Sallen–Key (SK) low-pass filter, an average voltage detector, and a hysteresis comparator. A common drain pair, M_3,4, with the capacitor, C₁, is adopted as envelope detector. It produces the envelope signal, V_ENV. Then, an SK filter (i.e., R₁, R₂, C₂, C₃, and Q_1,2) reduces the high frequency harmonics due to the power oscillator, while preserving the envelope signal. A further low pass filter (R₃ and C₄) extracts the average signal, V_AV, from the SK output voltage, V_SK, which is used by the comparator to produce a rail-to-rail signal, V_BS (i.e., the bitstream), for the decoder.

The latter delivers both V_{CTR_A} and V_{CK_A} at the input of the CSRC block.

As far as the CSRC is concerned, a PLL is exploited to lock f_{CK_A} and hold it during the power oscillator off state (i.e., when data transmission is not available). The PLL embeds a switch, SW, placed at the input of the low-pass filter (LPF) to open the PLL loop simultaneously with the power oscillator turning off. To this aim, SW is driven by $\widehat{V}$_{CTR_A} and freezes the VCO tuning voltage, V_T, into the LPF capacitors when $\widehat{V}$_{CTR_A} goes low, thus maintaining the VCO output frequency $\widehat{f}$_{CK_A} to the value of f_{CK_A}. By properly dividing $\widehat{f}$_{CK_A} thanks to a digital counter, the frequency of the reference clock, V_{CK_FF}, is set equal to f_{CK_A}/N, which is the same frequency as the control signal produced in domain B (i.e., f_{CK_B}/N). V_{CK_FF} is the input clock of the D flip-flop, D₁, which provides the control signal to the TPO. Specifically, the rising edge of V_{CK_FF} sets high $\widehat{V}$_{CTR_A} and determines the oscillator turn-on instant, whereas the falling edge of V_{CTR_A} resets D₁, imposing the duty cycle of $\widehat{V}$_{CTR_A} and hence the turn-on time of the TPO.

The PLL is the key building block of CSRC since it continuously provides an accurate reference clock (i.e., $\widehat{V}$_{CK_A}), which is exploited for the reconstruction of the control signal. Figure 5 shows a simplified schematic of the PLL forward path from the PFD/CP to the LPF made up of resistor R₁ and capacitors C₁ and C₂.

The UP and DOWN outputs of the PFD drive the MOS transistors M₁ and M₂, which implement the switches that enable the CP current generators (i.e., I_CP) to properly charge/discharge the second-order loop filter.

The switch placed between the PFD/CP and the filter is implemented by means of a transmission gate, SW, which exploits a complementary topology to preserve the CP output swing and minimize the charge injected into the loop filter capacitors. As far as the VCO is concerned, a ring oscillator topology is preferred, as depicted in Figure 6.

Specifically, the VCO consists of three current-controlled CMOS inverters along with C_VCO capacitors. Each stage provides a delay related to the voltage swing, V_S, and the slew rate I_VCO/C_VCO, where I_VCO is the bias current of the VCO. Considering the three inverting stages, the oscillation frequency is expressed as follows:

$${\widehat{f}}_{CK\_A}={\displaystyle \frac{I_{VCO}}{6·V_S·C_{VCO}}}$$

(2)

The oscillation frequency is tuned by I_VCO, which in turn is varied by the MOS transistor, M_R. Specifically, M_R mainly operates in triode region performing a variable resistance, R_M, that is controlled by the loop filter output voltage, V_T. Current I_VCO is given in first approximation by:

$$I_{VCO}={\displaystyle \frac{V_{DD\_A}-V_{SG5}}{R_1+R_2//R_M}}$$

(3)

The simulated tuning range of the VCO for typical, minimum, and maximum corners is shown in Figure 7.

The VCO control voltage ranges from 0.4 V to 1.6 V, which are the threshold voltage of M_R and the maximum allowable output voltage of CP, respectively. As is apparent, the VCO provides an oscillation frequency ranging from 3.8 MHz to 21 MHz at the nominal condition. The grey region in Figure 7 highlights the variation in $\widehat{f}$_{CK_A} due to process tolerance. It can be noticed that a range from 9.5 MHz (i.e., minimum corner) to 16.1 MHz (i.e., maximum corner) is guaranteed in the worst case. Therefore, despite the reduction in the frequency control range compared to the nominal condition, the VCO guarantees an oscillation frequency of 12.8 MHz, which is the locked frequency for the PLL. As far as the loop filter is concerned, it was sized to provide a 0.65 MHz PLL bandwidth while guaranteeing a phase margin of around 60°.

Table 2. Main design parameters of the PLL.

Block	Parameter	Value	Unit
Charge pump	ICP	1	µA
Switch, SW	W/LMS_P	470/180	nm/nm
	W/LMS_N	280/180	nm/nm
	R1	290	kΩ
Loop filter	C1	10	pF
	C2	0.5	pF
Voltage-controlled oscillator	CVCO	300	fF
	R1	21.5	kΩ
	R2	77.5	kΩ
	W/LMR	0.28/0.4	µm/µm
	W/LMINV,N	1.4/180	µm/nm
	W/LMINV,P	2/180	µm/nm

summarizes the main design parameters of the PLL.

Finally, an analysis of the stability of the control loop was carried out. To this aim, the simplified model shown in Figure 8 was used along with a single pole approximation for each block.

The open loop gain, T_O, can be written as follows:

$$T_O=k·A_{VTC}·A_{CSRC}·A_P$$

(4)

where k is the resistive partition at the converter output; A_VTC is the gain factor of the voltage-to-time converter; and A_CSRC and A_P are the gain factors of CSRC and power link, respectively. The loop gain transfer function, T(s), was evaluated by considering the main low-frequency contributions. Specifically, they are the pole of the power link at the output (i.e., R_L-C_L) and the delay due to VTC (about equal to the period of the PWM control signal, i.e., t₁ = NT_CK). It is worth noting that the delay due to the PLL was neglected since the PLL locking time was much lower than the delays introduced by other blocks.

$$T(s)=T_O{\displaystyle \frac{e^{-t_{1}s}}{(1+s{R}_L{C}_L)}}$$

(5)

In the worst case, a maximum 40 dB open loop gain, T_O, was set. Therefore, a dominant pole compensation was implemented by sizing the load capacitance, C_L, according to Equation (6):

$$C_L={\displaystyle \frac{T_O{t}_1}{R_L(\frac{\pi }{2}-PM)}}$$

(6)

where PM is the phase margin expressed in radians. A capacitor, C_L, of a few microfarads is sufficient to assure system stability with a 50 kHz PWM control signal.

4. Experimental Results

A micrograph photo of the single-channel dc–dc converter with galvanic isolation is depicted in Figure 9, along with the die size of each chip.

The system was assembled on a customized FR4 printed circuit board (PCB) for full electrical characterization. The proposed architecture is suitable for a highly integrated implementation, either in a two-chip [23] or in a three-chip [25] SiP, depending on the adopted transformer isolation technology [32]. Since the system was designed for a reinforced isolation application, a three-chip implementation was adopted with a separated chip for the polyimide transformer. However, a four-chip solution was used for the experimental demonstration. Specifically, chip A was fabricated in a 0.18 μm BCD technology and housed the low-voltage side circuits (i.e., power oscillator, receiver, and control signal reconstruction circuit), whereas a standalone post-processed isolation transformer (i.e., chip T) was exploited to provide reinforced galvanic isolation. As far as the high-voltage side is concerned, the power rectifier was fabricated in a 0.13 μm CMOS process (i.e., chip R), since it provided high-voltage Schottky diodes. The voltage-to-time converter along with the transmitter in chip B were implemented by using the same 0.18 μm BCD technology for chip A. Moreover, dedicated pads on the PCB were designed to mount the capacitors, C_TX,ext, thus externally setting the modulation index for control data transmission.

Figure 10 shows the simplified block diagram of the adopted measurement setup, which includes a digital oscilloscope for transient measurements and a signal generator to generate the reference clock signal.

Measurements were carried out at 5 V power supply, V_{DD_PO}. An auxiliary 1.8 V power supply, V_{DD_A}, was used for the RX and the power control circuits in chip A. On the other hand, the circuitry in chip B (i.e., the TX and VTC) was supplied by an auxiliary 3.3 V supply voltage, V_{DD_B}, which would be provided in a final implementation by a voltage regulator scaling down the isolated output voltage, V_ISO. The latter was set to 19 V by the integrated power control loop. An external 12.8 MHz clock frequency (i.e., V_{CK_B}) was used as reference to transmit the control bits and generate the internal 50 kHz PWM signal. To this aim, a division factor, N, of 256 was used for both D_B and D_A.

At maximum duty cycle, the system delivered up to 110 mW output power on a load resistance of 3.5 kΩ with a power conversion efficiency of about 17%. It is worth noting that the PCE was mainly affected by the four-chip assembling, which introduced additional losses in the power signal path compared to the three-chip solution. Indeed, the same isolation technology in a three-chip implementation provided a PCE as high as 25%, as reported in [32].

Figure 11 shows the transient response of the isolated voltage, V_ISO, to a step from 17.8 V to 19 V of the reference voltage, V_REF, which corresponds to a variation of the output power, P_ISO, from about 90 mW to 100 mW on a 3.5 kΩ load resistance. The output capacitance, C_L, is fixed to 3.9 μF, which guarantees the stability of the control loop while providing a reduced output ripple. As is apparent, the isolated output voltage is well regulated by the control loop to the external reference voltage, thus demonstrating the effectiveness of the proposed power control technique.

For the sake of completeness, the PWM control signals generated in Chip B and reconstructed in Chip A are also shown in Figure 12, along with the normalized voltage waveform at the drain terminal of the power oscillator. The RF power signal is turned on and off according to the desired output power. Specifically, the control loop imposes the duty cycle of the PWM signal at about 55% to set the steady-state output power to around 60 mW.

Figure 13 and Figure 14 show the normalized RF power oscillation at the rising and falling edges of the PWM control signal, respectively. A modulation index around 10% was chosen to preserve power conversion efficiency.

Figure 15 depicts the input, V_{CK_B}, and RX output, V_{CK_A}, clock signals at domain B and domain A, respectively, within the on phase of the power oscillator. It is worth noting that although V_{CK_A} is not available during the power oscillator off phase, the control signal in domain A is properly reconstructed thanks to the PLL.

Finally, the dc–dc converter performance is summarized in

Table 3. Summarized performance and comparison with state of the art.

Parameters	[23]	[25]	[33]	[34]	This Work
Supply voltage [V]	3.3	5 *	5.5	3.3	5 *
Isolated output voltage [V]	3.3	3.3	4	3.3	20
Max. output power [mW]	93	50	123	165	110
Power efficiency [%]	19	14	23	34	17
Oscillation frequency [MHz]	350	300	≈100	11	270
Control scheme/frequency [kHz]	PWM/100	Continuous time	n.a. **	Open-loop capacitor-based controller	PWM/50
Isolation level	Basic	Reinforced	Basic	Basic	Reinforced
Silicon technology	0.35 μm BCD	0.18 μm BCD, Schottky diode, 0.13 μm CMOS	0.13 μm CMOS	0.35 μm BCD	0.18 μm BCD, Schottky diode, 0.13 μm CMOS,
Isolation technology	Integrated SiO2 transformers with Cu/Al metals	Post-processed polyimide transformer with Au metals	PCB transformers	Coreless micro transformer	Post-processed polyimide transformer with Au metals
No. of isolation transformers	2	1	2	1	1

* Power oscillator supply voltage; ** The output voltage is not controlled.

and compared with recent state-of-the-art converters providing similar power levels.

5. Conclusions

A galvanically isolated dc–dc converter has been presented, which features a novel system architecture for power control functionality. Indeed, traditional isolated dc–dc converters exploit the PWM control scheme with a dedicated isolation link to perform efficient power regulation. Differently from the common approach, the proposed architecture implements a feedback control loop on the same physical isolation link used for power transfer, thus overcoming the need for an additional isolation channel with the consequent reduction in size, power consumption, and cost. To the authors’ knowledge, this is the very first integrated system that performs power transfer and closed-loop PWM output voltage/power regulation in the same isolation link.

6. Patents

A. Parisi, N. Greco, N. Spina, E. Ragonese, and G. Palmisano. Galvanic isolation circuit and system and a corresponding method of operation. U.S. Patent. US10917091B2, granted 9 February 2021.