Carrier-Based Implementation of SVPWM for a Three-Level Simplified Neutral Point Clamped Inverter with XOR Logic Gates

Abstract

The three-level simplified neutral point clamped (3L-SNPC) inverter has received increasing attention in recent years due to its potential applications in electrical drives and smart grids with renewable energy integration. However, most existing research has primarily focused on control development, with limited studies investigating modulation strategies or analyzing inverter losses under varying operating conditions. These aspects are critical for practical industrial applications. To address this gap, this paper proposes a novel carrier-based space vector pulse width modulation (CB-SVPWM) strategy for the 3L-SNPC inverter, aimed at simplifying PWM implementation and reducing cost. The proposed modulation strategy is experimentally evaluated by comparing inverter losses and total harmonic distortion with those of the conventional three-level neutral point clamped (3L-NPC) inverter under an equivalent carrier-based modulation scheme. A comprehensive comparative analysis is conducted across the full modulation range to demonstrate the effectiveness of the proposed approach, achieving a 13.2% reduction in total power loss, a 33.6% improvement in execution time, and maintaining a comparable weighted total harmonic distortion (WTHD) with a deviation within 0.04% of the conventional 3L-NPC inverter.

1. Introduction

Three-level neutral point clamped (3L-NPC) inverters have been widely adopted in low- to medium-voltage applications, such as electric machine drives [1,2], solar photovoltaic integration [3,4], vehicle traction [5] and propulsion [6,7], and grid integration [8,9], due to their low total harmonic distortion (THD), reduced voltage stress, and high voltage handling capability. However, two major drawbacks of conventional 3L-NPC inverters are their reliance on a large number of power semiconductors and their relatively high-power losses [10,11].

To reduce the number of semiconductors and the associated losses in low-voltage applications, J.W. Kolar et al. introduced the three-level T-type inverter [12] which eliminates the need for six clamping diodes while offering improved efficiency over a broad modulation range. Further reduction in semiconductor count is achieved with the three-level simplified NPC (3L-SNPC) inverter topology [13,14]. Compared to the three-level T-type inverter, the 3L-SNPC inverter eliminates two additional active switches along with their corresponding driver circuits, leading to lower system costs. Additionally, it mitigates neutral point voltage (NPV) fluctuations by eliminating medium voltage vectors (VVs) from its space vector diagram. Given these characteristics, the 3L-SNPC inverter, especially when paired with an efficient modulation scheme, holds strong potential for industrial applications where cost, simplicity, and thermal performance are critical. These include electric vehicle motor drive systems, renewable energy inverters, and compact, low-cost industrial power converters, where reduced switching losses and simpler implementation contribute to improved system-level efficiency and cost-effectiveness.

Despite these advantages, existing research on the 3L-SNPC inverter has primarily focused on control strategies [15,16,17,18,19,20,21,22], with minimal attention given to carrier-based modulation and loss analysis. Most carrier-based space vector pulse width modulation (CB-SVPWM) techniques are designed for 3L-NPC inverters, where the symmetrical three-phase structure allows direct implementation using standard modulation frameworks. However, these conventional CB-SVPWM methods fail to account for the inherent asymmetry of the 3L-SNPC inverter, making direct application infeasible. Specifically, traditional NPC-based carrier modulation methods rely on the presence of medium VVs to synthesize the reference vector accurately. In the 3L-SNPC topology, these medium VVs are absent, which restricts the available switching sequences. Additionally, direct carrier-based SVM implementation in the 3L-SNPC inverter may cause phase voltage imbalance due to the missing voltage states, potentially leading to increased harmonic distortion and modulation instability.

Conventional modulation methods [23,24] for multilevel inverters are not directly applicable due to the absence of medium VVs. For instance, a previously proposed modulation scheme for the 3L-SNPC inverter faces challenges in maintaining NPV balance under high modulation indices [14]. Furthermore, the asymmetric three-phase structure of the 3L-SNPC inverter prevents direct implementation of commonly used carrier-based space vector modulation (SVM) techniques [25,26]. A lookup-table-based enhanced SVM method has been introduced to reduce NPV fluctuations, but it suffers from drawbacks such as variable switching frequency, high design complexity, and increased hardware costs [27]. In 2019, a two-stage model predictive control strategy was proposed to regulate 3L-SNPC inverters connecting to an interior permanent magnet synchronous machine (IPMSM) [28], which achieved a 50% reduction in common-mode voltage amplitude (from 133 V to 67 V) and maintained balanced NPV under varying power factor conditions. In the same year, a deadbeat-based model predictive control approach was developed for 3L-SNPC inverter-fed motor drives, demonstrating excellent drive performance [20] and demonstrating smooth torque response and comparable performance at one-fourth the sampling frequency (5 kHz against 20 kHz) compared to conventional PTC. However, this approach relies on a non-carrier-based SVM, necessitating an additional complex programmable logic device (CPLD) or field-programmable gate arrays (FPGAs) for implementation, with a significant price increase compared to simple logic gates. Notably, none of the aforementioned studies have analysed the loss characteristics of the 3L-SNPC inverter.

In practice, a carrier-based SVM strategy for the 3L-SNPC inverter that ensures NPV balance across the full modulation range has rarely been studied. Furthermore, a comprehensive investigation into conduction and switching losses under varying modulation indices remains necessary. These two aspects are critical for industrial applications. On one hand, carrier-based SVM enables simplified modulation implementation with minimal hardware cost. On the other hand, a detailed loss analysis across the full modulation range provides valuable reference for power electronics engineers. To address these gaps, this paper presents a novel carrier-based SVM strategy that is easy to implement while maintaining NPV balance and delivering superior current performance across the full modulation range. In addition, a comprehensive evaluation of conduction and switching losses is performed and compared with those of a conventional 3L-NPC inverter using an equivalent modulation scheme. To further illustrate the structural and operational differences between the 3L-SNPC and 3L-NPC inverters,

Table 1. Comparative table for property and performance metrics between the 3L-SNPC and 3L-NPC inverter under the proposed method.

Comparative Metrics	3L-SNPC	3L-NPC
Number of switch components	10	12
Number of clamping diodes	0	6
Number of voltage vectors	21	27
Execution time (μs)	7.34	11.05
Average WTHD	1.034%	1.073%
Total Loss(W)	13.8	15.9

presents a comparative analysis of key characteristics, including hardware complexity, available voltage vectors, execution time, harmonic distortion, and power loss.

The key contributions of this paper are summarized below:

• A CB-SVPWM strategy is proposed for the 3L-SNPC inverter achieving low implementation cost and simplified real-time control. The proposed method effectively addresses the challenges of traditional carrier-based modulation in 3L-SNPC inverters by providing a computationally efficient alternative.
• The proposed modulation strategy utilizes XOR logic gates to replace FPGAs or CPLDs through hardware implementation and lowered system complexity and computational burden. This approach eliminates the need for lookup tables, making it more suitable for cost-sensitive applications.
• A comparative analysis between the 3L-SNPC and the conventional 3L-NPC topology under an equivalent modulation scheme is carried out. This study provides quantitative insights into modulation performance, efficiency, and system behavior across a full operating range.
• Loss characteristics including switching and conduction loss analysis of both inverters are presented to clearly demonstrate the advantages and disadvantages of the 3L-SNPC inverter. The findings provide a better understanding of power dissipation characteristics and their impact on overall inverter efficiency.

The rest of this paper is structured as follows: Section 2 describes the operating principle and mathematical modelling of the 3L-SNPC inverter. The proposed methodology is explained in Section 3. Section 4 presents experimental results and analysis. Finally, Section 5 concludes this paper.

2. System Modeling

The circuit topology of the 3L-SNPC inverter is illustrated in Figure 1. It consists of a dual buck converter interfaced with a conventional two-level voltage source inverter (2L-VSI). Two capacitors of equal capacitance are connected to the neutral point of the front-end dual buck converter, ensuring voltage balance.

Table 2. Switching logic of the front-end dual buck converter.

Switching Logic	$S_{f1}$	1	1	0	0
	$S_{f2}$	0	1	1	0
Terminal Voltage	$V_{in}^{+}$	$V_{dc}$	$V_{dc}$	$V_{dc}/2$	$V_{dc}/2$
	$V_{in}^{-}$	$V_{dc}/2$	0	0	$V_{dc}/2$

provides a summary of the switching logic for the dual buck converter, where $S_{f1}$, $S_{f1}^{-}$, $S_{f2}$, and $S_{f2}^{-}$ represent different switching combinations. The voltages $V_{in}^{+}$ and $V_{in}^{-}$ correspond to the positive and negative terminal voltages of the dual buck converter. Based on this configuration, the space vector diagram of the 3L-SNPC inverter can be derived, as shown in Figure 2.

The space vector diagram of the 3L-SNPC inverter consists of 21 voltage vectors (VVs), categorized as large, small, or zero VVs. Notably, in the 3L-SNPC inverter, six medium VVs are absent compared to the conventional 3L-NPC and T-type topologies. Each VV is represented using a three-digit notation, where ‘2’, ‘1’, and ‘0’ correspond to the three voltage levels $V_{dc}$, $V_{dc}/2$, and 0, respectively.

In the 3L-SNPC inverter, vector synthesis is restricted to the available 21 voltage vectors (VVs) instead of 27 VVs in the traditional 3L-NPC inverter. Among these, all large vectors $V_{1-6}$ consist only of ‘2’ and ‘0’, indicating a full DC voltage level. As a result, the dual buck converter maintains a consistent switching combination of ‘11’ of $S_{f1}$ and $S_{f2}$ for all large VVs. Importantly, large VVs do not contribute to NPV imbalance, making them advantageous for maintaining system stability.

According to the space vector diagram, generating a large VV, such as $V_1$(200), requires applying the aforementioned switching combination. Consequently, the switching state of the two-level inverter (2LI) is set to ‘100’, corresponding to $S_a=1$ and $S_b=S_c=0$. Under these conditions, the capacitor currents can be expressed as [20]

$$\left\{\begin{array}{c}{i}_{cp}=C_1{\displaystyle \frac{d{V}_{cp}}{dt}}\\ i_{cn}=C_2{\displaystyle \frac{d{V}_{cn}}{dt}}\end{array}\right.$$

(1)

where $i_{cp}$ and $i_{cn}$ represent the currents flowing through capacitors $C_1$ and $C_2$, respectively. Moreover, the neutral point current can be modeled as follows [25]:

$$i_n=\left(-\left|S_a-1\right|\right)i_a+\left(-\left|S_b-1\right|\right)i_b+\left(-\left|S_c-1\right|\right)i_c$$

(2)

where $i_a$, $i_b,$ and $i_c$ represent the currents generated by each phase leg, while $i_n$ corresponds to the neutral point current. The switching states of the respective phase legs are denoted as $S_a$, $S_b,$ and $S_c$. As shown in Figure 3, to generate the equivalent small voltage vector $V_9$ or $V_{10}$, the switching sequence of ‘110’ for the back-end 2LI is employed, while the front-end dual buck converter utilizes ‘10’ or ‘01’, corresponding to $V_9$ or $V_{10}$.

In Figure 3, the activation of $V_9$ results in $i_n=i_a+i_b={-i}_c$, which corresponds to the discharge of current from capacitor $C_1$, thereby reducing the $V_{cp}$. Similarly, for $V_{10}$, $i_n=-i_a-i_b=i_c$, indicating that current flows into capacitor $C_1$, leading to an increase in $V_{cp}$. Thus, the redundancy of small VVs plays a crucial role in balancing the NPV.

3. Proposed Methodology

This section presents the proposed modulation strategy for the 3L-SNPC inverter, ensuring NPV balance and efficient operation across a full modulation range.

3.1. Region Determination

In three-level inverters (3LIs), voltage levels are typically designed to change only once per VV switching action. This constraint not only reduces switching frequency variation and output harmonics but also significantly lowers computational complexity. Frequent switching actions would require additional calculations and increase the overall computational burden. To address this, each sector in the space vector diagram is systematically divided into four regions to optimize modulation control. As an example, Sector 1 is illustrated in Figure 4, and the same principle is applied to the remaining sectors.

To determine the appropriate region for a given reference VV (RVV), it can be decomposed into its α and β components, denoted as $V_{\alpha }$ and $V_{\beta }$, where $V_{\alpha }=\left|V_{ref}\right|·sin\theta$, and $V_{\beta }=\left|V_{ref}\right|·cos\theta$. The specific region is then determined based on the values of $V_{\alpha }$ and $V_{\beta }$. The boundaries between regions are defined as follows:

$$R_1: V_{\beta }\le -\sqrt{3}{V}_{\alpha }-{\displaystyle \frac{\sqrt{3}}{3}}{V}_{dc} and 0°\le \theta \le 60°$$

(3)

$$R_2:-\sqrt{3}{V}_{\alpha }-{\displaystyle \frac{\sqrt{3}}{3}}{V}_{dc}<V_{\beta }\le -{\displaystyle \frac{\sqrt{3}}{3}}{V}_{\alpha }+{\displaystyle \frac{2\sqrt{3}}{9}}{V}_{dc} and 0°\le \theta <30°$$

(4)

$$R_3:-\sqrt{3}{V}_{\alpha }-{\displaystyle \frac{\sqrt{3}}{3}}{V}_{dc}<V_{\beta }\le {\displaystyle \frac{1}{3}}{V}_{dc} and 30°\le \theta \le 60°$$

(5)

$$R_4:\left\{\begin{array}{c}-{\displaystyle \frac{\sqrt{3}}{3}}{V}_{\alpha }+{\displaystyle \frac{2\sqrt{3}}{9}}{V}_{dc}<V_{\beta }\le -\sqrt{3}{V}_{\alpha }+{\displaystyle \frac{2\sqrt{3}}{3}}{V}_{dc} and 0°\le \theta <30°\\ {\displaystyle \frac{1}{3}}{V}_{dc}<V_{\beta }\le -\sqrt{3}{V}_{\alpha }+{\displaystyle \frac{2\sqrt{3}}{3}}{V}_{dc}\end{array}\right.$$

(6)

3.2. Dwell Time Calculation

The dwelling time for the selected VVs can be determined based on their contribution to RVV synthesis. In Sector 1, five VVs are utilized, where each small voltage vector has two redundant switching states. As a result, five distinct duty cycles are defined.

The duty cycle $d_0$ corresponds to the zero-voltage vector $V_0$. The small voltage vectors $V_1$ and $V_2$ are assigned duty cycles $d_1$ and $d_2$, respectively. Similarly, the large voltage vectors $V_{7/8}$ and $V_{9/10}$ are associated with duty cycles $d_3$ and $d_4$. To ensure proper modulation, each duty cycle must remain within the range of 0 to 1, and their sum must always equal 1.

$$\left\{\begin{array}{c}0\le d_0,d_1,d_2,d_3,d_4\le 1\\ d_0+d_1+d_2+d_3+d_4=1\end{array}\right.$$

(7)

By following these constraints, the duty cycle of each voltage vector can be uniquely determined after identifying the specific region of RVV within each sector. This process is guided by the voltage-second balance principle, ensuring accurate reference voltage synthesis.

3.2.1. Dwell Time Calculation in $R_1$

If RVV enters region $R_1$, the duty cycles of $d_0$, $d_3,$ and $d_4$ are applied on $V_0$, $V_{7/8}$, and $V_{9/10},$ respectively. Since $V_1$ and $V_2$ are not used in this region, their corresponding duty cycles are set to zero, i.e., $d_1=d_2=0$. The relationship between duty cycles and the $\alpha ,\beta$ components of the reference voltage vector is given by

$$R_1:\left\{\begin{array}{c}{V}_{\alpha }={\displaystyle \frac{V_{dc}}{3}}{d}_3+{\displaystyle \frac{V_{dc}}{6}}{d}_4\\ V_{\beta }={\displaystyle \frac{\sqrt{3}{V}_{dc}}{6}}{d}_4\end{array}\right.$$

(8)

Solving (7) and (8) results in the following duty cycle expressions:

$$\left\{\begin{array}{c}{d}_3={\displaystyle \frac{3}{V_{dc}}}{V}_{\alpha }-{\displaystyle \frac{\sqrt{3}}{V_{dc}}}{V}_{\beta }\\ d_4={\displaystyle \frac{2\sqrt{3}}{V_{dc}}}{V}_{\beta }\\ d_0=1-{\displaystyle \frac{3}{V_{dc}}}{V}_{\alpha }-{\displaystyle \frac{\sqrt{3}}{V_{dc}}}{V}_{\beta }\end{array}\right.$$

(9)

3.2.2. Dwell Time Calculation in $R_2$

If RVV is positioned in region $R_2$, the voltage vectors $V_1$, $V_{7/8}$, and $V_{9/10}$ will be applied with duty cycles $d_1$, $d_3$, and $d_4$, respectively. Consequently, $d_0$ and $d_2$ are set to zero. The relationship between duty cycles and $V_{\alpha }$, $V_{\beta }$ in this region is given by

$$R_2:\left\{\begin{array}{c}{V}_{\alpha }={\displaystyle \frac{2V_{dc}}{3}}{d}_1+{\displaystyle \frac{V_{dc}}{3}}{d}_3+{\displaystyle \frac{V_{dc}}{6}}{d}_4\\ V_{\beta }={\displaystyle \frac{\sqrt{3}{V}_{dc}}{6}}{d}_4\end{array}\right.$$

(10)

Solving (10) while satisfying the constraints in (7) yields the following duty cycle expression:

$$\left\{\begin{array}{c}{d}_1={\displaystyle \frac{3}{V_{dc}}}{V}_{\alpha }+{\displaystyle \frac{\sqrt{3}}{V_{dc}}}{V}_{\beta }-1\\ d_3=2-{\displaystyle \frac{3}{V_{dc}}}{V}_{\alpha }-{\displaystyle \frac{3\sqrt{3}}{V_{dc}}}{V}_{\beta }\\ d_4={\displaystyle \frac{2\sqrt{3}}{V_{dc}}}{V}_{\beta }\end{array}\right.$$

(11)

3.2.3. Dwell Time Calculation in $R_3$

If RVV is situated in region $R_3$, the voltage vectors $V_2$, $V_{7/8}$, and $V_{9/10}$ will be applied with duty cycles $d_2$, $d_3$, and $d_4$, respectively. In this case, setting $d_0=d_1=0$ leads to the following relationships:

$$R_3:\left\{\begin{array}{c}{V}_{\alpha }={\displaystyle \frac{V_{dc}}{3}}{d}_2+{\displaystyle \frac{V_{dc}}{3}}{d}_3+{\displaystyle \frac{V_{dc}}{6}}{d}_4\\ V_{\beta }={\displaystyle \frac{\sqrt{3}{V}_{dc}}{3}}{d}_2+{\displaystyle \frac{\sqrt{3}{V}_{dc}}{6}}{d}_4\end{array}\right.$$

(12)

Solving (12) while considering the constraints in (7) results in the following duty cycle expressions:

$$\left\{\begin{array}{c}{d}_2={\displaystyle \frac{3}{V_{dc}}}{V}_{\alpha }+{\displaystyle \frac{\sqrt{3}}{V_{dc}}}{V}_{\beta }-1\\ d_3={\displaystyle \frac{3}{V_{dc}}}{V}_{\alpha }-{\displaystyle \frac{\sqrt{3}}{V_{dc}}}{V}_{\beta }\\ d_4=2-{\displaystyle \frac{6}{V_{dc}}}{V}_{\beta }\end{array}\right.$$

(13)

3.2.4. Dwell Time Calculation in $R_4$

If RVV is located in region $R_4$, the voltage vectors $V_1$, $V_2$, $V_{7/8}$, and $V_{9/10}$ will be applied with duty cycles $d_1$, $d_2$, $d_3$, and $d_4$, respectively. In this case, $d_0=0$. The following relationships can be established:

$$R_4:\left\{\begin{array}{c}{V}_{\alpha }={\displaystyle \frac{2V_{dc}}{3}}{d}_1+{\displaystyle \frac{V_{dc}}{3}}{d}_3+{\displaystyle \frac{V_{dc}}{6}}{d}_4+{\displaystyle \frac{V_{dc}}{3}}{d}_2\\ V_{\beta }={\displaystyle \frac{\sqrt{3}{V}_{dc}}{6}}{d}_4+{\displaystyle \frac{\sqrt{3}{V}_{dc}}{3}}{d}_2\end{array}\right.$$

(14)

Considering (7) and (14), there are four unknown variables but only three relationships, leading to an infinite number of possible solutions. Simplifying (14) using (7) gives

$$\left\{\begin{array}{c}2d_1-d_4={\displaystyle \frac{6}{V_{dc}}}{V}_{\alpha }-2\\ 2d_2+d_4={\displaystyle \frac{2\sqrt{3}}{V_{dc}}}{V}_{\beta }\\ 2d_1+d_3={\displaystyle \frac{3}{V_{dc}}}{V}_{\alpha }-{\displaystyle \frac{\sqrt{3}}{V_{dc}}}{V}_{\beta }\end{array}\right.$$

(15)

From (15), the following relationship for duty cycles can be derived:

$$d_3+d_4=2-{\displaystyle \frac{3V_{\alpha }}{V_{dc}}}-{\displaystyle \frac{\sqrt{3}V\beta }{V_{dc}}}$$

(16)

For ease of calculation, define $\kappa$ as

$$\kappa ={\displaystyle \frac{d_3}{2}}+{\displaystyle \frac{d_4}{2}}$$

(17)

To satisfy the duty cycle constraints $0\le d_3$, $d_4\le 1$, and $0\le d_3+d_4\le 1$, the following expressions are obtained:

$$\left\{\begin{array}{c}{d}_3=2\lambda \kappa \\ d_4=2(1-\lambda )\kappa \end{array}\right.$$

(18)

The duty cycle can then be determined as a function of $\lambda$ and $\kappa$:

$$\left\{\begin{array}{c}{d}_1={\displaystyle \frac{3V_{\alpha }}{V_{dc}}}+\left(1-\lambda \right)\kappa -1\\ d_2={\displaystyle \frac{\sqrt{3}{V}_{\beta }}{V_{dc}}}-\left(1-\lambda \right)\kappa \\ d_3=2\lambda \kappa \\ d_4=2\left(1-\lambda \right)\kappa \end{array}\right.$$

(19)

Substituting $d_1$ and $d_2$ from (19) into (7) yields

$$\left\{\begin{array}{c}1-{\displaystyle \frac{4V_{dc}-6V_{\alpha }}{2V_{dc}-3V_{\alpha }-\sqrt{3}{V}_{\beta }}}⩽\lambda ⩽1-{\displaystyle \frac{2V_{dc}-6V_{\alpha }}{2V_{dc}-3V_{\alpha }-\sqrt{3}{V}_{\beta }}}\\ 1-{\displaystyle \frac{2\sqrt{3}{V}_{\beta }}{2V_{dc}-3V_{\alpha }-\sqrt{3}{V}_{\beta }}}⩽\lambda ⩽1-{\displaystyle \frac{2\sqrt{3}{V}_{\beta }-2V_{dc}}{2V_{dc}-3V_{\alpha }-\sqrt{3}{V}_{\beta }}}\end{array}\right.$$

(20)

Given the constraint $0\le \lambda \le 1$, the boundary condition for $\lambda$ can be expressed as

$$\mathrm{m}\mathrm{a}\mathrm{x}\left(0,1-{\displaystyle \frac{2\sqrt{3}{V}_{\beta }}{2V_{dc}-3V_{\alpha }-\sqrt{3}{V}_{\beta }}}\right)⩽\lambda ⩽\mathrm{m}\mathrm{i}\mathrm{n}\left(1,1-{\displaystyle \frac{2V_{dc}-6V_{\alpha }}{2V_{dc}-3V_{\alpha }-\sqrt{3}{V}_{\beta }}}\right)$$

(21)

There is no fixed constant that satisfies the dynamic boundary condition of $\lambda$. For simplicity, the average of the upper and lower boundaries is chosen. In this case, the average value tends to balance the application of $V_{7/8}$ and $V_{9/10}$ by adjusting their respective duty cycles $d_3$ and $d_4$, ensuring both small VVs are applied for sufficient duration during sector selection and transitions. This prevents abrupt switching from large VVs to non-adjacent small VVs when the dwelling time of a small VV is shorter than the system dead time, such as the transition from $V_1$ to $V_{9/10}$. This guarantees a smoother VV transition sequence.

The final expression for $\lambda$ is given by

$$\lambda ={\displaystyle \frac{1}{2}}\left\{\mathrm{m}\mathrm{a}\mathrm{x}\left(0,1-{\displaystyle \frac{2\sqrt{3}{V}_{\beta }}{2V_{dc}-3V_{\alpha }-\sqrt{3}{V}_{\beta }}}\right)+\mathrm{m}\mathrm{i}\mathrm{n}\left(1,1-{\displaystyle \frac{2V_{dc}-6V_{\alpha }}{2V_{dc}-3V_{\alpha }-\sqrt{3}{V}_{\beta }}}\right)\right\}$$

(22)

3.3. Carrier-Based Implementation with XOR Gates

Once the duty cycles and switching states have been determined, the next step is to generate gate signals for the 3L-SNPC inverter. Traditional methods often rely on complex sequential programming, where each duty cycle is assigned to its corresponding switching state, resulting in high programming complexity and implementation challenges. To address this issue, a carrier-based implementation method using XOR gates is proposed to simplify the intricate FPGA-based sequential programming process.

The 3L-SNPC inverter consists of five pairs of complementary switches: The front-end dual buck converter includes $(S_{f1},S_{\overline{f1}})$ and $(S_{f2},S_{\overline{f2}})$, while the back-end 2L-VSI consists of $(S_{ap},S_{an})$, $(S_{bp},S_{bn})$ and $(S_{cp},S_{cn})$. To generate the correct gate signals, five reference values need to be compared with the carrier signal, denoted as $r_{f1}$, $r_{f2}$, $r_a$, $r_b$, and $r_c$.

Due to the inherently asymmetric three-phase structure of the 3L-SNPC inverter, directly comparing the reference values with the carrier signal does not produce the correct gate signals. To overcome this challenge, a logic compensatory counter (LCC) is introduced for each reference value to ensure the accurate output of switching states.

For their respective logic operations associated, five LCCs are defined: $C_{f1}$, $C_{f2}$, $C_a$, $C_b,$ and $C_c$, where counters $C_{f1}$ and $C_{f2}$ are required for switches $(S_{f1},S_{\overline{f1}})$, and $(S_{f2},S_{\overline{f2}})$, $C_a$, $C_b,$ and $C_c$ are employed to maintain the correct output of the back-end 2L-VSI.

Compared to FPGA-based implementations, XOR logic integrated circuits (ICs) offer a low-cost alternative (<USD 1 per chip), significantly reducing system complexity while maintaining accurate modulation and NPV balancing across the full modulation range. This ensures that the proposed carrier-based XOR implementation provides an efficient and practical solution for real-time control in the 3L-SNPC inverters.

A flowchart of the proposed carrier-based implementation with XOR gates is presented in Figure 5. It generates PWM signals in two stages. The first stage involves comparing reference values and a subset of LCCs with the carrier. The LCCs follow a different comparison logic, and if the counter value exceeds the carrier, a ‘0’ is outputted. This ‘0’ is subsequently used in the XOR logic operation, which follows the logic operation principles $0 XOR m=m$, and $1 XOR m=\overline{m}$.

3.4. RVV Sythesization

To synthesize the RVV, only small and zero vectors are employed in $R_1$, whereas small and large vectors are utilised in $R_2$, $R_3,$ and $R_4$. Redundant small vectors are employed to balance the NPV, such as $V_7$, $V_8$, $V_9$, and $V_{10}$. For instance, $V_7$ and $V_9$ can be used to discharge $C_1$, while $V_8$ and $V_{10}$ can be utilised to discharge $C_2$. Define NPV deviation as $\Delta V=V_{C1}-V_{C2}$.

3.4.1. RVV Synthesis in $R_1$

In $R_1$, when the neutral point voltage deviation $\Delta V$ is greater than zero, switches $S_{f1}$ and $S_{\overline{f2}}$ are activated to balance the NPV. Consequently, the output voltages of the dual buck converter $(V_{in+},V_{in-})$ are clamped at $V_{dc}$ and $V_{dc}/2$.

In this case, voltage vectors $V_0$, $V_7,$ and $V_9$ are selected. Their corresponding 2L-VSI switching sequence is illustrated in Figure 6. The reference values for the 2L-VSI can be derived as

$$r_a=1, r_b=d_3, r_c=d_3+d_4$$

(23)

The LCCs for this case are

$$C_a=0, C_b=C_c=1$$

(24)

When $\Delta V$ is smaller than zero, switches $S_{f2}$ and $S_{\overline{f1}}$ must be activated to increase $\Delta V$. In this scenario, voltage vectors $V_8$ and $V_{10}$ are selected, following the switching sequence shown in Figure 7. The reference values determined in this case are the same as Equation (23).

To generate the correct PWM output, the LCCs mentioned in Equation (24) are used; the final PWM output is obtained by

$$PWMx=PWM r_x \mathrm{X}\mathrm{O}\mathrm{R} C_x$$

(25)

where $PWMx$ represents the pulse width modulation signals for the corresponding phase leg, and $PWM r_x$ is generated by comparing the reference value $r_x$ with the carrier. Since the back-end 2L-VSI produces consistent gate signals, any fluctuations in $\Delta V$ only affect the dual buck converter operation, ensuring smooth transitions.

3.4.2. RVV Synthesis in $R_2$ and $R_3$

In $R_2$, when $\Delta V$ is greater than zero, voltage vectors $V_1$, $V_7,$ and $V_9$ are selected. The inverter switching sequence is shown in Figure 8.

Since voltage level ‘2’ is used for the dual buck converter, $r_{f1}=1$. Additionally, switch $S_{f2}$ conducts only when the voltage level transitions to zero, leading to $r_{f2}=d_4$. Thus, the following combination is applied:

$${\displaystyle \genfrac{}{}{0pt}{}{r_a=1, r_b=d_1+d_3, r_c=0}{C_a=C_c=0, C_b=1}}$$

(26)

The methodology for vector synthesis in $R_3$ is a similar logic to $R_2$. For simplicity, further elaboration is omitted herein.

3.4.3. RVV Synthesis in $R_4$

In $R_4$, two large vectors are used for vector synthesis. The LCCs of the dual buck converter participate in the modulation process, acting similarly to the duty cycle that is compared with the carrier signal to produce PWM LCC signals. The gate signal for the front-end dual buck converter is obtained using XOR logic operations between the first-layer PWM signal against the PWM LCC signals. The PWM output is then expressed as

$$PWM S_{fn}=PWM r_{fn} \mathrm{X}\mathrm{O}\mathrm{R} PWM C_{fn}$$

(27)

where its complement generates the PWM output for $S_{\overline{fn}}$. When $\Delta V$ is positive, the switching sequence at this region results in the same 2L-VSI reference values, as shown in Equation (26). For the dual buck converter, switch $S_{f1}$ remains always ON, so $r_{f1}=1$. However, for $S_{f2}$, the desired switching sequence is neither 0-1-0 nor 1-0-1. To address this, LCC $C_{f2}$ is assigned to $d_1$, yielding

$$r_{f2}=d_1+d_3+d_4, C_{f2}=d_1$$

(28)

where gate pulse generation in this region is shown in Figure 9.

3.5. Overmodulation Consideration

When the modulation index lies within the range of 0 to 0.866, the inverter operates in the linear modulation region. In this region, the RVV remains within the inscribed circle of the outer hexagon of the space vector diagram, as shown in Figure 10, and can be synthesized by the proposed method straight away. The outer hexagon boundary represents the theoretical limit of space vector modulation. The area between the inscribed circle and the hexagon boundary, which is shaded in grey in the figure, is not covered by linear modulation.

When the modulation index goes beyond 0.866, reaching values between 0.866 and 1, the $V_{ref}$(RVV) moves into the overmodulation region, which is located between the inscribed circle and outer hexagon and can be represented by the red dashed circle in Figure 10. In this region, the proposed method employs a minimum phase angle error approach to handle the overmodulation challenge [29,30]. Specifically, when the RVV exceeds the outer hexagon boundary, it is projected back onto the boundary while maintaining the same phase angle ($\theta$), as illustrated in Figure 11. This approach successfully extends the proposed method to achieve overmodulation for the 3L-SNPC inverter.

4. Experimental Results

To validate the proposed methodology, experimental setups of both the 3L-SNPC and 3L-NPC inverters are built, as depicted in Figure 12. The system parameters are detailed in

Table 3. Experiment parameters.

Circuit Variables	Description	Value
$V_{dc}$	DC-Link Voltage	$200 \mathrm{V}$
$C_1$$\& C_2$	DC-Link Capacitance	$680 \mathrm{\mu }\mathrm{F}$
$L$	Load Inductance	$10 \mathrm{m}\mathrm{H}$
$f_s$	Switching Frequency	$5 \mathrm{k}\mathrm{H}\mathrm{z}$

. The proposed method is implemented on the NXP QorIQP5020 processor in the dSPACE DS1202 MicroLabBox with a control period and sampling period of 200 $\mathrm{\mu }\mathrm{s}$. Carrier frequency is set to 5 kHz. Both inverter platforms use an Infineon FF100F12RT4 IGBT module with the same driver and sampling circuit.

4.1. Execution Time

The execution time of the proposed method is measured to test its computational complexity in the 3L-SNPC inverter compared to the 3L-NPC inverter. In this case, the modulation method is written in C language and implemented on a DSP TMS320F28335 with a clock frequency of 150 MHz. A digital output port of a DSP is utilized to measure the execution time. Specifically, the level of the digital output port is set to 5 V when modulation starts and reset to 0 V when execution is finished. The results of the proposed method in comparison to state-of-the-art methods and traditional methods are shown in Table 3.

Table 4. Execution time of different modulation methods.

Modulation Method	Circuit Topologies	$\mathbf{Execution} \mathbf{Time} \left(\mathbf{\mu }\mathbf{s}\right)$
Proposed method	3L-NPC	11.05
Traditional method	3L-NPC	21.5
Simplified traditional method	3L-NPC	16.8
Method in [31]	3L-NPC	11.5
Method in [32]	3L-NPC	13.4
Proposed method	3L-SNPC	7.34
Method in [27]	3L-SNPC	10.05
Method in [18]	3L-SNPC	7.39

shows that the proposed method achieves a shorter execution time than both the traditional and state-of-the-art methods. In the 3L-SNPC inverter, it reduces the execution time to 7.34 $\mathrm{\mu }\mathrm{s}$, outperforming the method in [27] (10.05 $\mathrm{\mu }\mathrm{s}$) and matching performance against the method in [18] (7.39 $\mathrm{\mu }\mathrm{s}$). However, unlike [18], which requires additional FPGA hardware, the proposed method only uses XOR logic gates, making it more cost-effective. For the 3L-NPC inverter, the proposed method also outperforms the traditional method (21.5 $\mathrm{\mu }\mathrm{s}$) and achieves comparable performance to state-of-the-art methods.

The proposed method reduces computational complexity and eliminates FPGA dependency on hardware implementation of 3L-SNPC inverters, making it a faster and more cost-effective solution for real-time DSP-based inverter control.

4.2. Performance Comparison

Experimental observations, including the line voltage $V_{ab}$, the voltage across the upper capacitor $V_{cp}$, and the phase currents $I_a$ and $I_b$, are presented in Figure 13. The modulation index, defined as $\left|V_{ref}\right|/(2/3V_{dc})$, varied from 0 to 0.866. For modulation indices of 0.3, 0.5, and 0.866, the proposed method for the 3L-SNPC inverter demonstrated an output waveform performance comparable to the same method used in the 3L-NPC inverter.

To further evaluate waveform quality, the weighted total harmonic distortion (WTHD) of the line voltage is calculated for various modulation indices, as illustrated in Figure 14. WTHD provides a more robust evaluation metric compared to total harmonic distortion (THD), which is easily influenced by load characteristics and the effectiveness of the filter parameters. The use of WTHD ensures that its weighted values are independent of filter parameters, allowing for a fair comparison to rule out the external circuit influences.

At lower modulation indices, both the 3L-SNPC and 3L-NPC inverters operate closer to the inner hexagon of the space vector diagram, sharing the same space vector distribution of voltage vectors (VVs). As a result, their output performance in this region is similar. However, at modulation indices of 0.2 and 0.3, the WTHD of the 3L-SNPC inverter is slightly higher than that of the 3L-NPC inverter by 0.25% and 0.12%, respectively. This occurs because, during reference VV synthesis, the effective allocation time for selected VVs is minimal, making dead-time a significant factor in increasing the harmonic distortion. This effect is more pronounced in the 3L-SNPC inverter due to its three-phase asymmetric circuit structure.

As the modulation index increases, the influence of harmonics diminishes, and the WTHD of the 3L-SNPC inverter shows a reduction of 0.15% and 0.06% compared to the 3L-NPC inverter.

Under heavy load conditions, the WTHD of the 3L-SNPC inverter is slightly higher than that of the 3L-NPC inverter by 0.09–0.02%. The absence of six medium VVs in the 3L-SNPC inverter, compared to the 3L-NPC inverter, limits its ability to accurately approximate the reference VV. However, as the operating region approaches the outer hexagon of the SVM diagram and the output current amplitude increases, the selected VVs have a longer effective duration, reducing harmonics caused by IGBT dead-time.

Higher current amplitudes at elevated modulation indices generally result in increased inverter losses. However, the 3L-SNPC inverter has the potential for lower losses due to its reduced component count. To further investigate this aspect, switching loss tests are conducted for both inverters.

4.3. Loss Analysis

The switching losses are assessed using double-pulse test (DPT) experiments, consisting of a half-bridge module identical to that used in the inverter, a variable air-core inductor, and a DSP development board. The measured waveforms are shown in Figure 15. Following the methodology described in [10], the switching and conduction losses are quantified under various operating conditions, with voltages ranging from 100 V to 200 V and currents from 1 A to 10 A.

Figure 15 demonstrates that the 3L-SNPC inverter, utilizing the proposed CB-SVM, incurs lower switching and conduction losses compared to the conventional 3L-NPC inverter across the entire modulation spectrum.

Figure 16 and Figure 17 demonstrate the loss characteristics of the proposed modulation method implemented in the 3L-SNPC and 3L-NPC inverter. In summary, these findings confirm that the proposed CB-SVM method, when applied to the 3L-SNPC inverter, maintains comparable voltage and current waveform quality while achieving reduced inverter losses relative to the conventional 3L-NPC inverter.

5. Simulation Results

To further validate the performance of the proposed modulation strategy, simulations were conducted and compared with two state-of-the-art methods under two operating conditions in

Table 5. Simulation results of state-of-the-art methods compared to the proposed method under $V_{dc}=200\mathrm{V}, R=10 \mathrm{\Omega }$.

Modulation Index	Method 1 [27] $10.05 \mathbf{\mu }\mathbf{s}$		Method 2 [18] $7.39 \mathbf{\mu }\mathbf{s}$		Method Proposed $7.34 \mathbf{\mu }\mathbf{s}$
m	WTHD (%)	Loss (W)	WTHD (%)	Loss (W)	WTHD (%)	Loss (W)
0.1	1.23568	2.6565	1.4597	2.6565	1.3502	2.1297
0.2	1.059388	5.9926	1.391786	5.9926	1.1167	4.9875
0.3	0.8095	10.1481	0.9095	10.1481	0.81381	8.6015
0.4	0.569445	15.0471	0.61398	15.0471	0.53217	13.0086
0.5	0.39745	20.8078	0.39745	20.8078	0.40818	18.2699
0.6	0.49493	24.9515	0.49493	23.392	0.49634	23.1803
0.7	0.56166	29.5731	0.56166	27.9754	0.54426	27.5937
0.8	0.58528	34.2186	0.58528	33.2209	0.49616	32.3649
0.9	0.55825	38.9909	0.55825	38.4157	0.41715	37.2091
1.0	0.50178	43.4061	0.50178	43.2129	0.40487	41.7622

and

Table 6. Simulation results of state-of-the-art methods compared to the proposed method under $V_{dc}=100 \mathrm{V}, R=5 \mathrm{\Omega }$.

Modulation Index	Method 1 [27] $10.05 \mathbf{\mu }\mathbf{s}$		Method 2 [18] $7.39 \mathbf{\mu }\mathbf{s}$		Method Proposed $7.34 \mathbf{\mu }\mathbf{s}$
m	WTHD (%)	Loss (W)	WTHD (%)	Loss (W)	WTHD (%)	Loss (W)
0.1	1.23574	1.9751	1.45976	1.9751	1.3503	1.738
0.2	1.05941	4.4903	1.391764	4.4903	1.1167	4.0419
0.3	0.80954	7.6175	0.90958	7.6175	0.81401	6.9275
0.4	0.56946	11.3358	0.61398	11.3358	0.53359	10.4182
0.5	0.39746	15.6486	0.40362	15.6486	0.40812	14.5384
0.6	0.4949	19.1029	0.48403	18.3639	0.49661	18.2844
0.7	0.56164	22.6562	0.62855	21.9164	0.54501	21.7733
0.8	0.58525	26.2935	0.69391	25.8197	0.49683	25.53
0.9	0.55821	30.0027	0.6086	29.6792	0.41712	29.308
1.0	0.50173	33.7267	0.54343	33.5928	0.40501	33.0623

. The modulation index was tested from 0.1 to 1.0; the WTHD of line voltage and the loss of the inverter from switching and conducting actions of IGBT are recorded. Power loss was estimated through a co-simulation framework combining MATLAB/Simulink and PLECS, where empirical switching and conduction loss data derived from double-pulse test (DPT) experiments were embedded into the loss models.

It can be seen from Table 5 and Table 6 that for each method, the WTHD results under the two operating conditions are nearly the same. This shows that using line voltage WTHD is a more stable and fair way to compare different modulation methods because it is less affected by filter or load parameters. This also gives better guidance for practical use and engineering evaluation.

As for comparative performance, the proposed method outperforms both reference methods in WTHD when the modulation index exceeds 0.6. At lower modulation indices, it achieves better performance than Method 2 and delivers comparable results to Method 1. In terms of execution time, measured experimentally, the proposed method achieves lower latency than Method 1 and comparable speed to Method 2. Most notably, the hardware implementation cost of the proposed strategy is significantly reduced. It requires only a single XOR logic gate IC, while Method 1 relies on an FPGA-based sequence control, and Method 2 requires FPGA or CPLD support, resulting in considerably higher hardware complexity and cost. In summary, the proposed method achieves a favorable balance between modulation performance, computational complexity, and hardware cost, making it a highly attractive solution for real-time low-cost multilevel inverter applications.

6. Conclusions

This paper presented a low-cost carrier-based SVPWM strategy for the 3L-SNPC inverter, aiming to simplify implementation by replacing FPGA/CPLD with XOR logic gates. The proposed method achieved a minimum WTHD of 0.40% at full load condition, reduced inverter loss, and shortened execution time to 7.34 μs, demonstrating comparable or superior performance to existing methods via different working conditions. These results confirm its effectiveness and cost-efficiency. Future work will explore advanced control algorithms based on the proposed modulation to further enhance performance.