A High-Efficiency Frequency Multiplier with Triangular-Resistance Phase Interpolation

Abstract

A high-efficiency frequency multiplier is presented in 65-nm CMOS with a core area of 0.06 mm². A low-cost five-segment triangular-resistance phase interpolation scheme is proposed. By performing resistive interpolation on four-path orthogonal triangular signals, 10-fold frequency multiplication is achieved within the input frequency range of 12–20 MHz. The prototype only includes a quadrature square-wave generator, four orthogonal square-triangular converters and the proposed four-path 5-segment triangular-resistance phase interpolators, with a frequency deviation less than 7%. The presented design achieves an output power of −9.8 dBm, with an input power of −2.0 dBm and power consumption of 0.45 mW from a 1.2-V supply, which obtains a frequency multiplication efficiency up to 9.6%. The proposed mechanism could be extended to accomplish a configurable multiplication factor.

1. Introduction

Frequency multipliers are widely utilized in communication systems to generate high-frequency working clocks from a low-frequency reference one. The traditional mechanisms for achieving frequency multiplication can be broadly divided into two categories. One is to use a nonlinear device or a narrow-pulse generator for harmonic generation and then employ a bandpass filter to extract the desired harmonic frequency [1,2,3,4], but this encounters a low multiplication factor with limited high-order harmonics or requires a complex filtering topology with the high-Q feature. The other is to use digital sub-sampling/injection-locked phase-locked loops (PLLs) based on frequency discrimination and division to obtain a higher output frequency from the embedded voltage-controlled oscillator (VCO) under the reference of a lower input frequency, which has a pure output spectrum and low output noise, at the cost of the hardware implementation [5,6,7].

An optimized method is to inject the harmonics into a free-running oscillator or quadrupler [8,9]; however, the injection-locked frequency multipliers suffer from a limited frequency range that is unfit for sub-GHz applications, and additional error-correcting modules are required. Nowadays, mainstream frequency multipliers consist of a multiphase generator and an edge combiner [10,11,12,13]. The reported design [10] employs RC networks as delay units for multiphase generation, but is prone to low robustness, as R and C are highly process dependent. The existing work [11] uses multiphase VCOs for frequency multiplication, at the cost of hardware consumption and silicon area. The presented implementations [12,13] utilize delay-locked loops for multiphase generation, but require complicated loops.

In this article, a high-efficiency five-segment triangular-resistance phase interpolation (TRPI) scheme is proposed, which is fully different from those described in the existing literature. As a result, a low-power, low-cost and configurable frequency multiplier is achieved.

This article is organized as follows: Section 2 provides the frequency multiplier architecture, Section 3 provides the detailed circuit implementation, followed by experimental results in Section 4 and the conclusion in Section 5.

2. Proposed Architecture

A low-complexity frequency multiplier is proposed based on multiphase triangular generation and a k-segment resistive phase interpolation scheme, which is shown in Figure 1a Four paths of quadrature clocks are provided by a square-wave generator with a frequency division of 2 from the input reference signal, and then are sent to four parallel square-to-triangular converters to obtain orthogonal triangular signals. The subsequent phase interpolator, based on 5-segment resistance across two adjacent triangular signals with a fixed phase difference of 90°, generates 4 groups of narrow pulses with a phase step of 18° (=90°/5). Therefore, four paths of quadrature interpolators obtain 4 × 5 groups of narrow pulses. Finally, all pulses are combined together in an OR gate to conduct frequency multiplication with a factor (n) as depicted in (1).

$$n={\displaystyle \frac{F_{out}}{F_{IN}}}={\displaystyle \frac{1}{2}}\times k\times 4=2k$$

(1)

The proposed mechanism could be extended to achieve a configurable multiplication factor, depending on the number (k) of interpolating resistors that are used. To accomplish a high multiplication robustness over different triangular-wave slopes, common-mode feedback (CMFB) modules are applied to the square-triangular converters to achieve zero-crossing voltage (V_CM) calibration and benefit the subsequent V_CM comparison. To ensure an accurate phase step and relax the hardware complexity, the phase interpolation is conducted on triangular waves rather than other signal types such as sinusoidal or sawtooth waves.

The resistive interpolation technique is a simple, passive and high-efficiency method in various multiphase schemes. The operational principle of the proposed 5-segment resistive phase interpolation is shown in Figure 1b. Five serial resistors of the same size are inserted between two adjacent triangular signals with a phase difference of 90°. Twenty of the same resistors in total are used in four paths of interpolators. Phase-interpolating voltages (V₁–V₅ and V₆–V₁₀) and their corresponding waveforms are thus generated, which are evenly distributed at equal time (phase) intervals between orthogonal triangular signals. As a result, a small phase step of 18° (=90°/5) is achieved. With four paths of 5-segment resistive phase interpolators, 20 narrow pulses are generated with the adjacent pulse phase difference of 18°, and thus ten-fold frequency multiplication is finally accomplished.

The proposed architecture only consists of a digital quadrature square-wave generator, four analogue orthogonal triangular converters and four digitalized phase interpolators, and is thus considered a half-digital implementation. The presented topology has the following merits: (1) a reconfigurable multiplication factor; (2) a half-digital structure that benefits low-cost low-power features; and (3) common-mode feedback and comparison that optimize frequency robustness, and thus the multiplication efficiency.

3. Design Implementation

3.1. Low-Cost Quadrature Square-Wave Generator

The proposed multiplication mechanism requires multiphase clock signals for phase interpolation. A simplified square-wave generator is given in Figure 2, based on D-type flip-flops (DFFs) and logic gates to obtain four paths of quadrature signals. The edge detector doubles the input clock frequency (such as 16 MHz) by triggering both rising and falling edges via an inverter-based delay cell. The quadrature divider-by-4 is made of two-stage cascaded dividers-by-2 and conducts the frequency division of 4 to generate four paths of clocks with an accurate phase difference of 90° under the output frequency of 8 MHz. CMOS transmission gates (TGs) are adopted to match the inverter delay to obtain an accuracy phase difference of 90°. The MOS capacitor is used to set the pulse width (8 ns) for the edge detector. CMOS transmission gates (TGs) are adopted to match the inverter delay, to obtain an accuracy phase difference of 90°. Due to the rising-edge trigger mode of DFFs, the initial timing order is different at the first arriving clock edge between rising and falling, which causes output phase dislocation. To avoid this, an additional edge detector is introduced.

3.2. Low-Power Square-to-Triangular Converter

As the proposed multiplication mechanism prefers triangular waves, multiphase square-to-triangular converters are needed. Figure 3 shows the proposed converter based on a capacitor charging–discharging scheme controlled by two pairs of complementary switches under the timing sequence of the differential square waves. The low-voltage cascode current mirror provides a fixed charging–discharging current (I_C) through the capacitor to generate a triangular wave.

To avoid the triangular distortions that occur at peaks and valleys due to the level translation of square waves, a replica cell was introduced to guarantee the continuity of the charging–discharging current. The triangular slope and peak/valley voltages (V_H/V_L) are depicted in (2). Here, T is the square-wave period. Low-voltage self-biased cascode current mirror topology ensures enough voltage-drop margins for V_H and V_L variations. Consistent deviations in the slope/V_H/V_L among four converters under process/voltage/temperature (PVT) variations do not affect the equal time (phase) interval feature among phase-interpolating points. That is, the presented converter not only has a high robustness over PVT variations, but also covers a wide input frequency range.

$$Slope={\displaystyle \frac{I_C}{C}}, { V}_H=V_{CM}+{\displaystyle \frac{I_C}{C}}\times {\displaystyle \frac{T}{4}}, { V}_L=V_{CM}-{\displaystyle \frac{I_C}{C}}\times {\displaystyle \frac{T}{4}}$$

(2)

Additionally, to match the phase-interpolating voltages (V₁–V₂₀) to V_CM, the CMFB module is introduced, accomplishing a high multiplication robustness over different slopes under PVT variations. After low-pass filtering, triangular CM voltage is obtained and compared to V_CM, which inversely tunes the current I_F and thus corrects the triangular DC voltage. Considering the two-stage loop stability of the CMFB, a high-speed high-gain amplifier with a diode-connected cross-couple topology is used. Both the large transistor size and matched layout design effectively suppress the inverse effect of the CMFB offset voltage.

3.3. Digitalized Resistive Phase Interpolator

As the core module of the frequency multiplier, the presented triangular-resistance phase interpolators set the upper limit of both the silicon area and power consumption. To achieve low cost/power, Figure 4 gives the proposed four-path quadrature 5-segment phase interpolators with a digitalized and passive structure including 20 resistors, 20 simplified comparators, 20 MOS-transistor capacitors and a small quantity of logic gates.

Twenty phase-interpolating voltages (V₁–V₂₀) are generated by four paths of serial resistors across the adjacent orthogonal triangular signals, and are then compared to the zero-crossing voltage (VCM) in ultra-low-cost five-transistor comparators. The subsequent rising-edge detectors (REDs), based on a 3-ns delay cell and an AND gate, generate 20 groups of narrow pulses, which are combined together via two-stage cascaded OR gates.

As phase-interpolating signals are calibrated to be centered at V_CM via CMFB modules and are then discriminated to V_CM in the comparators, high PVT robustness of frequency multiplication is achieved.

Figure 5 shows the detailed timing diagram of the frequency multiplier. The input clock (F_IN) is divided-by-2 to quadrature square waves, which then are converted to orthogonal triangular waves. The following four paths of resistive phase interpolators with a phase step of 18° generate 20-phase square signals at the comparator outputs, which are then converted to 20 paths of narrow pulses by the REDs. All these pulses are finally combined to obtain a high-frequency clock (F_out) with a multiplication factor of 10, as there are 20 output pulses during each two input clock periods.

In this design, V_CM = 0.6 V is generated from the resistive subdivision of a 1.2-V supply. The biasing currents for both comparators and square-triangular converters are generated by a simple current mirror, with the input reference current being externally provided.

4. Experimental Results

The proposed ten-fold frequency multiplier was implemented in a standard 65-nm CMOS, whose layout is shown in Figure 6, where all submodules are clearly demonstrated. A silicon area of 0.06 mm² was observed and the overall power consumption was 0.45 mW from a 1.2-V supply.

Figure 7 shows the post-layout simulated transient waveforms and output frequencies of the frequency multiplier under the power supply (V_DD) fluctuation of ± 10% (1.08 V, 1.20 V and 1.32 V). Centered at 160 MHz, the output frequency had a maximum deviation of 7.5% (155 MHz~172 MHz) from the same 16-MHz input clock.

Figure 8 shows post-layout simulated output frequency components under different process corners (TT/SS/FF) and temperature variations from −40 °C to 90 °C. When the output frequency was located at 160 MHz, it had a maximum deviation of 6.3% (152 MHz~170 MHz).

Figure 9 shows post-layout simulated output spectra under input frequencies of 12–20 MHz and an input power (P_IN) of −2.0 dBm. With a multiplication factor of 10, the output signals were located at 120 MHz/160 and MHz/200 MHz, respectively, with a typical output power (P_OUT) of −9.80 dBm. Spurs less than −28 dB were also observed, which showed good frequency stability. A frequency multiplication efficiency (η) of 9.6% was achieved and depicted in (3) under a power dissipation (P_diss) of 0.45 mW. The proposed frequency multiplicator supports a wide input frequency range of 12–20 MHz or ± 25%.

$$\eta ={\displaystyle \frac{P_{OUT}}{P_{IN}+P_{diss}}}={\displaystyle \frac{0.1047 \mathrm{mW}}{0.6310 \mathrm{mW}+0.45 \mathrm{mW}}}=9.6\%$$

(3)

Frequency multiplication performances are summarized and compared to the existing designs in

Table 1. Performance summary and comparison.

	[3]	[12]	[13]	[14]	[15]	This Work
Technology	65 nm	65 nm	40 nm	65 nm	65 nm	65 nm
Architecture	MR-ILFM	EPCG	MDLL	IL+CAL	R-ILCM	TRPI
VDD (V)	1.0	1.2	1.8/1.1	-	1.1	1.2
FIN (MHz)	4300–5800	80–600	19.2	19.2	120	12–20
Fout (GHz)	22.4–40.6	0.32–2.4	0.15–0.52	0.06–0.96	0.96–1.44	0.12–0.2
Mult. factor	5/7	4	8-27	3-5	8-12	10
Error correction	No	Yes	Yes	Yes	-	No
Pdiss (mW)	10	2.85	2.6	1.6	9.5	0.45
Area (mm2)	0.22	-	0.05	0.06	0.06	0.06
Efficiency (%)	0.33	-	-	-	-	9.6
FoM *	-	-	−58.9	−54.0	−57.2	−53.5

* FoM = 10log₁₀(jitter_rms × F_out × P_diss).

. The figure of merit (FoM) was evaluated to consider the output frequency, root-mean-square (rms) jitter and hardware dissipation. The proposed design achieved attractive features of multiplication efficiency and power consumption.

The proposed work has the following merits: (1) half-digital implementation with small-sized (0.06 mm²) ultra-low-dissipation (0.45 mW) features; (2) a common-mode feedback and comparison mechanism to optimize multiplication efficiency up to 9.6% without error calibration/correction; and (3) a reconfigurable multiplication factor, by modifying the resistor number (k).

5. Conclusions

A small-sized 5-segment triangular-resistance phase interpolation scheme was proposed and implemented in 65-nm CMOS. Under the input frequency of 12–20 MHz, the reconfigurable frequency-multiplication factor centered at 10 was achieved, with a multiplication efficiency up to 9.6% and an ultra-low power consumption of 0.45 mW from a 1.2-V supply.

The proposed frequency multiplier has the following advantages: (1) a reconfigurable multiplication factor depending on the interpolating resistor number; (2) a high-efficiency/low-cost/low-power topology with semi-digital implementation; and (3) high PVT robustness with V_CM calibration and discrimination.