FPGA Design, Implementation, and Breadboard Development of an Innovative SCCC Telemetry + Pseudo-Noise Ranging Satellite System

Abstract

In recent years, missions requiring payload telemetry data transmission to ground stations have increasingly demanded a higher bandwidth. Traditional ranging techniques for spacecraft position determination often use a dedicated spectrum, reducing the available bandwidth for telemetry. To overcome this limitation, a transmission system capable of simultaneously sending high data-rate telemetry and ranging signals within the same bandwidth represents a key advancement for modern space missions, particularly Lagrangian science missions and planetary probes. To enhance the technological readiness of such a system, a hardware demonstrator has been developed using the AMD Xilinx (San Jose, CA, USA) ZCU111 Field Programmable Gate Array (FPGA), selected for its high-speed digital signal processing capabilities and integrated converters. The system, in this preliminary breadboarding phase, operates at a fixed telemetry rate of 4.25 Msym/s and a ranging rate of 2.987 Mchip/s, constrained within a 10 MHz bandwidth typical for science missions. Despite these limitations, tests demonstrated that integrating telemetry with Pseudo Noise (PN) Ranging introduces negligible implementation losses compared to telemetry-only transmission. The system also supports high-order modulations up to 64-APSK, improving spectral efficiency within the available bandwidth. Although some limitations have been found in the use of very high-order modulations, this prototype demonstrates the feasibility of integrating advanced coding techniques with PN Ranging.

1. Introduction

Over the past decade, the demand for a higher downlink throughput in satellite communications has significantly increased, driven by advancements in satellite payload technology [1,2,3]. To address the challenge of transmitting such large data volumes, coding and modulation techniques have evolved to include high-order modulation schemes and adaptive channel techniques, such as Variable/Adaptive Modulation (VCM/ACM). Types of such communication systems include the Consultative Committee for Space Data Systems (CCSDS) 131.2-B standard [4] and the European Telecommunications Standards Institute (ETSI) Digital Video Broadcasting—Satellite Second Generation (DVB-S2) standard [5]. Concerning the CCSDS 131.2-B, it incorporates advanced Forward Error Correction (FEC) techniques, such as Serially Concatenated Convolutional Codes (SCCCs), alongside modulation formats supporting up to 64-APSK, with high coding rates reaching 0.91. These features improve spectral efficiency while maintaining robust data transmission, leveraging adaptive modulation and coding techniques.

While these characteristics were originally designed for Low Earth Orbit (LEO) scenarios, the challenge of transmitting large volumes of data within a limited bandwidth has also arisen in scientific missions, such as those involving Lagrangian points or planetary exploration. In contrast to LEO communications, which currently benefit from broader bandwidth allocations around 600–650 MHz in the Ka/Ku spectrum, scientific missions typically operate within much narrower bandwidths, often around 10 MHz. Additionally, missions far from Earth require precise positioning techniques [6,7] that cannot be achieved with widespread systems like GNSS (GPS, Galileo, etc.), as for LEO missions. These positioning procedures rely on the transmission and reception of dedicated signals, which require proper bandwidth allocation. In cases of limited bandwidth, the allocation for ranging (RG) shares the same bandwidth as telemetry (TM), meaning the satellite shall temporarily disable telemetry transmission during ranging measurements, which take several hours depending on the mission. As a result, the already limited data rate available with traditional modulation techniques such as GMSK, BPSK, and QPSK is further reduced, making overall data transmission a key limiting factor.

To address this limitation, a transmission architecture that enables the simultaneous transmission of GMSK and PN Ranging according to CCSDS 414.1-B [8] has been developed and presented in the CCSDS 413.1-G-2 green book [9]. The latter technique has already been implemented in several institutional missions, including Solar Orbiter and BepiColombo [10], and is also planned for future missions such as EnVision [11] (although EnVision will have a larger bandwidth allocation compared to the previously mentioned 10 MHz). However, the use of GMSK + PN Ranging only partially addresses the data return volume issue, as transmitting both signals simultaneously requires a reduction in the TM rate to comply with the strict bandwidth limitations.

In order to further increase the data rate while preserving the advantages of simultaneous TM + RG transmission, the main solution is to enhance the spectral efficiency of the telemetry signal. Drawing inspiration from the LEO standard mentioned earlier, the approach is to combine high-order modulations with PN Ranging, thereby boosting the overall net data return compared to the GMSK telemetry case. In the context of CCSDS 131.2-B, the maximum spectrally efficient coding and modulation (ModCod) pair theoretically guarantees 5.4 bits/Hz (coded), which is significantly higher than the maximum 1 bit/Hz uncoded value of GMSK transmission (further decreased after coding). This advantage would ideally result in a significant improvement in data volume, which could be leveraged in future missions such as M7 M-Matisse and Theseus [11].

To analyze this solution, theoretical studies have been conducted in recent years to simulate such a transmission system [12,13]. These studies concluded that, from a theoretical perspective, the performance of this system is suitable for use in science missions. However, some limitations were identified, particularly due to spectral regrowth impacting the bandwidth occupation compared to the GMSK case, which benefits from a constant envelope. While these studies confirmed the functionality of the system, many parameters were considered to be idealized, and the receiver was “genie-aided”, meaning that some characteristics of the input waveform were known, even though this would not be the case in a real-world receiver. For this reason, further studies were needed.

Taking into account such studies, authors designed and developed a breadboard prototype capable of simultaneously transmitting signals based on CCSDS 131.2-B [4] telemetry and CCSDS 414.1-B [8] ranging. Therefore, this system serves as an initial hardware-based validation platform, enabling the verification of transmission in a more realistic scenario. To achieve this, the hardware implementation includes all the necessary modules for actual communication, without any a prior knowledge of the input signal, except for known link configuration parameters such as the symbol rate, chip rate, telemetry Square Root Raised Cosine (SRRC) filter roll-off, modulation index, and ranging code type. Specifically, the system also implements the dynamic configuration changes in the encoding and modulation scheme, thus enabling support for VCM/ACM techniques.

To the best of the authors’ knowledge, no existing state-of-the-art hardware solutions have been developed for such a specific system. Therefore, this work represents an innovative starting point in the field of satellite communication hardware development and engineering research. This paper presents the modeling, breadboarding, and architectural features that enable this transmission scheme. The breadboard comprises three primary modules, all implemented on the same AMD Xilinx ZCU111 (ZynQ Ultrascale+ RFSoC FPGA) development board and interconnected via analog SMA cables. The constituent modules, as shown in Figure 1, are the following:

• The Transmitter Module generates telemetry and ranging signals independently. These signals are then phase-modulated onto one another to create the combined output. All processing occurs in the baseband, while the up-conversion to intermediate frequency is performed directly by the Digital-to-Analog Converter (DAC).
• The Channel Emulator introduces noise into the clean input waveform to simulate the signal-to-noise ratio (SNR) conditions relevant to real application scenarios. All functions related to setting the E_S/N₀ operating point are handled in the baseband, while the down-conversion and the following up-conversion are performed by the embedded Analog-to-Digital Converter (ADC) and DAC, respectively.
• The Receiver Module is the most complex module in the breadboard, containing a full SCCC receiver and a PN-Ranging receiver, along with the necessary algorithms for signal reconstruction and cross-cancellation. To recover both TM and RG from the received signal, two nested loops are required for acquisition, reconstruction, and cancellation. Specifically, the receiver first acquires the TM signal, enabling its cancellation from the TM + RG input, thus isolating the RG component. During this initial phase, the isolated RG component may be affected by increased noise due to residual demodulation errors in the telemetry. The RG signal is then acquired, reconstructed, and canceled from the TM + RG signal, allowing for the extraction of a cleaner telemetry signal. Once the two loops converge, the telemetry demodulator is presented with a clean signal, enabling it to achieve performance curves similar to those of a TM-only transmission. The processing is similar to that described in [9].

The presented architecture, while not supporting full two-way transmission as in a real satellite communication system, allows for a comprehensive evaluation of telemetry and ranging performances. As such, it provides a cost-effective approach to assess the system’s real behavior in a relevant scenario without relying on a priori knowledge.

In summary, the hardware prototype developed in this study represents an innovative advancement in satellite communications, providing a practical solution for the simultaneous transmission of telemetry and ranging signals while ensuring dynamic modulation and efficient bandwidth utilization. This research was carried out within the framework of a European Space Agency (ESA) activity, aimed at demonstrating the feasibility of such a system in real-world scenarios—going beyond previous theoretical and simulation-based studies [12,13]. The results of this work not only confirm the viability of this approach but also lay the foundation for future advancements in satellite communication hardware, addressing the increasing demands for high data-rate telemetry and precise ranging in challenging environments.

The reminder of this paper is organized as follows:

• Section 2 presents algorithms implemented for the transmitter module and the related architecture;
• Section 3 presents algorithms implemented for the channel emulator module and the related architecture;
• Section 4 presents algorithms implemented for the receiver module and the related architecture;
• Section 5 presents the main results obtained by designing the proposed system in VHDL and implementing it on the breadboard;
• Section 6 presents the conclusion of this work.

2. Transmitter

This section details the architectural solution for the SCCC + PN-Ranging transmitter, which is composed of two distinct transmitters that are later combined to the generate the output waveform. The first one generates an SCCC telemetry signal at eight times the symbol rate using the CCSDS 131.2-B Intellectual Property (IP) Core developed by IngeniArs S.r.l. [14] (Pisa, Italy). The main goal of this initial prototype was to validate the findings of previous theoretical studies and to address limitations stemming from genie-aided assumptions used in those works. Given the exploratory nature of the activity and the limited budget allocated by ESA, the system was intentionally required to implement a simplified configuration of data rates. In particular, only a single set of symbol and chip rates was implemented to reduce overall complexity and development effort. The chosen telemetry symbol rate was 4.25 Mbaud, corresponding to a 34 Msps output rate at the telemetry transmitter. This value was selected based on earlier considerations related to the 10 MHz bandwidth constraint, as discussed in [12,13]. Operating in parallel, the second transmitter generates the PN-Ranging signal by producing the PN sequence and applying phase modulation at the same output sample rate as the telemetry signal (i.e., 34 Msps). The two generated signals are then combined through a complex multiplier, producing the simultaneous TM + RG signal. This combined signal is then forwarded to the output interface, which includes an up-sampler to 816 Msps and the Xilinx DAC interface [15] (clocked at 3264 Msps). The adoption of such a high sample rate was necessary to enable direct RF synthesis at carrier IF = 620 MHz, similar to IFs of actual ground stations, such as ESA TTCP.

The general architecture of the transmitter is illustrated in Figure 2, showing the sample rates throughout the transmission chain. A detailed description of both transmitters is provided in the following subsections.

2.1. CCSDS 131.2-B Telemetry Transmitter

The architecture of the breadboard telemetry transmitter is illustrated in Figure 3, where all blue blocks represent the processing blocks within the SCCC-TX IP-Core developed by IngeniArs [14]. Specifically, the IP Core receives a PN23 sequence from a hardware generator, processes it according to the CCSDS 131.2-B [4] standard, and forwards it to the telemetry + ranging combiner. The use of PN sequences for the data enables a straightforward method for measuring Bit Error Rate (BER) curves, allowing for an accurate evaluation of the telemetry section’s performance.

The SCCC signal generation process involves input data adaptation and slicing based on the current ModCod configuration. It then applies SCCC encoding, consisting of two convolutional encoders with an interleaver between them, followed by Physical Layer (PL) framing generation. The PL frame, whose construction is depicted in Figure 4, serves as the fundamental physical structure for transmission.

This structure enables the telemetry receiver to reconstruct the position of data blocks for the decoder while supporting data-aided algorithms for impairment recovery as well, a crucial aspect when using high-order modulations such as 16-APSK and beyond [16]. Moreover, this structure facilitates the implementation of VCM or ACM techniques by leveraging the header data embedding the ModCod value. This value informs the receiver about the coding scheme applied to the data payload, enabling dynamic adaptation to channel conditions.

The telemetry section’s configuration changes are managed through an AXI4-Lite monitoring and control interface (Figure 3), enabling the on-the-fly reconfiguration of internal parameters. In particular, the ability to dynamically reconfigure the ModCod at runtime without interrupting the frame stream is a mandatory requirement for an ACM/VCM approach and has therefore been implemented in this system.

From an implementation perspective, the entire telemetry section operates at a clock rate of 34 MHz, with a fixed symbol oversampling factor of eight, resulting in a symbol rate of 4.25 MBaud in serial mode. Due to the lower symbol rate requirements for science missions compared to LEO missions, the output of this section is provided as a straightforward serial stream of samples, obtained by serializing the output of the SRRC filter.

2.2. Ranging Transmitter

The ranging transmitter can generate both T2B and T4B PN sequences [8], which are implemented with sinusoidal shaping, allowing the user to adjust the modulation index. These parameters can be configured in real time via an AXI4-Lite configuration and status interface. Specifically, the Pseudo-Noise Ranging transmitter generates a signal with baseband pulse shaping, defined as in Equation (1), where $T_c$ represents the chip period.

$$h_{RG}\left(t\right)=h_{RG-sin}\left(t\right)=\left\{\begin{array}{cc}\{sin\left({\displaystyle \frac{\pi t}{T_c}}\right)\hfill & \hfill tϵ[0,T_c]\\ 0\hfill & \hfill elsewhere\end{array}\right.$$

(1)

Subsequentially, the module creates the complex baseband signal, as represented in Equation (2), where m_IDX is the modulation index and c(t) identifies the pseudo random sequence, selected (i.e., T2B or T4B) over time.

$$s_{RG}\left(t\right)=e^{i·m_{IDX}·c\left(t\right)·h_{RG}\left(t\right)}$$

(2)

The transmitter operates based on the chip sequence c(t), generated in accordance with the recommendation in [8], which specifies the use of T2B and T4B codes. Both sequences share the same six-component binary structure, implemented using linear-feedback shift registers (LFSRs). The outputs of these registers are combined according to the selected code type using a simple weighting function, which can be easily adjusted at runtime. Figure 5 illustrates the structure of the T2B and T4B sequence generators as defined in the standard and implemented in the breadboard.

From an architectural perspective, the signal generation relies on a 36-bit Numerically Controlled Oscillator (NCO), which is used to count the chip duration with high precision, controlling both the code generator increment and the position for sine shaping. The sine shaping and phase component extraction, which represent $s_{RG}\left(t\right)$ using cartesian components, are implemented through high-resolution lookup tables with 16-bit addresses. Therefore, the overall architecture enables the signal to be generated at any sampling rate, with the rate chosen to be 34 Msps in the breadboard for alignment with the telemetry rate, facilitating an efficient signal combination.

2.3. Telemetry and Ranging Combiner

The two independent signals are then combined. Since the ranging signal is purely phase-modulated, it can be seamlessly added to the telemetry signal using complex multiplication between the cartesian components of the two signals. This operation results in a transmitted telemetry constellation that appears to be affected by a wide phase noise effect, as illustrated in Figure 6.

Such modulation also impacts the system’s occupied bandwidth due to the convolution of the main ranging chip tones with the telemetry spectrum in the frequency domain. This effect is illustrated in Figure 7, where the “shoulder effect” of this convolution can be observed. The influence on the 99% power bandwidth occupation has already been thoroughly analyzed in [13]. Figure 7 illustrates the combined spectrum for the case where telemetry employs an SRRC filter with a roll-off factor of 0.35, while the ranging signal utilizes a T2B code with a modulation index of 0.20 rad-pk.

3. Channel Emulator

The channel emulator is the subsystem in charge of reproducing the main impairments affecting the satellite downlink during transmission. Specifically, it introduces Additive White Gaussian Noise (AWGN) to the transmitter module’s output signal. The emulator allows for the selection of the noise generation level within the range of [−4 dB, 30 dB] of E_S/N₀. The architecture of the designed channel emulator is shown in Figure 8.

Initially, the overall module’s input is sampled at 3264 Msps using the integrated ADC blocks from Xilinx (San Jose, CA, USA) (the same sample rate used in the transmitter DAC). This is followed by a down-conversion to the baseband, simplifying processing for downstream blocks. The ADC’s baseband output samples are then decimated by a factor of eight using Xilinx’s hard-coded decimators, reducing the sample rate to 408 Msps. The signal is further down-sampled using two half-band filter decimators, reducing the sample rate to 102 Msps for more efficient data processing and management.

Next in the processing chain is the Digital Automatic Gain Control (DAGC) module, which adjusts the input power level to ensure the noise amplitude is appropriately scaled, setting the correct operating point for the receiver system. The AWGN is then introduced into the signal by the corresponding block, with the ability to dynamically adjust the E_S/N₀ value through the AXI4-Lite status and configuration interface.

Finally, the signal is up-sampled back to 408 Msps using a pair of half-band filters, designed similarly to the input ones. The sample rate is then further up-sampled by a factor of eight using the internal interpolators embedded in the Xilinx Data Converter blocks [15]. This process restores the sample rate to the channel emulator’s original input rate of 3264 Msps, which is appropriate for up-conversion to the 620 MHz intermediate frequency. Since both the input ADC and output DAC clocks are derived from the same source, no timing drift impairment is introduced during this process.

4. Receiver

The final and most complex system component is the receiver, whose architecture is shown in Figure 9. It consists of five primary blocks responsible for processing the input signal and reconstructing both telemetry and ranging signals.

The received signal (i.e., TM + RG) is first sampled by the ADC and then decimated to an integer multiple of the symbol rate. This reduces the sampling rate, facilitating data processing without compromising system performance, as the oversampling factor remains high relative to the telemetry and ranging rates. After decimation, each sample is assigned to a timestamp, referred to as a time tag, which is used to align the reconstructed signals with the input ones. The samples are then forwarded to the telemetry processing block, which is responsible for compensating frequency, phase, and amplitude impairments, as well as performing constellation de-mapping and decoding. Additionally, the telemetry processing chain includes SCCC decoding for BER statistics plotting. The de-mapper output data (i.e., uncoded data bits) are then used for TM signal reconstruction, enabling PL-frame regeneration from the uncoded bit stream.

Subsequentially, the reconstructed telemetry frame is used by the ranging processing block for its cancellation on the ranging row, with all operations performed at the same integer multiple of the symbol rate (i.e., at 34 Msps). The output of the cancellation process is then decimated to an integer multiple of the chip rate and adjusted in amplitude, frequency, and phase before tracking the chip timing and aligning it with the ranging code epoch. Finally, the ranging signal is reconstructed and used in the telemetry processing branch to remove the ranging “interference”.

Regarding the involved signals, the received one can be modeled as in Equation (3), where $x_{TM}$ represents the amplitude of the telemetry signal, whereas ${\phi }_{TM}$ and ${\phi }_{RG}$ represent the phase modulation of the telemetry and ranging, respectively. The total signal is impaired by a frequency offset ($f$), which is assumed to be constant for this analysis, by a timing offset ($\tau$), still approximated as a constant, and by AWGN ($w_i$).

$$r\left(t\right)=x_{TM}\left(t-\tau \right)e^{i\left(2\pi ft+{\phi }_{TM}\left(t-\tau \right)+{\phi }_{RG}\left(t-\tau \right)\right)}+w_i(t)$$

(3)

Regarding the contribution of telemetry cancellation in the ranging path, the RG signal can be obtained by multiplying the received input with the complex conjugate of the reconstructed telemetry signal, as shown in Equation (4). For this operation, the only impairments that need to be compensated during telemetry reconstruction are the timing offset (τ) and signal amplitude. The latter constraints are needed to approximate $x_{TM}\left(t-\tau \right){·x}_{TM-rec}\left(t-\tau \right)\approx 1$, or at least to ensure that its expectation is equal to 1. As a result, the ranging signal remains affected by timing offset, frequency offset, and AWGN noise.

$$\begin{array}{c}{r}_{c-rg}\left(t\right)=\left[x_{TM}\left(t-\tau \right)e^{i\left(2\pi ft+{\phi }_{TM}\left(t-\tau \right)+{\phi }_{RG}\left(t-\tau \right)\right)}+w_i\left(t\right)\right]\left[x_{TM-rec}\left(t-\tau \right)e^{i\left(-{\phi }_{TM}\left(t-\tau \right)\right)}\right]\approx \\ {{|x}_{TM}\left(t-\tau \right)|}^2{e}^{2\pi ft+{\phi }_{RG}\left(t-\tau \right)}+w_a\left(t\right)\approx e^{2\pi ft+{\phi }_{RG}\left(t-\tau \right)}+w_a\left(t\right)\end{array}$$

(4)

In practice, the imperfect cancellation of telemetry in the ranging arm results in an increased noise level. As detailed in [13], this noise-like effect introduces a floor in the ranging jitter performance. On the other hand, for ranging modulation removal in the telemetry arm, the TM signal is obtained by multiplying the total received signal by the ranging signal, as shown in Equation (5). Specifically, the reconstructed ranging signal only needs to match the timing of the input. This alignment can be achieved by leveraging the cyclic nature of the ranging code sequence, which exhibits a specific periodicity [8].

$$\begin{array}{c}{r}_{c-tm}\left(t\right)=\left[x_{TM}\left(t-\tau \right)e^{i\left(2\pi ft+{\phi }_{TM}\left(t-\tau \right)+{\phi }_{RG}\left(t-\tau \right)\right)}+w_i\left(t\right)\right]\left[e^{i\left(-{\phi }_{RG}\left(t-\tau \right)\right)}\right]\approx \\ {{(x}_{TM}\left(t-\tau \right))}^2{e}^{2\pi ft+{\phi }_{TM}\left(t-\tau \right)}+w_b\left(t\right)\end{array}$$

(5)

The next subsections detail the modules for the processing and reconstruction operations of TM and RG signals.

4.1. Telemetry Receiver Processing

The telemetry receiver submodule is based on the SCCC-RX for science projects, developed by IngeniArs S.r.l. [17,18], the architecture of which is depicted in Figure 10, including internal loops and uncoded/coded output separation as well.

The received input signal, sampled at 34 Msps, is first corrected for residual frequency offset using a feedback approach based on data-aided statistics from the Frame Marker (FM) field in each received PL frame (Figure 4). This architecture is necessary due to the lack of prior knowledge about the modulation type and the need to support high-order modulations. As a result, timing recovery and frame synchronization must be performed in a non-coherent mode, thus sustaining large carrier offsets at the beginning of each satellite pass.

For this reason, the Gardner algorithm has been selected as the timing recovery algorithm because of its insensitivity to large carrier offsets [16]. In particular, the timing recovery block foresees an automatic gain control (AGC) for properly tuning the loop bandwidth before timing loop processing. In addition, since the signal amplitude is critical for telemetry reconstruction for cancellation, the gain imposed by such an AGC shall be stored and propagated. Furthermore, the timing fractional offset applied by the interpolator within the timing recovery loop shall also be saved for back-compensation during the reconstruction.

For frame synchronization and PL-frame start detection, the module employs a double-correlation algorithm [19] that leverages Frame Marker symbols, represented by a known 256-symbol sequence, modulated using a π/2-BPSK scheme. Subsequently, the detector output is validated through index matching, ensuring consistent index detection across multiple windows, each having the same length as a PL frame.

Once the frame start position is estimated, frequency offset is corrected using the previously mentioned feedback mechanism. Specifically, the selected algorithm for the carrier offset estimation is the Mengali and Morelli method [20], which provides a wide estimation range of 40% of the symbol rate. This enables support for a 4.24 Mbaud signal and allows frequency offset estimation of up to 1.7 MHz, covering all possible LEO satellite scenarios [16]. Moving to the next blocks, phase correction is implemented with a feed-forward data-aided algorithm that operates on known PL-frame data, specifically the Frame Marker (FM) and the distributed pilot symbols [21]. The estimated phase values are then linearly interpolated between fields to also compensate for the residual frequency offset.

The ModCod identification is then performed by the Descriptor Decoder module, which operates using a maximum likelihood algorithm to search for all possible values of the Frame Descriptor field within the PL frame [4,21]. The module declares the ModCod as the one yielding the highest correlation among all possible combinations. For SNR estimation and AGC, the architecture follows the approach presented in [21], with the added requirement that the amplitude correction applied by the AGC is forwarded to subsequent modules for use during the telemetry reconstruction phase. Specifically, the gain applied at the input within the timing recovery loop must be multiplied by the gain applied by the AGC before the symbol de-mapper and append it as side information to the data stream. Finally, constellation de-mapping is performed to derive Log-Likelihood Ratios (LLRs) and related hard-decision bits for the telemetry reconstruction. Meanwhile, the LLRs are also forwarded to the SCCC decoder, which is used to generate BER curves for system performance evaluation, as shown in Figure 9.

4.2. Telemetry Reconstruction and Cancellation

The telemetry receiver reconstruction is based on hard-decoded bits obtained from LLR estimation. These bits are immediately reused, along with information such as the ModCod and the presence of pilots, to regenerate the PL frame. However, the regenerated frame symbols may be affected by bit errors due to the current operating point. The system must then be capable of locking onto the ranging signal even in the presence of such impairments. Then, the signal amplitude and timing are corrected by applying inverse adjustments to the reconstructed signal, using the additional information stored during the telemetry demodulation process. The latter are carried out with a Farrow structure [22], which implements a third-order polynomial interpolation, similar to that implemented when performing all fractional alignments and decimations. As a result, the reconstructed signal is corrected in timing to match the receiver’s input signal and amplitude to ensure consistency between the reconstructed and received telemetry signal amplitudes. Notably, only the telemetry amplitude is matched, even though all AGCs operate on the combined TM + RG + AWGN signal power.

With the reconstructed signal generated, telemetry cancellation over the ranging signal is implemented using timestamps and a circular buffer. The buffer stores samples from the ranging arm, which are then read based on the timestamp provided by the telemetry reconstruction process (where time tags are propagated along with the data during the demodulation and the reconstruction phases). This results in automatic delay compensation, enabling precise cancellation.

4.3. Ranging Receiver Processing

Following the removal of the telemetry signal, the system proceeds with processing the ranging signal. The first main stage involves sample rate adaptation to an integer multiple of the chip rate. This is followed by chip timing recovery and code epoch detection, which are key steps before reconstructing the ranging signal for subsequent cancellation on the telemetry branch. The general architecture of the ranging receiver is illustrated in Figure 11. In addition to the core processing stages, the design incorporates automatic gain control blocks and frequency/phase correction loops. These components are essential for ensuring a stable and reliable signal before it reaches the subsequent blocks responsible for resolving the sampling timing and tracking of T2B/T4B code.

In the ranging chain, the input sample rate of 34 Msps is not an integer multiple of the chip rate, which is a requirement for the chip tracking loop (CTL) module implementing the timing recovery loop. This module relies on the “mid-phase integration” algorithm, which is straightforward to implement when the oversampling factor is both an integer and even with respect to the chip rate. To overcome this issue, a fractional decimator is employed to adjust the sample rate to eight times the chip rate (i.e., 23.896 Msps). Specifically, the chip rate is set to be lower than the symbol rate (value fixed to 2.987 Mchip/s); therefore, a fractional decimator using a third-order polynomial interpolation based on a Farrow structure [22] is employed. Then, the decimated signal at 23.896 Msps undergoes frequency and phase correction using a Costas loop [23] approach, designing a classical architecture with a complex baseband input and multipliers for the in-phase and quadrature rows.

Afterward, the signal is adjusted to ensure power level consistency at the CTL module’s input. This step is crucial for setting the working point of the time tracking loop, which is only sensitive to the power of the ranging signal (i.e., the S-curve is noise-invariant). Since a standard AGC normalizes the entire input signal, including both the ranging signal and AWGN in this case, a modification has been introduced to adjust and normalize only the ranging component (scaling the noise accordingly). This adjustment is achieved using an SNR estimator based on the M₂M₄ algorithm (i.e., second and fourth moment-based estimation) [24], which determines the gain target of the AGC. Indeed, by knowing the SNR, a scaling coefficient can be derived, allowing the target gain to be set according to Equation (6).

$$\begin{array}{c}A=\sqrt{{\displaystyle \frac{SNR+1}{SNR}}}\\ \left\{\begin{array}{c}{P}_{RG}+P_N=1\\ {A^{2}P}_{RG}=1\end{array}\right.\end{array}$$

(6)

Then, chip timing recovery is performed using the chip tracking loop, whose architecture is shown in Figure 12. This loop is similar to the telemetry timing recovery loop, but employs a different Timing Error Detection (TED) and a different method for output value extraction. The CTL exploits a mid-phase integrator TED to integrate the ranging signal over [−T_C/2, +T_C/2] around the ideal sampling point, scaled by a step. The output of this estimator is multiplied by an alternate sequence to partially compensate for the effect of the unknown ranging code (i.e., T2B or T4B). On the output side, an in-phase integrator sums the samples over a chip period without the step multiplication effect, yielding the chip pulse area. This approach mitigates noise effects compared to methods relying solely on sampling point values, benefiting from the direct binary transmission of the ranging signal.

After integration, code acquisition is performed using correlator banks to align the sub-codes that constitute the ranging sequence. The receiver employs six correlator banks, each containing at least two sub-correlators (i.e., as the positions in Figure 5). Given the resource flexibility of ground-based architectures, all 77 sub-correlators (i.e., one for each sub-code and phase shift [8]) operate in parallel, minimizing acquisition latency.

Each sub-correlator integrates the input chips with one of the code generator sequences, which are eventually phase-shifted over a specified number of chips. The correlation outputs are then sent to a decision block (maximum peak search block), which identifies the sub-correlator with the highest correlation as the correct one. This corresponds to finding the phase rotation of each code generator as in the transmitter, allowing the determination of the beginning of the epoch. The corresponding code delay is determined and passed to the next module, which uses it to assert the code lock flag. The overall architecture of the code acquisition block is depicted in Figure 13.

Finally, lock declaration relies on a multi-window searching approach. Indeed, the lock is confirmed only if two consecutive integration periods produce the same code delay, thus ensuring a low false-lock probability, crucial for incorrect RG reconstruction prevention. An incorrect acquisition would in fact result in an erroneous reconstruction and cancellation, ultimately degrading telemetry conditions (even if the system assumes the loops are functioning correctly and operating in a cooperative way). Conversely, unlock is declared whenever four consecutive integration periods yield different or incorrect code delays relative to the locked one. This situation typically occurs during a cycle slip in the TM or RG recovery loops, which necessitates a complete re-acquisition procedure.

4.4. Ranging Reconstruction and Cancellation

This section presents the architecture and functionalities of the receiver submodule dedicated to the reconstruction of the ranging signal and its cancellation on the telemetry processing chain. The complexity of this operation arises from the need to leverage the cyclic behavior of the ranging code to determine the sample values required for cancellation. To achieve this, the proposed approach utilizes a timestamp (i.e., time tag) and the fractional delay applied within the Clock Tracking Loop (CTL) to estimate both the position of the cancellation pulse and the corresponding chip value at the input of the telemetry processing arm.

Chip pulse alignment is ensured by propagating timestamps through the ranging processing chain, as illustrated in Figure 14. Specifically, two fractional timestamp adjustments occur within the chain. The first adjustment accounts for the decimation from 34 Msps to 23.896 Msps, performed by simply adding the fractional delay to the input timestamps, since the reference sampling point is initially set at 34 Msps. The second adjustment is applied by the CTL, which estimates a fractional delay that is referenced to the 23.896 Msps sample rate. Consequently, this value must be rescaled to the 34 Msps reference to maintain consistency across both the ranging and telemetry processing branches. This approach ensures stable time tracking, expressed in 34 Msps pulses, between the input sample and chip pulse peak, allowing for the precise estimation of the time tag within the ranging pulse interval.

Once the time tags have been propagated and the code epoch has been identified, the timestamp difference between a known chip within the epoch and the timestamp at the input of the processing chain can be determined. This difference, when divided by the nominal chip pulse duration and the estimated chip rate error, enables a precise estimation of the chip to be generated for cancellation. The generated chip is then subtracted from the TM+RG signal, effectively removing the “phase noise-like” contribution of the ranging signal and extracting a cleaner telemetry signal. This operation finalizes the second cancellation loop, bringing the system to its fully operational state, where the two nested loops work in a cooperative manner to ensure optimal telemetry and ranging signal separation.

5. Results

This section presents the key results from the implementation, analysis, and validation campaign of the SCCC + PN-Ranging breadboard. The goal was to assess system performance for both telemetry and ranging. For the telemetry component, BER curves were used to quantify implementation losses compared to an SCCC-only transmission. This provided a measure of signal quality, thus characterizing the impact of ranging presence on the downlink data transmission. For the ranging component, jitter measurements served as the primary evaluation metric, and the observed values were compared against theoretical curves to verify whether the system met the expected performance [9,13].

As mentioned in Section 1, the current demonstrator has been designed with limited configurability, as both the symbol rate and chip rate are fixed. Nevertheless, the system enables a generalized performance evaluation, since these rates are not directly linked (i.e., long fractional relationship), which helps mitigate timing dependencies that could otherwise falsify the results. This constraint remains the only significant limitation, as the transmitter and receiver offer full configurability for the other parameters, including SRRC roll-off, telemetry ModCod, ranging code type (T2B or T4B), modulation index, and more. However, for performance evaluation in the test campaign, some parameters have been kept static in order to reduce the number of test cases. The results presented in this chapter are therefore based on the following settings:

• Telemetry symbol rate: 4.250 Msym/s;
• Telemetry SRRC roll-off: 0.25;
• Ranging chip rate: 2.987 Mchip/s;
• Ranging code type: T2B;
• Ranging modulation index: 0.20 rad-pk.

Concerning receiver parameters, loop bandwidths of the TM and RG timing recovery section were also set to constant values:

• Telemetry timing equivalent loop bandwidth: 10⁻⁵ (tuned @ E_S/N₀ = −2 dB);
• Ranging timing loop bandwidth: 2.5 kHz (constant).

As already mentioned, for the implementation, authors have used the ZCU111 RFSoC board from Xilinx, which embeds high speed ADCs and DACs in a friendly manner to the developer (compared to JESD204B interfaces). Implementation results are detailed in

Table 1. Breadboard resource occupation on the ZCU111 development board.

Module Name	CLB LUTs	CLB Regs	DSP	BRAM	URAM
TM Transmitter	16,727	21,389	212	137	0
RG Transmitter	611	923	1	22.5	0
TX Combiner	791	1150	8	1.5	0
CH Emulator	4816	5815	46	4	0
TM + RG Receiver	150,431	108,751	896	388	67
TOTAL	173,376 (40.76%)	138,028 (16.23%)	1163 (27.22%)	553 (51.20%)	67 (83.75%)

, showing the individual occupation of the transmitter, channel emulator, and receiver sections in terms of the number of specific Xilinx FPGA cells/blocks used. The report clearly indicates that the most complex block in the breadboard is the receiver, which occupies almost 86% of the required CLB LUTs and almost 78% of all CLB REGs. Furthermore, the main memory utilization (indicated with Block-RAM and Ultra-RAM occupation) is also entitled to the BCJR SCCC decoder section within the receiver block. Finally, Xilinx DSP macrocells are mainly used in the transmitter section for the pulse shaping filter, while the receiver section uses such blocks for the telemetry synchronization algorithms and reconstruction (including receiver match filtering and resampling modules).

The first parameter to be characterized, as is also done in the related system simulation on which the breadboard is based, was the lock-in capability at very low SNR levels (i.e., around 0 dB E_S/N₀). The E_S/N₀ ≈ 0 dB condition represents the lower bound operational point defined in the CCSDS 131.2-B standard [4,21]. At such a low E_S/N₀, the objective was to minimize the “phase-noise-like” effect introduced by the ranging signal on telemetry. This was crucial to ensure that the residual BER at the constellation de-mapper output remained low enough to allow the subsequent acquisition of the ranging signal (as the BER itself acts as an interferer on the ranging channel due to incorrect regeneration and cancellation). To determine an optimal configuration, a modulation index sweep was performed. The results identified 0.2 rad-pk as a suitable operating point (and also values below such), ensuring a system lock probability above 99% under these conditions.

Then, telemetry BER tests were performed to evaluate implementation losses due to synchronization algorithms (i.e., timing, phase, and frequency recovery), quantization effects, and cross-cancellation accuracy related to reconstruction/cancellation alignment. The results indicated that, with T2B and a modulation index of 0.2 rad-pk, no significant implementation loss was observed when compared to the TM-only transmission for ModCod 1 (QPSK), ModCod 7 (8-PSK), ModCod 13 (16-APSK), and ModCod 18 (32-APSK), as shown in Figure 15. These findings highlight the robustness of the TM+RG system across various modulation schemes, with minimal performance degradation attributed to the implemented algorithms and system architecture (loss is below 0.1 dB).

However, for 64-APSK (i.e., ModCod 27) with a modulation index 0.2 rad-pk, the tests highlighted an implementation loss of approximately 2.1 dB compared to the TM-only curve, as depicted in Figure 16. Further analysis indicated that the cross-cancellation algorithm was functioning correctly, as verified through ranging jitter and SNR measurements, performed with and without RG cancellation activated; therefore, it was excluded as the main cause of the losses. To underline that theoretical and simulative evaluations currently available in the literature are based exclusively on uncoded BER curves and do not provide any information about the cross-cancellation interaction of estimators, jitter was used during demodulation. Therefore, the observed performance degradation could be currently attributable either to theoretical limitations or to external impairments affecting the SCCC + PN-Ranging signal in the case of 64-APSK ModCods. However, given the preliminary nature of the hardware demonstrator, the intrinsic complexity of the dual-loop interactions, and the potential for the system-level mitigation of these effects, an in-depth investigation into these phenomena was considered outside the scope of ESA activity. Further investigations to identify the underlying mechanisms, define the specific origin of the observed loss, and characterize the associated limitations will surely be part of future work. However, these phenomena do not compromise the overall functionality and assessment of the transmission scheme, thereby fulfilling the primary objective of ESA activity.

Indeed, as shown in Figure 17, despite this limitation, the observed loss for 64-APSK can be effectively mitigated by employing a lower modulation index, e.g., 0.1 rad-pk. This adjustment has minimal impact on ranging performance, as 64-APSK is typically utilized only in high-SNR scenarios where ranging jitter is primarily constrained by the residual TM modulation; the system actually works with jitter values close to the saturation region depicted in Figure 18 for the QPSK case.

Regarding ranging jitter performance, it is important to note that it is closely related to the timing loop bandwidth. Therefore, ensuring that both the theoretical analysis and hardware implementation share the same equivalent loop bandwidth is essential for accurate comparability. The main challenge arises in hardware, where there is no prior knowledge of the input power and noise level. Since the loop bandwidth is influenced solely by the ranging signal power (S), and the input consists of both signal and noise, the normalization of S is required. To achieve this, an interaction between the AGC and an SNR estimator was implemented, as detailed in Section 4.3. Specifically, the TED of the CTL is only responsive to the ranging component of the input signal, which is a fraction of the total power according to the modulation index.

The resulting jitter measurements are illustrated in Figure 18, where they are compared to the theoretical curves for the linear region (yellow) and the saturation region (violet). Related values are also detailed in

Table 2. Ranging jitter curve−ModCod 1 (QPSK), 0.2 rad-pk.

Es/N0	0 dB	5 dB	10 dB	15 dB	20 dB	25 dB	30 dB
Theory (Linear region)	−22.73 dB	−27.73 dB	−32.73 dB	−37.73 dB	−42.73 dB	−47.73 dB	−52.73 dB
Theory (Saturation region)	−49.90 dB	−49.90 dB	−49.90 dB	−49.90 dB	−49.90 dB	−49.90 dB	−49.90 dB
Simulated model	−23.54 dB	−28.01 dB	−33.06 dB	−37.94 dB	−42.15 dB	−45.28 dB	−45.98 dB
Measured	−23.73 dB	−27.95 dB	−33.07 dB	−38.06 dB	−42.23 dB	−45.21 dB	-

. The saturation value considered for this test has been obtained according to [12,13], along with all considerations about the high-order modulation interaction in the ranging performances when simultaneous transmission is implemented (specific details about interactions are provided in Chapter 4 of [13]).

The linear region is primarily influenced by noise, while the saturation region represents a performance-limiting zone caused by the imperfect cancellation of the telemetry signal due to its non-constant envelope. Specifically, the two theoretical regions can be described with Equation (7), where $B_L{T}_C$ is the normalized equivalent noise bandwidth, $R_C$ is the chip rate, $R_S$ is the symbol rate, and $m_{RG}$ is the modulation index. Instead, the value of $L_{ck}$ is a correction factor that depends on the clock tone suppression ($L_{ck}=0.881$ for T4B and $L_{ck}=0.3936$ for T2B [9]), while ${\sigma }_{\zeta }^2$ represents a factor representing the saturation point, depending on modulation type and the SRRC roll-off factor (${\sigma }_{\zeta }^2=-13.9\mathrm{dB}$ for roll-off 0.25 for QPSK as in Figure 18, while ${\sigma }_{\zeta }^2=-6.48\mathrm{dB}$ for roll-off 0.25 for 64-APSK).

$$\left\{\begin{array}{cc}\hfill {\displaystyle \frac{1}{8}}{\displaystyle \frac{B_L}{L_{ck}\frac{E_s}{N_0}·R_s\left[2J_1^2\left(m_{RG}\right)\right]}},& forthelinearregion\hfill \\ \hfill {\sigma }_{\zeta }^2{\displaystyle \frac{B_L}{{2R}_c}},& forthesaturationregion\hfill \end{array}\right.$$

(7)

As shown, the observed performance closely follows the theoretical model in the linear region, while exhibiting an error of approximately 3 dB in the saturation zone. The system also shows improved performances with respect to the theoretical expectations in the low SNR region, but such a values are only related to an error in the SNR estimator. The latter estimator is in fact used by Equation (6) for the signal power normalization. As the SNR includes a small deviation up to +0.3 dB, especially in the low SNR region, the signal at the ranging input of the CTL results in a reduced amplitude (compared to the ideal circular amplitude with radius one). This implies a reduction in the equivalent loop bandwidth that is no more 1.5 kHz, dictating the lower jitter output.

Notably, these interaction effects were not considered in the previous theoretical studies that defined reference values. Despite this, the ranging jitter can be adjusted by tuning the loop filter coefficients, offering the potential to improve the accuracy of ranging distance measurements and compensate non-idealities. Additionally, further refinements could be made to reduce the offset/jitter introduced by other synchronization algorithms that directly impact ranging performance, such as the E_s/N₀ estimator used in telemetry. However, these improvements come at the cost of increased convergence time and extended lock-in ranges for such estimators. This trade-off must be carefully considered to balance performance and dynamic response.

Finally, tests were conducted to validate the system’s ability to maintain proper functionality even during ModCod changes in operation. The results demonstrated that the system successfully manages dynamic modulation and encoding adjustments, thereby supporting ACM/VCM techniques. Overall, the test results confirmed that the SCCC + PN-Ranging transmission scheme can be effectively implemented and operated in satellite environments, dynamically adapting in accordance with the ACM approach. While some limitations were identified, mitigation strategies have been established to ensure the robust implementation of the transmission scheme, even for high-order modulations and dynamic ModCod changes.

6. Conclusions

This work presents the design, development, and implementation of a breadboard system capable of simultaneously transmitting CCSDS 131.2-B [4] telemetry and CCSDS 414.1-B [8] ranging signals. Building upon a foundation of prior theoretical analysis and simulation studies [12,13], the project introduces implementation algorithms for key operations, including synchronization, signal reconstruction, and cross-cancellation, which are critical for the efficient functioning of telemetry and ranging system integration in dynamic satellite environments.

A particularly noteworthy aspect of this work is its novelty. To the best of the authors’ knowledge, there are no existing scientific studies that provide a direct comparison to the approach presented herein. While simulation-based studies and established standards in the field exist [12,13], none have successfully implemented and validated the combined SCCC + PN-Ranging transmission system in a hardware setup. This lack in the literature underscores the innovative nature of this research, which bridges the gap between theoretical models and practical, real-world applications. The successful integration of these complex subsystems in the very same system represents a significant advancement in satellite communication technologies, particularly in the context of modern, high-throughput satellite systems that require adaptive and efficient communication strategies.

Through the extensive evaluation of the system’s performance, several strengths and some limitations were identified. The proposed breadboard successfully demonstrates the feasibility of dynamically optimizing the link budget during satellite passes, while concurrently performing ranging operations. This dual functionality is crucial for future satellite missions that require efficient data transmission and precise ranging in real time. Despite certain limitations related to the performance of the ranging component under high-order modulation schemes, the implementation of targeted mitigation strategies has proven effective. These strategies, including adjustments for modulation indices, and improved algorithmic synchronization, help in minimizing the impact of such limitations, ensuring reliable system operation.

In conclusion, the successful validation of the SCCC + PN-Ranging transmission system in this study provides a clear path toward its integration into future satellite communication networks. This work not only advances current satellite communication systems, but also opens the door for further research and optimization to enhance system performance, particularly in dynamic and challenging operational environments. Future efforts will focus on refining the algorithms, reducing the implementation losses observed at higher modulation indices, extending the capabilities of the system to cope with more demanding operational conditions (e.g., implementing the usage of custom values for TM symbol rate and RG chip rate, and also emulating channel conditions that include Doppler shift, Doppler rate, and phase noise profiles). In particular, different rate values will be made configurable by enhancing the decimation, reconstruction, and estimation blocks within the receiver through runtime-adjustable settings. The configurability of these parameters is expected to have a significant impact, due to their distributed influence across multiple internal receiver components, especially for interpolators, delay-line structures, filtering chains, and equalization stages. Finally, to advance the system TRL, the implementation of the transmitter and receiver system designs will be ported to space-qualified hardware and ground station equipment, respectively.