A New CUK-Based Z-Source Inverter

Abstract

This paper proposes a new three-switch single-phase Z-source inverter (ZSI) based on a CUK converter, which is named a CUK-based ZSI. This topology has characteristics of buck‒boost capability and dual grounding. In addition, the voltage gain of proposed inverter is higher than those of the single-phase quasi-Z-source and semi-Z-source inverters. Aside from that, a simple control method is presented to achieve the linear voltage gain. The operational principle of the proposed topology is described. Finally, a performance evaluation is carried out and the test results verify the effectiveness of the proposed solution.

1. Introduction

In recent years, photovoltaic solar power has attracted more and more attention [1,2,3,4,5]. Because the output of the photovoltaic generation is DC, inverters are necessary for a photovoltaic generation system. However, the demerits of the conventional inverters are that their output AC voltage is lower than the input DC voltage. So, sometimes an additional DC‒DC converter is needed before the inverter [6,7], which will increase the volume of the inverter and reduce the reliability of the system.

At the same time, the leakage current is an important problem for transformerless inverters [8]. So, in some types of inverters, a high-frequency transformer is used in a two- or multi-stage configuration. A transformer can provide galvanic isolation, but, at the same time, the inverters’ efficiency is decreased because of additional losses caused by the transformer. Therefore, there is a trend toward developing transformerless inverters on purpose to reduce the cost and improve the system efficiency [9,10,11,12,13].

In order to solve the problem of conventional inverters, a lot of single-stage inverters with buck–boost capability were proposed in [14,15]. A new topology of the high-frequency alternating current (HFAC) inverter is presented in [16]. In [17], an AC-side voltage doubling converter is presented. Another interesting topology named UNI-AC (unified non-inverting and inverting AC–AC converter) is proposed in [18]. On the other hand, a Z-source inverter was first proposed in [19], which can achieve a boost function of input DC voltage by its X-shaped impedance network. More researchers have focused on the Z-source inverter because of its boost characteristic without an additional DC‒DC converter.

As the Z-source inverter was proposed, different types of Z-source inverters were developed [20,21], and [22] illustrates a new semi quasi-Z-source inverter. Compared with the traditional single-phase ZSI, the topologies have features of lower cost and dual grounding, and they can achieve the same output performance as the traditional full bridge voltage source inverter (VSI). However, these topologies suffer from high voltage stress and need a nonlinear control method, which limits their applications. In order to solve these problems, new three-switch three-state single-phase Z-source inverters are created [23], which can be divided into two kinds of topologies. One is called boost-based ZSI, and the other is called buck‒boost-based inverters. The topology named boost-based ZSI is derived from combining boost converter and semi quasi Z-source inverter, and the topology named buck‒boost-based ZSI is derived from combining buck‒boost converter with semi quasi-Z-source inverter. Both topologies have the advantages of fewer switches, low voltage stress, and large power density compared to traditional single-phase ZSIs. Moreover, these topologies have simple linear control and the characteristic of dual grounding, which can be used for reducing leakage current. However, buck‒boost-based type of TSTS-ZSIs cannot produce reactive power. As we know, Z-source inverters will have different characteristics based on different converters. The CUK converter has the advantages of the input supply current and the output load current both being continuous and the ripple being small, which is beneficial for filtering the input and output. Therefore, a new topology named CUK-based ZSI is presented. The following will present the analysis and performance evaluation.

2. Topologies Classification

2.1. CUK-Based ZSI

Figure 1 shows the proposed CUK-based ZSI. This topology is composed of a CUK converter and a semi Z-source inverter. In order to ensure that the boost function and the Z-source inversion work independently, only two switches can be turned on at the same time. Therefore, the gate signal in a switching period should be divided [23], and the control method is built in MATLAB as shown in Figure 2. In Figure 2, it is used to generate the gating signal, which ensures the proposed topology to achieve the sinusoidal voltage output, and the duty cycle of each switch is calculated by following equations.

The output voltage of the CUK-based TSTS Z-source inverter is defined as follows:

$${\mathrm{v}}_{\mathrm{o}}{=\mathrm{V}}_{\mathrm{o}}{\sin \mathsf{\omega }\mathrm{t}=\mathrm{AV}}_{\mathrm{in}}\sin \mathsf{\omega }\mathrm{t}$$

(1)

where ${\mathrm{V}}_{\mathrm{in}}$ is the input voltage, A or the peak voltage gain is defined as ${\mathrm{A}=\mathrm{V}}_{\mathrm{o}}{/\mathrm{V}}_{\mathrm{in}}$, and the maximum output voltage is ${\mathrm{V}}_{\mathrm{o}}$.

Boost part, to set ${\mathrm{D}}_1$ (Duty cycle of S1) as a constant value and k is the maximum boost ratio is defined as follows [23]:

$$\mathrm{k}=\frac{{\mathrm{D}}_1}{{1-\mathrm{D}}_1}\Rightarrow {\mathrm{D}}_1=\frac{\mathrm{k}}{1+\mathrm{k}}$$

(2)

In the inversion part, the sinusoidal output voltage ${\mathrm{v}}_{\mathrm{o}}$ is generated by ${\mathrm{D}}_2$ (duty cycle of S2) as a varied sinusoidal value. ${\mathrm{D}}_3$ (duty cycle of S3) can be obtained from Figure 3. They are defined as follows [23]:

$${\mathrm{D}}_2=\frac{\mathrm{k}+2}{2(\mathrm{k}+1)}-\frac{\mathrm{A}}{2(\mathrm{k}+1)}\sin \mathsf{\omega }\mathrm{t}$$

(3)

$${\mathrm{D}}_3=2-{\mathrm{D}}_1-{\mathrm{D}}_2.$$

(4)

So, according to the above circuit and the switching period, the circuit in Figure 1 can be divided into three states in one switching period, whose equivalent circuits are shown in Figure 3a–c.

2.2. Mode Analysis of Proposed CUK-Based ZSI

Figure 3a–c show the operation modes of proposed CUK-based ZSI. The detailed operational principle is as follows:

• First mode: In this mode, switches S1 and S3 are turned on, whereas switch S2 is turned off, as depicted in Figure 3a. The inductor Lf is magnetized by input voltage ${\mathrm{V}}_{\mathrm{in}}$, and capacitors C1, C2 and C0 are charged; C3 is discharged. The equations of this mode can be expressed as:

  $$\{\begin{array}{l}{\mathrm{V}}_{\mathrm{C}2}+{\mathrm{V}}_{\mathrm{C}3}=-{\mathrm{V}}_{\mathrm{L}2}\\ -{\mathrm{V}}_{\mathrm{C}0}+{\mathrm{V}}_{\mathrm{C}1}={\mathrm{V}}_{\mathrm{L}1}+{\mathrm{V}}_{\mathrm{L}3}\\ {\mathrm{V}}_{\mathrm{in}}={\mathrm{V}}_{\mathrm{Lf}}\end{array}$$

  (5)

  $$\{\begin{array}{l}{\mathrm{i}}_{\mathrm{C}2}={\mathrm{i}}_{\mathrm{C}3}={\mathrm{i}}_{\mathrm{L}2}\\ {\mathrm{i}}_{\mathrm{C}1}=-{\mathrm{i}}_{\mathrm{L}1}=-{\mathrm{i}}_{\mathrm{L}3}\end{array},$$

  (6)

  where ${\mathrm{V}}_{\mathrm{C}0}$, ${\mathrm{V}}_{\mathrm{C}1}$, ${\mathrm{V}}_{\mathrm{C}2}$ and ${\mathrm{V}}_{\mathrm{C}3}$ are the voltage of capacitors C0, C1, C2 and C3. ${\mathrm{V}}_{\mathrm{L}1}$ and ${\mathrm{V}}_{\mathrm{L}2}$ and ${\mathrm{V}}_{\mathrm{L}3}$ are the voltage of inductors L1, L2 and L3, and ${\mathrm{V}}_{\mathrm{Lf}}$ is the voltage of input inductor Lf. Similarly, ${\mathrm{i}}_{\mathrm{C}1}$, ${\mathrm{i}}_{\mathrm{C}2}$ and ${\mathrm{i}}_{\mathrm{C}3}$ are the current of capacitors C1, C2 and C3, and ${\mathrm{i}}_{\mathrm{L}1}$, ${\mathrm{i}}_{\mathrm{L}2}$ and ${\mathrm{i}}_{\mathrm{L}3}$ are the current of inductors L1, L2 and L3.
• Second mode: In this mode, switches S1 and S2 are turned on, whereas switch S3 is turned off, as depicted in Figure 3b. The inductor Lf is magnetized by input voltage ${\mathrm{V}}_{\mathrm{in}}$, and capacitors C1, C2 and C0 are discharged; C3 is charged. The equations of this mode can be expressed as:

  $$\{\begin{array}{l}{\mathrm{V}}_{\mathrm{C}2}={\mathrm{V}}_{\mathrm{L}1}\\ {\mathrm{V}}_{\mathrm{C}1}={\mathrm{V}}_{\mathrm{L}2}\\ -{\mathrm{V}}_{\mathrm{C}3}-{\mathrm{V}}_{\mathrm{C}0}={\mathrm{V}}_{\mathrm{L}3}\\ {\mathrm{V}}_{\mathrm{in}}={\mathrm{V}}_{\mathrm{Lf}}\end{array}$$

  (7)

  $$\{\begin{array}{l}{\mathrm{i}}_{\mathrm{C}3}={\mathrm{i}}_{\mathrm{L}3}\\ {\mathrm{i}}_{\mathrm{C}2}=-{\mathrm{i}}_{\mathrm{L}1}\\ {\mathrm{i}}_{\mathrm{C}1}=-{\mathrm{i}}_{\mathrm{L}2}\end{array}.$$

  (8)
• Third mode: In this mode, switches S2 and S3 are turned on, whereas switch S1 is turned off, as depicted in Figure 3c. The capacitors C1, C2 and C0 are charged; C3 is discharged.

  $$\{\begin{array}{l}{\mathrm{V}}_{\mathrm{in}}-({\mathrm{V}}_{\mathrm{C}3}+{\mathrm{V}}_{\mathrm{C}2}+{\mathrm{V}}_{\mathrm{C}1})={\mathrm{V}}_{\mathrm{Lf}}\\ -{\mathrm{V}}_{\mathrm{C}2}={\mathrm{V}}_{\mathrm{L}1}\\ -{\mathrm{V}}_{\mathrm{C}1}={\mathrm{V}}_{\mathrm{L}2}\\ {\mathrm{V}}_{\mathrm{C}2}+{\mathrm{V}}_{\mathrm{C}1}-{\mathrm{V}}_{\mathrm{C}0}={\mathrm{V}}_{\mathrm{L}3}\end{array}$$

  (9)

  $$\{\begin{array}{l}{\mathrm{i}}_{\mathrm{C}1}=-{\mathrm{i}}_{\mathrm{L}1}=-{\mathrm{i}}_{\mathrm{L}3}=-{\mathrm{i}}_{\mathrm{L}2}\\ {\mathrm{i}}_{\mathrm{C}2}=-{\mathrm{i}}_{\mathrm{L}1}\\ {\mathrm{i}}_{\mathrm{C}3}={\mathrm{i}}_{\mathrm{Lf}}\end{array},$$

  (10)

  where ${\mathrm{i}}_{\mathrm{Lf}}$ is the current of inductor Lf.

2.3. Control of Proposed CUK-Based ZSI

The control block diagrams of the proposed inverters are shown in Figure 4a–c. According to Figure 4a, we input a constant value K, then compare with the carrier signal to produce the switch signal of S1, which is used to boost the voltage. According to Figure 4b, it is different from (a), because it inputs a sinusoidal value, and then, compared with a carrier signal, after reversing, the switch signal of S2 is obtained, which is used to generate output sinusoidal voltage. At the same time, the switch signal of S3 is decided by the switch signal of S1 and the switch signal of S2, and the switch signal of S1 and the switch signal of S2 pass through the XOR gate to get the switch signal of S3, as shown in Figure 4c, where the XOR gate is a digital logic gate that gives a true (1 or HIGH) output when the number of true inputs is odd.

XOR is a logic manipiulator.

3. Device Stress Calculation and Passive Component Design

3.1. Device Stress Calculation

Based on Figure 3 and Equations (5)–(10), the current of switches S1, S2 and S3 and the voltage of switches S1, S2 and S3 can be determined. Consequently, the following rate equations express the voltage and the current stresses of switches S1, S2 and S3.

$${\mathrm{V}}_{\text{S-max}}{=(1+\mathrm{k})\mathrm{V}}_{\mathrm{in}}$$

(11)

$${\mathrm{I}}_{\text{S-max}}{=(\mathrm{A}+1)\mathrm{I}}_{\mathrm{o}},$$

(12)

where ${\mathrm{I}}_{\mathrm{o}}$ is the output current. ${\mathrm{V}}_{\text{S-max}}$ and ${\mathrm{I}}_{\text{S-max}}$ are the maximum voltage stresses and current stresses, respectively. The output current is considered to be a sinusoidal waveform. ${\mathrm{V}}_{\mathrm{o}}$ is expressed in (1) and ${\mathrm{I}}_{\mathrm{o}}$ similarly can be written as:

$${\mathrm{I}}_{\mathrm{o}}={\mathrm{I}}_{\mathrm{M}}\sin \mathsf{\omega }\mathrm{t}$$

(13)

where ${\mathrm{I}}_{\mathrm{M}}$ denotes the output peak current.

3.2. Passive Component Design

Supposing that inductor L1 and inductor L2 are equal, and capacitor C1 and capacitor C2 are equal, according to the volt-second balance principle, it is easy to get the following equations:

$$\{\begin{array}{l}{\mathrm{V}}_{\mathrm{C}1}={\mathrm{V}}_{\mathrm{C}2}=\frac{{1-\mathrm{D}}_2}{{\mathrm{D}}_2}{\mathrm{V}}_{\mathrm{in}}\\ {\mathrm{V}}_{\mathrm{C}3}=\frac{1}{{1-\mathrm{D}}_1}{\mathrm{V}}_{\mathrm{in}}\end{array}$$

(14)

$$\{\begin{array}{l}{\mathrm{i}}_{\mathrm{L}1}={\mathrm{i}}_{\mathrm{L}2}=\frac{{1-\mathrm{D}}_2}{{\mathrm{D}}_2}{\mathrm{I}}_{\mathrm{o}}\\ {\mathrm{i}}_{\mathrm{L}3}={\mathrm{I}}_{\mathrm{o}}\\ {\mathrm{i}}_{\mathrm{Lf}}=\frac{{-\mathrm{D}}_1}{{1-\mathrm{D}}_1}{\mathrm{I}}_{\mathrm{o}}\end{array}$$

(15)

The inductor L and input inductor Lf, capacitors C and output capacitor can be calculated by the following equations. In order to calculate the current ripple of inductor Lf, the equation in the first mode is considered. Using this equation and knowing that ${\mathrm{V}}_{\mathrm{L}}{=\mathrm{L}(\mathrm{di}}_{\mathrm{L}}{/\mathrm{d}}_{\mathrm{t}})$, the current ripple of inductor Lf can be extracted as:

$${\mathsf{\Delta }\mathrm{i}}_{{\mathrm{L}}_{\mathrm{f}}}=\frac{{\mathrm{V}}_{\mathrm{in}}{\mathrm{DT}}_{\mathrm{s}}}{\mathrm{Lf}}$$

(16)

where ${\mathsf{\Delta }\mathrm{i}}_{{\mathrm{L}}_{\mathrm{f}}}$ is the current ripple of inductor Lf and ${\mathrm{T}}_{\mathrm{s}}$ denotes the switching period.

Therefore, the inductor Lf can be calculated by the following equation:

$$\mathrm{Lf}=\frac{{\mathrm{V}}_{\mathrm{in}}{\mathrm{D}}_1{\mathrm{T}}_{\mathrm{s}}}{{\mathsf{\Delta }\mathrm{i}}_{\mathrm{Lf}}}.$$

(17)

So, the current ripple of inductors L can be expressed by the same method, and the inductors L can be calculated by the following equations:

$$\mathrm{L}1=\mathrm{L}2=\frac{{\mathrm{V}}_{\mathrm{in}}{(1-\mathrm{D}}_2{)\mathrm{T}}_{\mathrm{s}}}{{\mathsf{\Delta }\mathrm{i}}_{\mathrm{L}1}}$$

(18)

$$\mathrm{L}3=\frac{{(\mathrm{V}}_{\mathrm{C}0}{\mathrm{V}}_{\mathrm{C}3}{)\mathrm{D}}_1{\mathrm{T}}_{\mathrm{s}}}{{\mathsf{\Delta }\mathrm{i}}_{\mathrm{L}3}}=\frac{{\mathrm{V}}_{\mathrm{in}}{\mathrm{T}}_{\mathrm{s}}}{{\mathsf{\Delta }\mathrm{i}}_{\mathrm{L}3}},$$

(19)

where ${\mathsf{\Delta }\mathrm{i}}_{\mathrm{L}1}$ and ${\mathsf{\Delta }\mathrm{i}}_{\mathrm{L}3}$ are the current ripple of inductor L1 and L3, respectively.

Similarly, by employing the equations in the first mode and knowing that ${\mathrm{i}}_{\mathrm{c}}{=\mathrm{C}(\mathrm{dV}}_{\mathrm{c}}{/\mathrm{d}}_{\mathrm{t}})$, the capacitors can be calculated by the following equations:

$$\mathrm{C}1=\mathrm{C}2=\frac{{\mathrm{i}}_{\mathrm{L}1}{\mathrm{D}}_2{\mathrm{T}}_{\mathrm{s}}}{{\mathsf{\Delta }\mathrm{V}}_{\mathrm{C}2}}$$

(20)

$$\mathrm{C}3=\frac{{\mathrm{i}}_{\mathrm{L}3}{\mathrm{D}}_1{\mathrm{T}}_{\mathrm{s}}}{{\mathsf{\Delta }\mathrm{V}}_{\mathrm{C}3}}$$

(21)

$$\mathrm{C}0=\frac{{\mathsf{\Delta }\mathrm{i}}_{\mathrm{L}3}{\mathrm{T}}_{\mathrm{s}}}{{2\mathsf{\Delta }\mathrm{V}}_{\mathrm{C}0}},$$

(22)

where ${\mathsf{\Delta }\mathrm{V}}_{\mathrm{C}0}$, ${\mathsf{\Delta }\mathrm{V}}_{\mathrm{C}2}$ and ${\mathsf{\Delta }\mathrm{V}}_{\mathrm{C}3}$ are the voltage ripple of capacitors C0, C2 and C3, respectively.

4. Simulation and Comparison

4.1. Simulation Conditions and Results

In order to test the performances of the proposed CUK-based ZSI, a series of simulations have been done in Matlab/Simulink® 2015a. The simulation condition and parameters are shown in

Table 1. Simulation parameters for current topology.

Parameters	Proposed Topologies
Input voltage, Vin	90 V
Output voltage (rms), Vo	110 V
Switching frequency, fs	20 kHz
Output voltage gain, A	1.75
Maximum boost ratio, k	2
Inductance Lf	0.48 mH
Z-impedance inductance, L1 and L2	1 mH
Z-impedance capacitance, C1 and C2	46.3 $\mathsf{\mu }\mathrm{F}$
Capacitance C3	27.4 $\mathsf{\mu }\mathrm{F}$
Inductance L3	1.45 mH
Output capacitance, C0	10 $\mathsf{\mu }\mathrm{F}$

. The designs use an input voltage of 90 V for generating the output voltage at 110 V and 50 Hz. The switching frequency is considered to be 20 kHz. In the design procedure, the inductors are calculated using Equations (17)–(19) and supposing $\Delta {\mathrm{i}}_{\mathrm{L}}=20\%{\mathrm{I}}_{\mathrm{L}}$ for all inductors. Similarly, the capacitors are designed according to Equations (20)–(22) with ${\mathsf{\Delta }\mathrm{V}}_{\mathrm{C}}{=7\%\mathrm{V}}_{\mathrm{C}}$, where ${\mathsf{\Delta }\mathrm{V}}_{\mathrm{C}}$ are the voltage ripple of capacitors. What is more, IGBT is selected for each switch.

Using the parameters from Table 1, the simulations have been done. In order to test the reliability of the proposed topologies, simulations for proposed CUK-based ZSI are carried out. Firstly, the input voltage is set 90 V and load is 10 Ω. Figure 5a–c illustrate the load voltage, load voltage and FFT analysis, respectively. Figure 6a–c shows the voltage waveforms of the switches S1, S2 and S3. At the same time, the voltage waveform of the capacitors C1, C2, C3, and the output capacitor C0 are shown in Figure 7a–d. Lastly, the simulation of input voltage changes suddenly during the simulation is carried out, and the output results are shown in Figure 8a,b.

From the above simulation results, it can be observed when the input voltage is 90 V and load is 10 Ω, the output voltage and current satisfy the requirements, and the THD = 2.71%, which is well below 5%. On the other hand, the voltage stresses of switches are about 300 V. According to Figure 8, when the input voltage changes suddenly, although the waveform fluctuates in the course of the change, it tends to stabilize quickly. In summary, the proposed inverter can operate under different conditions with good performance.

4.2. Comparison

Table 2. Comparative summary of the proposed inverter with other Z-source inverters.

Z-Source Inverter Topologies	Total no. Component			Complexness	Power Density	Cost	Voltage Gain	Switches’ Voltage Stress	THD %
	S	L	C
Semi-ZS-Based in [24]	2	3	3	simple	high	low	<1	/	/
Semi-ZSI in [22]	2	2	3	simple	high	low	<1	$(1+\frac{2}{\mathrm{A}}{)\mathrm{V}}_{\mathrm{o}}$	/
Boost-based TSTS-ZSI in [23]	3	3	3	simple	high	low	>1	$(1+\frac{2}{\mathrm{A}}{)\mathrm{V}}_{\mathrm{o}}$	2.82
Buck‒boost-based TSTS-ZSI in [23]	3	3	4	simple	High	low	>1	$(1+\frac{1}{\mathrm{A}}{)\mathrm{V}}_{\mathrm{o}}$	3.15
Proposed	3	4	4	simple	High	low	>1	$(1+\frac{1}{\mathrm{A}}{)\mathrm{V}}_{\mathrm{o}}$	2.71

shows the comparison among the proposed inverter and Semi-ZS-Based [24], Semi-ZSI [22], boost-based TSTS-ZSI [23] and buck‒boost-based TSTS-ZSI [23]. These topologies are all based on Z-source inverters, and an extra boost stage is not needed anymore. On the other hand, they all have the characteristics of the common input and output terminals, which means these topologies can eliminate the leakage current for PV systems. Meanwhile, the voltage gain of the proposed topology is more than 1. The major feature compared with boost-based TSTS-ZSI and buck‒boost-based TSTS-ZSI is that the proposed topology is based on a CUK converter. So it has the same advantages as a CUK converter.

In Table 2, the THD is valid under the condition of input 90 V and full load. What is more, all of them have a simple topology; although the proposed inverter has one more inductor than buck‒boost-based TSTS-ZSI, it still has good performance. So all of these inverters have high power density and low cost.

5. Experimental Verification

In order to further verify the effectiveness of the proposed inverter, the corresponding experiment is carried out. Input 90 V voltage and work under 30 Ω resistive load for the proposed inverter. According to Equations (11) and (12), the K40T1202 IGBT is used for each switch in the experiment.

Firstly, the proposed inverter is tested under 90V input voltage. Figure 9 shows the output voltage and current waveforms, which are in agreement with Figure 5. The voltage waveforms of S1, S2, and S3 are depicted in Figure 10a–c, which are in agreement with the simulation results in Figure 6. The capacitor voltages are shown in Figure 11a,b, and these waveforms match with Figure 7.

Another experiment is carried out when the load changes suddenly during the experiment. The output voltage and current are displayed in Figure 12.

It can be seen from Figure 12 that the proposed inverter still works well when the load changes suddenly. In conclusion, from the above experimental results, it can be observed that they are in good agreement with the theoretical analysis and the simulation results, which again confirms the effectiveness of the proposed inverter.

6. Conclusions

The main contribution of this paper is to present a new ZSI topology, named CUK-based ZSI. Compared with traditional ZSI, this topology has fewer switches but can achieve high voltage gain. Moreover, this topology has the feature of a common input‒output terminal, which is helpful for reducing leakage current. According to the concrete results from simulations and experiments, the proposed inverter works well. Figure 5 and Figure 9 indicate that the proposed topology has a high voltage gain and a low THD, which is beneficial for many applications such as PV systems. However, the proposed inverter topology also has some drawbacks. Because the proposed topology has more inductors and capacitors than conventional single-phase Z-source inverters, there will be more system losses. Future research should focus on using the coupled-inductor technique and SiC devices to optimize the power density.