A Piecewise Control Strategy for a Bidirectional Series Resonant Converter

Abstract

An energy storage system (ESS) plays an important part in a renewable energy generation system for stable and efficient power harvesting. To realize the function of an ESS, a bidirectional DC/DC converter with high power density and high efficiency is highly desired. In this paper, a high-frequency (HF) isolated dual-bridge series resonant converter (DBSRC) with a piecewise control strategy is proposed for an application with a wide variation of voltage gain. The proposed control strategy is based on dual-phase-shift modulation for a balance between complexity and flexibility. With this proposed control strategy, zero-voltage switching is kept for all switches on the low-voltage side and half of switches on the high-voltage side. Besides, there is no circulation energy on the low-voltage high-current side for full load operation. A step-by-step design procedure is also included to calculate the converter components and control parameters. Verification of the analysis and design are performed successfully through simulation and n experimental test. Comparisons with some existing control methods are also made experimentally, which highlights that the proposed control strategy is able to achieve comparable performance as the reported optimal current control with simpler calculation and implementation.

1. Introduction

To deal with the greenhouse effect due to fossil fuel use and the potential energy crisis in the future, renewable energy generation techniques have drawn much attention from not only industrial/academic researchers, but policy-makers from governments around the world [1,2,3,4,5,6,7,8]. In Figure 1, a DC-linked hybrid renewable energy generation system is shown [9,10,11]. To accommodate the fluctuating nature of renewable energies, an energy storage system (ESS) including a bidirectional DC/DC converter and energy storage units (rechargeable battery stacks or super-capacitors) becomes an essential part of the hybrid system. The ESS will absorb excess power when the total amount of available renewable energy is high and the power demand is low. If the total amount of available renewable energy is low and the power demand is high, the energy storage units could release power to keep the DC bus voltage stable. While the DC bus has a relatively stable and high voltage, the energy storage units normally have a lower voltage with a large variation. For example, a typical single LiFePO${}_4$ battery cell with a rated voltage at 3.2 V has a voltage range of 2.5–3.65 V. The voltage range of a Maxwell 48 V super-capacitor module is between 28 V and 45 V.

In the literature, both the dual-active-bridge converter (DAB) and dual-bridge series resonant converter (DBSRC) are discussed extensively for high power density high efficiency applications [10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32]. If single-phase-shift control (SPS) is applied, both DAB and DBSRC suffer from a limited zero-voltage switching (ZVS) range with the variation of non-unity converter gain and high circulation current. At the cost of more control parameters, different advanced modulations have been proposed for those two dual-bridge converters in order to extend ZVS range [11,12,13], eliminate circulation current [19], and minimize conduction loss [22,23,24,33]. A minimum current control was proposed in [24] based on triple-phase-shift (TPS) control to realize the minimum current trajectory (MCT). The MCT strategy is complicated since a total of three controllable phase-shift angles is used. Furthermore, no information about a customized design procedure is given for a specified application. In this paper, two phase-shift angles will be used to control a DBSRC for a balance of complexity and flexibility. The steady-state performance of the DBSRC with dual-phase-shift angles (DPS) is evaluated first in Section 2. In Section 3, a piecewise dual-phase-shift control strategy (PW-DPS) is presented for the DBSRC to deal with variable low-voltage side voltage and variable load levels. Verification of the control strategy with simulation and experimental results is included in Section 4. The main features of the proposed PW-DPS control can be concluded as: no circulation energy on the low-voltage side at full load for any voltage gain, ZVS operation of six switches, and high efficiency at partial load. A comparative study with the DBSRC under SPS control and MCT control is also presented. The proposed PW-DPS strategy is proven to be more advantageous over the SPS control in terms of efficiency and soft-switching operation. Besides, the proposed PW-DPS strategy shows quite similar competitive performance compared with the MCT control, which tends to achieve an overall minimized rms current operation through complicated optimization calculation of three phase-shifts.

2. Steady-State Analysis for DBSRC with DPS Control

As shown in Figure 2, a dual-bridge series resonant converter consists of two full-bridges, which are linked by a series LC-type resonant tank and a high-frequency (HF) isolation transformer. The two voltage sources $V_H$ and $V_L$ are high-voltage (HV) side voltage and low-voltage (LV) side voltage, respectively. $S_1$∼$S_4$ and $Q_1$∼$Q_4$ are eight MOSFET switches with body diodes. $C_H$ and $C_L$ are filter capacitors on the HV side and LV side, respectively.

In Figure 3, steady-state waveforms of the DBSRC with DPS modulation for two directional power transfers are presented. The power transfer from the HV side to the LV side is defined as a positive power. All switches in each bridge arm are operating alternatively at almost 50% duty cycle with necessary deadband. The bidirectional power is a function of two phase-shift angles. The inner-bridge angle ${\alpha }_1$ is defined as the phase-shift by which the gating signal of $S_4$ leads to that of $S_1$, which is in the range of [0, $\pi$]. The inter-bridge angle ${\alpha }_2$ is defined as the phase-shift by which the gating signal of $S_1$ leads to that of $Q_1$. The range of ${\alpha }_2$ depends on the polarity of power and the value of ${\alpha }_1$. Consequently, the HF AC voltage on the HV side $v_{AB}$ is a quasi-square wave voltage with a variable pulse width ($\pi -\frac{{\alpha }_1}{2}$), while the LV side HF AC voltage $v_{XY}$ is a square wave voltage. The angle by which the fundamental component of $v_{AB}$ leads to the fundamental component of $v_{XY}$ is defined as $\varphi$, which is always equal to (${\alpha }_1/2+{\alpha }_2$) regardless of power transfer direction. $\beta$ is the angle by which the fundamental component of $v_{AB}$ leads to the fundamental component of resonant current $i_s$.

In this work, the fundamental harmonics approximation (FHA) approach is utilized for the steady-state analysis as the converter is designed to work nearly at the resonance state. The obtained results can be used for a quick initial design. In this paper, the LV side voltage $V_L$ is assumed in the range of $\left[V_{Lmin}{V}_{Lmax}\right]$ and the HV side voltage $V_H$ is fixed. For the purpose of simplicity, all quantities refer to the HV side (marked by a superscript “${}^{\prime }$” if the quantity is on the LV side actually) and normalized by the following base values:

$$V_B=V_H,Z_B=\frac{n_t^2{V}_{Lmax}^2}{P_F},I_B=\frac{V_B}{Z_B},f_B=\frac{1}{2\pi \sqrt{L_s{C}_s}}$$

(1)

where $f_B$ is the resonance frequency, $P_F$ is the rated full-load power, and $n_t$ is the HV-to-LV turn ratio of the HF transformer.

The voltage gain of the bidirectional converter is defined as:

$$M=\frac{n_t{V}_L}{V_H}$$

(2)

All normalized reactance can be expressed as:

$$\begin{array}{c}\hfill X_{Ls,pu}=QF;X_{Cs,pu}=-Q/F;\\ \hfill X_{s,pu}=X_{Ls,pu}+X_{Cs,pu}=Q(F-1/F)\end{array}$$

(3)

where the quality factor Q is defined as $Q=\frac{2\pi f_B{L}_s}{Z_B}=\frac{1}{2\pi f_B{C}_s{Z}_B}$, normalized switching frequency F is $F=f_s/f_B$, and $f_s$ is the switching frequency.

The equivalent circuit of a DBSRC in steady-state is given in Figure 4. According to the waveforms of $v_{AB}$ and $v_{XY}$ shown in Figure 3, the normalized fundamental components of the two voltage sources can be calculated as:

$$\begin{array}{c}{v}_{AB,1pu}({\omega }_{s}t)=\frac{4}{\pi }cos(\frac{{\alpha }_1}{2})sin({\omega }_{s}t)\hfill \end{array}$$

(4)

$$\begin{array}{c}{v}_{XY,1pu}^{\prime }({\omega }_{s}t)=\frac{4M}{\pi }sin({\omega }_{s}t-\varphi )\hfill \end{array}$$

(5)

By using the principle of superposition, the normalized fundamental resonant current $i_{\mathrm{s},\mathrm{pu}}$ can be found easily as:

$$i_{s,pu}({\omega }_{s}t)=\frac{4[Mcos({\omega }_{s}t-\varphi )-cos(\frac{{\alpha }_1}{2})cos{\omega }_{s}t]}{\pi X_{s,pu}}$$

(6)

The normalized peak current $I_{sp,pu}$ is given as:

$$I_{sp,pu}=\frac{4\sqrt{M^2-2M_{L}cos(\varphi )cos\frac{{\alpha }_1}{2}+{cos}^2\frac{{\alpha }_1}{2}}}{\pi X_{s,pu}}$$

(7)

The necessary conditions of ZVS operation for all switches require that the anti-parallel diodes be turned on prior to the switch channel. These conditions could be checked by evaluating the resonant current at three special time points, which are the turn-on moment of $S_1$, the turn-on moment of $S_3$, and the turn-on moment of $Q_1,Q_4$, respectively. The three instantaneous values of resonant current should satisfy the following inequality:

$$\begin{array}{c}\hfill i_{s,pu}(\frac{{\alpha }_1}{2})=\frac{4[Mcos{\alpha }_2-{cos}^2(\frac{{\alpha }_1}{2})]}{\pi X_{s,pu}}<0\end{array}$$

(8)

$$\begin{array}{c}\hfill i_{s,pu}(\pi -\frac{{\alpha }_1}{2})=\frac{4[{cos}^2(\frac{{\alpha }_1}{2})-Mcos({\alpha }_1+{\alpha }_2)]}{\pi X_{s,pu}}>0\end{array}$$

(9)

$$\begin{array}{c}\hfill i_{s,pu}(\frac{{\alpha }_1}{2}+{\alpha }_2)=\frac{4(M-cos\frac{{\alpha }_1}{2}cos\varphi )}{\pi X_{s,pu}}<0\end{array}$$

(10)

After simplification, the following results are obtained.

$$\begin{array}{c}\hfill Mcos{\alpha }_2<{cos}^2\frac{{\alpha }_1}{2}\end{array}$$

(11)

$$\begin{array}{c}\hfill Mcos({\alpha }_1+{\alpha }_2)<{cos}^2\frac{{\alpha }_1}{2}\end{array}$$

(12)

$$\begin{array}{c}\hfill M>cos\frac{{\alpha }_1}{2}cos\varphi \end{array}$$

(13)

The three inequality expressions are necessary ZVS conditions for $S_1,S_2$, ($S_3,S_4$), and ($Q_1$∼$Q_4$), respectively. The statements above are valid for both positive and negative power.

According to the discussion above, the relationship between the soft-switching conditions and the voltage gain of the converter are illustrated in Figure 5a–c. In each figure, the two straight solid lines indicate the boundary of ${\alpha }_2$. The ZCSoperation region is enclosed by the curves, whose area depends on the voltage gain.

The average power transferred between the two DC sources can be evaluated as:

$$P_{o,pu}=\frac{8M}{{\pi }^{2}Q(F-\frac{1}{F})}cos\frac{{\alpha }_1}{2}sin(\frac{{\alpha }_1}{2}+{\alpha }_2)$$

(14)

Apparently, the polarity of transferred average power relies on the polarity of $sin(\frac{{\alpha }_1}{2}+{\alpha }_2)$. Therefore, if the power is positive, ${\alpha }_2$ is in the range of $[-\frac{{\alpha }_1}{2},\pi -\frac{{\alpha }_1}{2}]$. If the power is negative, ${\alpha }_2$ is in the range of $[-\pi -\frac{{\alpha }_1}{2},-\frac{{\alpha }_1}{2}]$. The normalized power can also be expressed as:

$$P_{o,pu}=\frac{P}{V_B^2/Z_{\mathrm{B}}}=\frac{P}{P_F}{(\frac{n_t{V}_{Lmax}}{V_B})}^2=G{M}_{max}^2$$

(15)

where $G=\frac{P}{P_F}\in [01]$ is the percentage of the power level and $M_{max}=\frac{n_t{V}_{Lmax}}{V_H}$ is the maximum voltage gain. Substituting (15) into (14) yields:

$$\frac{M_{max}^2}{M}=\frac{8}{{\pi }^{2}GQ(F-\frac{1}{F})}cos\frac{{\alpha }_1}{2}\left|sin(\frac{{\alpha }_1}{2}+{\alpha }_2)\right|$$

(16)

This equation above describes the relationship among the power level (G) and the varying voltage gain M in a DBSRC under DPS modulation. If either or both of the two quantities ($G,M$) changes, the two phase-shift angles shall be adjusted appropriately to keep the balance in (16).

3. The Proposed Piecewise Control Strategy

3.1. Design Approach

According to (14) and (16), there are infinite combinations of ${\alpha }_1$ and ${\alpha }_2$ that are able to achieve a particular voltage gain at a particular power, in theory. In this work, the top priority for selecting a suitable control strategy is to reduce circulation energy and, meanwhile, to maintain a wide ZVS operation range with the variation of both the load and the converter gain. Inspired by the fact that a unity converter gain M is the optimal situation for ZVS operation when SPS control is adopted, a piecewise control strategy based on DPS is proposed.

At first, the principles of the piecewise control strategy can be summarized as:

• The high circulation current would induce high rms current and hence result in high conduction loss, especially on low-voltage high-current side at heavy load. Therefore, the LV-side voltage and current are manipulated to be in phase (i.e., zero circulation energy) at full load regardless of the converter gain and the polarity of power. At this moment, the power factor on the LV side is unity, and the power factor on the HV side has the minimum value.
• Phase I, heavy load: At a reduced load level, the pulse-width of the HV-side HF AC voltage ($v_{AB}$) is reduced until the length of effective HV-side AC voltage vector ${\mathbf{V}}_{\mathbf{AB}}$ has the same length as that of the LV-side HF AC voltage vector ${\mathbf{V}}_{\mathbf{XY}}^{\prime }$. In Phase I, the power factor on the LV side decreases and the power factor on the HV side increases.
• Phase II, light load: To achieve even a low load level, the angle between two isometric voltage vectors (${\mathbf{V}}_{\mathbf{AB}}$ and ${\mathbf{V}}_{\mathbf{XY}}^{\prime }$) is reduced, which is actually analogous to the unity gain operation of DAB or DBSRC with SPS control. In Phase II, the power factor on both sides increases.

Based on the principle, the converter operation under the piecewise control strategy will be explained in detail for the case of positive power transfer. To make the explanation understandable, the phasor diagrams to illustrate key operation conditions for positive power are presented in Figure 6.

3.2. Full Load Operation

3.2.1. Full Load Operation at $M=M_{max}$

This special operation situation is used for the converter design with maximum power $P_F$ and the maximum voltage gain $M_{max}$ (i.e., $V_L=V_{Lmax}$). At the design point shown in Figure 6a1, ${\alpha }_1$ is equal to zero to let $v_{AB}$ have a maximum pulse width to make full use of the input. ${\alpha }_2$ is chosen so that the resonant current vector ${\mathbf{I}}_{\mathbf{s}}$ is in phase with the phasor ${\mathbf{V}}_{\mathbf{XY}}^{\prime }$, which means zero circulation current on the LV side. The two phase-shift angles at the design point are:

$$\left\{\begin{array}{c}{\alpha }_1=0\hfill \\ {\alpha }_2=arccos(M_{max})={\varphi }_o\hfill \end{array}\right.$$

(17)

where ${\varphi }_o$ is the inter-bridge phase-shift at the design point.

With above resonance operation ($F>1$), there is a certain amount of circulation current existing on the HV side at the design point. On the one hand, a small amount of circulation current is helpful to realize ZVS operation for the HV side bridge. On the other hand, a large amount of circulation current will increase rms current and bring up more conduction loss. Fortunately, the induced conduction loss is low since the current on the HV-side is relatively low. Furthermore, the loss can be reduced by a proper selection of $M_{max}$.

3.2.2. Full Load Operation at $M<M_{max}$

At full load operation with $M<M_{max}$, a similar right-angle phasor triangle could be constructed to make the resonant current ${\mathbf{I}}_{\mathbf{s}}$ be in phase with ${\mathbf{V}}_{\mathbf{XY}}^{\prime }$. Both ${\alpha }_1$ and $({\alpha }_1/2+{\alpha }_2)$ have to be adjusted properly compared with the case at the design point. With a lower $V_{\mathrm{L}}$, the load current is higher than before at full load, i.e., the length of ${\mathbf{V}}_{\mathbf{XY}}^{\prime }$ is shorter and the length of ${\mathbf{I}}_{\mathbf{s}}$ (which is proportional to ${\mathbf{V}}_{\mathbf{AB}}-{\mathbf{V}}_{\mathbf{XY}}^{\prime }$) is longer compared with the case in Figure 6a1. At the full load condition with $M<M_{\max }$ (Figure 6b1), the two phase-shift angles can be solved geometrically:

$$\left\{\begin{array}{c}{\varphi }_o^{*}=arccos\left(\frac{M^2}{\sqrt{M^4-M_{\max }^4+M_{\max }^2}}\right)\hfill \\ {\alpha }_1=2arccos\left(\frac{\sqrt{M^4-M_{\max }^4+M_{\max }^2}}{M}\right)\hfill \\ {\alpha }_2={\varphi }_o^{*}-\frac{{\alpha }_1}{2}\hfill \end{array}\right.$$

(18)

3.3. Phase I

As shown in Figure 6b2, in order to regulate the output power in Phase I, ${\alpha }_1$ is increased and ${\alpha }_2$ is decreased, while the sum $({\alpha }_1/2+{\alpha }_2)$ is fixed at ${\varphi }_o^{*}$. The results in the phasor diagram are that the length of phasor ${\mathbf{V}}_{\mathbf{AB}}$ is shortened and the angle between the two voltage phasors is still equal to ${\varphi }_o$. During the procedure, the circulation current on the HV side decreases and the circulation current on the LV side increases. Furthermore, the length of the resonant current phasor ${\mathbf{I}}_{\mathbf{s}}$ decreases.

$$\left\{\begin{array}{c}{\alpha }_1=2arccos\left(\frac{G\sqrt{M^4-M_{\max }^4+M_{\max }^2}}{M}\right)\hfill \\ {\alpha }_2={\varphi }_o^{*}-{\alpha }_1/2\hfill \end{array}\right.$$

(19)

Phase I ends when the lengths of two voltage phasors are equal. At the boundary point, the power level is:

$$G_b=cos{\varphi }_o^{*}=\frac{M^2}{\sqrt{M^4-M_{\max }^4+M_{\max }^2}}$$

(20)

and the two phase-shift angles are:

$$\left\{\begin{array}{c}{\alpha }_1=2arccos\left(M\right)\hfill \\ {\alpha }_2={\varphi }_o^{*}-{\alpha }_1/2\hfill \end{array}\right.$$

(21)

3.4. Phase II

As shown in Figure 6b3, only ${\alpha }_2$ is decreased to manipulate output voltage in Phase II. This is an imitation of DAB or DBRC with SPS at unity gain. The length of the resonant current phasor continues to decline, and the circulation current on both the HV side and the LV side decreases.

$$\left\{\begin{array}{c}{\alpha }_1=2arccos\left(M\right)\hfill \\ {\alpha }_2=arcsin\left(\frac{G{M}_{\max }\sqrt{1-M_{\max }^2}}{M^2}\right)-arccos\left(M\right)\hfill \end{array}\right.$$

(22)

In order to realize the case in Figure 6b1, there is a limit on the range of converter gain. The restriction of converter gain is given as:

$$M_{\min }^2>\sqrt{1-M_{\max }^2}$$

(23)

For a converter with a voltage gain range that does not satisfy (23), it is impossible to achieve zero circulation energy at full load. If the power direction is reversed, the piecewise control strategy can be applied as well. It can be understood easily with the fundamental phasor diagram shown in Figure 7.

3.5. A Design Example

The following specifications are used in the paper to illustrate the design procedure: the HV-side voltage $V_{\mathrm{H}}$ is 100 V; the LV-side voltage $V_{\mathrm{L}}$ is 28.8–48 V; the rated power $P_{\mathrm{F}}$ is 200 W; switching frequency $f_{\mathrm{s}}$ is equal to 100 kHz. The design point is selected at the condition with $M=M_{\max }$ (i.e., $V_H=100$V, $V_L=48$ V) and the rated power. The approximately optimal parameters for designing a DBSRC can be chosen according to [10], then the voltage gain M and the normalized switching frequency F in this work are chosen as: $M_{max}=0.96$, $F=1.1$.

According to the definition of converter gain, the HV-to-LV turn ratio of the HF transformer $n_{\mathrm{t}}$ can be calculated:

$$n_{\mathrm{t}}=\frac{V_{\mathrm{B}}·M_{\max }}{V_{\mathrm{Lmax}}}=2.$$

(24)

The impedance base value $Z_{\mathrm{B}}$ is calculated as:

$$Z_{\mathrm{B}}=\frac{n_t^2{V}_{\mathrm{Lmax}}^2}{P_{\mathrm{F}}}=46.08\mathsf{\Omega }$$

(25)

At the design point, the load condition is $G=1$. By using (16), the quality factor is calculated as:

$$Q=\frac{8·sin{\alpha }_2}{{\pi }^2·M·(F-1/F)}=1.238$$

(26)

Therefore, the values of $L_{\mathrm{s}}$ and $C_{\mathrm{s}}$ are calculated as:

$$\begin{array}{c}{L}_{\mathrm{s}}=\frac{QF{Z}_{\mathrm{B}}}{2\pi f_{\mathrm{s}}}=99.87\mathsf{\mu }\mathrm{H}\hfill \\ C_{\mathrm{s}}=\frac{F}{2\pi f_{\mathrm{s}}Q{Z}_{\mathrm{B}}}=30.69\mathrm{n}\mathrm{F}\hfill \end{array}$$

(27)

Results of some particular cases at $M=M_{\max }$ and $M=M_{\min }$ for both positive power and negative power are listed in

Table 1. Phase-shift angles under PW-DPS control for bidirectional power transfer.

Power	${\mathit{\alpha }}_1$	${\mathit{\alpha }}_2$
200 W	0${}^{\circ }$	16.3${}^{\circ }$	full load @$V_{\mathrm{L}}=48V$
192 W	32.6${}^{\circ }$	0${}^{\circ }$	boundary @ $V_{\mathrm{L}}=48$ V
−200 W	0${}^{\circ }$	−16.3${}^{\circ }$	full load @ $V_{\mathrm{L}}=48$ V
−192 W	32.6${}^{\circ }$	−32.6${}^{\circ }$	boundary @ $V_{\mathrm{L}}=48$ V
200 W	84.4${}^{\circ }$	−3.2${}^{\circ }$	full load @ $V_{\mathrm{L}}=28.8$ V
155 W	109.6${}^{\circ }$	−15.8${}^{\circ }$	boundary @ $V_{\mathrm{L}}=28.8$ V
−200 W	84.4${}^{\circ }$	−81.2 ${}^{\circ }$	full load @ $V_{\mathrm{L}}=28.8$ V
−155 W	109.6${}^{\circ }$	−93.8${}^{\circ }$	boundary @ $V_{\mathrm{L}}=28.8$ V

. The calculation of two phase-shift angles can be done similarly with the help of (18)–(22) for other power levels and other voltage gains.

In Figure 8, the relationship between the output power and the phase-shifts for the design example are presented. The contours shown are the levels of normalized bidirectional power. The actual varying paths of the two phase shifts based on the SPS, PW-DPS, and MCT control strategy are all marked for bidirectional power with maximum gain (Figure 8a) and minimum gain (Figure 8b), respectively. Marked in black color, the control path of PW-DPS consists of two line sections. Aligned on the y-axis and marked in blue color, the control path of SPS control is a straight line as well, since ${\alpha }_1$ is always kept at zero. Marked in red color, the control paths under MCT control is a piece of smooth curve, which is almost enclosed by the trajectory of PW-DPS. It can be shown that the MCT and PW-DPS share similar changing trends, even though they are not derived from the same approach.

4. Verification with Simulation and Experimental Results

To verify the proposed PW-DPS control strategy, a series of simulations were performed in PSIM. The DBSRC to be tested has the same specification as designed in the last section. In order to get accurate results, the non-ideal parameters are assigned to the components in PSIM. The diode threshold voltage of power MOSFET is set to 1.3 V, and the on-state resistance of MOSFET is set to 0.06 $\mathsf{\Omega }$. To show the hard switching losses, the parasitic capacitor is set to 0.2 nF. Figure 9a–d presents some simulation plots, which were tested under the full load and half load operation at $M_{\max }$ and $M_{\min }$, respectively, when the net power is positive. The same curves are illustrated for the reverse power flow in Figure 9e–h.

The waveforms recorded in the simulation include: $v_{\mathrm{AB}}$, $v_{\mathrm{XY}}$ (two HF AC voltages), $i_{\mathrm{s}}$ (the resonant current), $i_{\mathrm{H}},i_{\mathrm{L}}$ (the currents on both HV and LV side without filtering), $i_{\mathrm{s}1}$ (switch current of the lagging arm in the HV-side bridge), $i_{\mathrm{s}3}$ (switch current of the leading arm in the HV-side bridge), and $i_{\mathrm{Q}1}$ (switch current in the LV-side bridge). It can be observed from the waveforms of $i_{\mathrm{s}}$ and $i_{\mathrm{Q}1}$ that the circulation current on the LV side is almost zero at full load test and also not significant at half load regardless of the converter gain and power direction, which indicates low conduction losses and high efficiency. The HV side current is discontinuous due to the PWM control except for the operation with full load and maximum converter gain. As for soft-switching conditions, the LV-side switches are able to be turned on/off with zero current under full load condition for both $M_{\max }$ and $M_{\min }$. For half-load test conditions, switches in the LV side are turned on with zero voltage, which can be determined from the waveforms of $i_{\mathrm{Q}1}$. According to the phase delay between $v_{\mathrm{AB}}$ and $i_{\mathrm{s}}$ or the waveforms of switch currents for positive power flow, switches in the leading arm of the HV side bridge can maintain ZVS, while switches in the lagging arm of the HV side bridge would lose ZVS at partial load. When the power flow is negative, the conditions are just opposite, i.e., switches in the lagging arm of the HV side bridge can maintain ZVS, while switches in the leading arm of the HV side bridge would lose ZVS at partial load.

A lab prototype of the DBSRC was built and tested, as well. Eight MOSFET IRFS4620 ($R_{ds}=63.7$ m$\mathsf{\Omega }$) were selected as the main switches. The HF transformer had two windings with an 18:9 turn ratio, which were wound on an ETD39 ferrite core (Material N97). The gating signals were generated from an FPGA board and sent to the IR2181-based driver circuit. The resonant inductor was made of an RM12 air-gapped ferrite core (Material 3C95) wound with nine turns of wire. The photo of the experimental setup is given in Figure 10. The oscilloscope used to measure the waveforms was the Agilent DSO-X 3024A. The voltage probe was the Agilent N2791A, 25-MHz differential probe with an attenuation ratio at 100:1. The current probe was the Agilent N2782B.

The signals measured in the experimental test were HF AC voltage $v_{AB}$, $v_{XY}$, and resonant current $i_s$. In general, the experimental waveforms had a good match with the simulation results. Figure 11 shows the operation condition when the load levels were 200 W and 100 W with $V_L=48$ V. The operation condition when the load levels were 200 W and 100 W with $V_L=28.8$ V are presented in Figure 12. Figure 13 and Figure 14 show the same conditions except for the reverse power flow. As predicted by theoretical calculation and simulation, the circulation current on the LV side in the experimental plots is quite low from full load to partial load. ZVS transition can be observed from the soft rising/falling edges of $v_{AB}$ and $v_{XY}$. In the theoretical calculation, the magnetizing inductance of the HF transformer is neglected. In the actual implementation, the magnetizing inductance may be helpful to maintain ZVS for switches on the LV side, especially at partial load.

For the sake of a fair comparison, the prototype converter was also tested with SPS and MCT control. In Figure 15, the comparisons of the variation of rms resonant current with regards to load level under SPS, MCT, and PW-DPS control are presented for different voltage gains, respectively. It can be seen that there were no significant differences for those three controls when the converter gain was maximum. This can be attributed to the approximated optimal circuit design for maximum converter gain. When the converter gain was away from the designed one, the MCT and PW-DPS still had similar performance, and they showed apparent advantageous over the conventional SPS control, i.e., low rms resonant current, which indicates that the proposed control can provide lower loss and higher efficiency. The measured efficiency of the lab prototype converter under different control schemes is listed in Figure 16 for comparison. It can be shown that both MCT and PW-DPS control were able to maintain relatively high efficiency among a wide range of load levels, while the SPS control had weak performance when the voltage gain was away form the designed value. Being claimed as the minimized current control, MCT control did show better performance over the proposed PW-DPS control; however, the margin was not large. The potential reasons might be: (1) the proposed control happened to be a good piecewise approximation of the MCT, though no minimization calculation was executed; (2) the MCT calculation was also based on the FHA approach, which is known to have limited accuracy, especially at a low load level.

5. Conclusions

To improve the performance of a dual-bridge series resonant converter, a piecewise control strategy based on dual-phase-shift modulation is proposed in this work. This PW-DPS control tends to achieve a compromise between the flexibility and simplicity of control by using only two phase-shift angles. By properly adjusting the two phase-shift angles in two phases, there is no circulation current existing on the low-voltage/high-current side at full load regardless of the power direction and variation of the LV-side voltage. Compared with SPS control, it is found that the proposed control strategy is able to alleviate circulation energy significantly, reduce conduction loss and maintain high efficiency over a wide range of load levels and LV-side voltage. Besides, at least six out of eight switches in the converter can be turned on with ZVS for the whole operation range. Although not derived for the objective to optimize the rms resonant current, the proposed PW-DPS control demonstrates competitive performance compared with the optimized MCT control in terms of rms resonant current and efficiency in a series of experimental tests. The calculation used in PW-DPS control is also simpler than that in MCT control. The number of control variables isless than that of MCT control. Besides, it is not difficult to implement the proposed PW-DPS control in a closed-loop manner. As shown in Equations (18)∼(22), the only parameter that needs to be monitored continuously is the LV-side voltage $V_{\mathrm{L}}$, which can be used to determine the actual voltage gain and the corresponding boundary load level $G_{\mathrm{b}}$ according to (20). Through comparison between the load level command and the boundary load level, the control phase can be determined, and then, the appropriate formula (either (19) or (22)) can be selected to find the correct phase-shift angles. The dynamics and implementation of closed-loop control using PW-DPS deserve more efforts in future work. Using a DBSRC with the proposed PW-DPS with a much higher power rating, the performance of low-load operation might be poor due to the loss of ZVS. These drawbacks also need to be investigated further in the future.