A Countermeasure against DPA on SIMON with an Area-Efficient Structure
Abstract
:1. Introduction
2. Background
2.1. Notation
- m: the keyword size in SIMON algorithm
- n: the word size in SIMON algorithm
- T: the round number of SIMON
- Li, Ri: the left and right half output of the ith round
- Li(j), Ri(j): the jth bit of Li, Ri, j ∈ {1, …, n}
- ki: the ith of the master-key group, i ∈ {1, …, m}
- Ki: the ith of round-key, i ∈ {1, …, T}
- Ki(j): the jth bit of Ki, j ∈ {1, …, n}
- L*, R*: the left and right half faulty output of the each round
- : the jth bit of L*, j ∈ {1, …, n}
- PL(i), PR(i): the ith bit of left and right half part of plaintext, i ∈ {1, …, n}
2.2. Description of SIMON
3. Differential Power Attack on SIMON
3.1. Selection of Power Model
3.2. Implementation of DPA on SIMON
3.3. DPA Experimental Evaluation
4. DPA-Resistant SIMON Based on Power Randomization
4.1. Design of DPA-Resistant SIMON
4.2. Random Bit Generation Circuit
4.3. Implementation of Optimized SIMON Circuit
5. Leakage Quantification
6. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
- Beaulieu, R.; Shors, D.; Smith, J.; Treatman-Clark, S.; Weeks, B.; Wingers, L. The SIMON and SPECK lightweight block ciphers. In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 8–12 June 2015; pp. 1–6. [Google Scholar] [CrossRef]
- Bhasin, S.; Graba, T.; Danger, J.L.; Najm, Z. A look into SIMON from a side-channel perspective. In Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Arlington, VA, USA, 6–7 May 2014; pp. 56–59. [Google Scholar] [CrossRef]
- Fu, K.; Sun, L.; Wang, M. New integral attacks on SIMON. IET Inf. Secur. 2017, 11, 277–286. [Google Scholar] [CrossRef]
- McCann, D.; Eder, K.; Oswald, E. Characterising and Comparing the Energy Consumption of Side Channel Attack Countermeasures and Lightweight Cryptography on Embedded Devices. In Proceedings of the 2015 International Workshop on Secure Internet of Things (SIoT), Vienna, Austria, 21–25 September 2015; pp. 65–71. [Google Scholar]
- Zhang, F.; Guo, S.; Zhao, X.; Wang, T.; Yang, J.; Standaert, F.X.; Gu, D. A Framework for the Analysis and Evaluation of Algebraic Fault Attacks on Lightweight Block Ciphers. IEEE Trans. Inf. Forensics Secur. 2016, 11, 1039–1054. [Google Scholar] [CrossRef]
- Matsuda, S.; Moriai, S.; Zhang, W.; Bao, Z.; Lin, D.; Rijmen, V.; Yang, B.; Verbauwhede, I. RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms. Sci. China Inf. Sci. 2015, 58, 408–425. [Google Scholar]
- Al-Qutayri, M.; Marzouqi, H.; Salah, K. Review of gate-level differential power analysis and fault analysis countermeasures. IET Inf. Secur. 2014, 8, 51–66. [Google Scholar]
- Yoshikawa, M.; Nozaki, Y. Power Analysis Attack and Its Countermeasure for a Lightweight Block Cipher Simon. In Information Technology: New Generations; Springer: Cham, Switzerland, 2016; pp. 151–160. [Google Scholar]
- Shahverdi, A.; Taha, M.; Eisenbarth, T. Lightweight Side Channel Resistance: Threshold Implementations of Simon. IEEE Trans. Comput. 2017, 66, 661–671. [Google Scholar] [CrossRef]
- Chen, C.; İnci, M.S.; Taha, M.; Eisenbarth, T. SpecTre: A tiny side-channel resistant speck core for FPGAs. In International Conference on Smart Card Research and Advanced Applications; Springer: Cham, Switzerland, 2017; pp. 73–88. [Google Scholar]
- Shahverdi, A.; Taha, M.; Eisenbarth, T. Silent Simon: A threshold implementation under 100 slices. In Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, USA, 5–7 May 2015. [Google Scholar]
- Ahir, P.; Mozaffari-Kermani, M.; Azarderakhsh, R. Lightweight Architectures for Reliable and Fault Detection Simon and Speck Cryptographic Algorithms on FPGA. ACM Trans. Embed. Comput. Syst. 2017, 16, 1–17. [Google Scholar] [CrossRef]
- Peeters, E.; Standaert, F.X.; Quisquater, J.J. Power and electromagnetic analysis: Improved model, consequences and comparisons. Integration 2007, 40, 52–60. [Google Scholar] [CrossRef]
- Sasaki, A.; Abe, K. Algorithm-level evaluation of DPA resistance to cryptosystems. Electr. Eng. Jpn. 2008, 165, 37–45. [Google Scholar] [CrossRef] [Green Version]
- Prouff, E.; Rivain, M.; Bévan, R. Statistical analysis of second order differential power analysis. IEEE Trans. Comput. 2009, 58, 799–811. [Google Scholar] [CrossRef]
- Bellizia, D.; Bongiovanni, S.; Monsurrò, P.; Scotti, G.; Trifiletti, A.; Trotta, F.B. Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks. IEEE Trans. Very Large Scale Integr. Syst. 2018, 26, 1368–1376. [Google Scholar] [CrossRef]
- Goodwill, G.; Jun, B.; Jaffe, J.; Rohatgi, P. A testing methodology for side-channel resistance validation. NIST Non-Invasive Attack Test. Workshop 2011, 7, 115–136. [Google Scholar]
- Leiserson, A.J.; Marson, M.E.; Wachs, M.A. Gate-Level Masking under a Path-Based Leakage Metric. In International Workshop on Cryptographic Hardware and Embedded Systems; Springer: Berlin/Heidelberg, Germany, 2014; pp. 580–597. [Google Scholar]
- Bilgin, B.; Gierlichs, B.; Nikova, S.; Nikov, V.; Rijmen, V. Higher-Order Threshold Implementations. In International Conference on the Theory and Application of Cryptology and Information Security; Springer: Berlin/Heidelberg, Germany, 2014; pp. 326–343. [Google Scholar]
Attack Position and Distinguishing Function | Attack Bits | Correlation Bits | Constraint Condition |
---|---|---|---|
L3(1) = [L1(14)&L1(7)]⊕{[K1(16)⊕L1(14)]&[K1(9)⊕L1(7)]} | K1(16) K1(9) | L1(14) L1(7) | L1(1) L1(13) L1(15) L1(8) |
L3(3) = [L1(16)&L1(9)]⊕{[K1(2)⊕L1(16)⊕(L1(1)&L1(10))]&[K1(11)⊕L1(9)]} | K1(2) K1(11) | L1(16) L1(9) L1(10) L1(1) | L1(3) L1(15) |
L3(4) = L1(16)⊕[L1(1)&L1(10)]⊕{[K1(3)⊕L1(1)]&[K1(12)⊕L1(10)]} | K1(3) K1(12) | L1(16) L1(1) L1(10) | L1(4) L1(11) L1(2) |
L3(5) = L1(5)⊕[L1(2)&L1(11)]⊕{[K1(4)⊕(L1(3)&L1(12))]&[K1(13)⊕(L1(12)&L1(5))]} | K1(4) K1(13) | L1(3) L1(12) L1(5) L1(2) L1(11) | L1(1) |
L3(6) = L1(2)⊕[L1(3)&L1(12)]⊕{[K1(5)⊕L1(3)]&[K1(14)⊕L1(12)]} | K1(5) K1(14) | L1(3) L1(12) L1(2) | L1(6) L1(13) L1(4) |
L3(7) = L1(7)⊕L1(3)⊕{[K1(6)⊕(L1(5)&L1(14)]&[K1(15)⊕(L1(14)&L1(7))]} | K1(6) K1(15) | L1(7) L1(3) L1(5) L1(14) | L1(4) L1(13) |
L3(8) = [L1(5)&L1(14)]⊕{[K1(7)⊕L1(5)]&[K1(16)⊕L1(14)]} | K1(7) K1(16) | L1(5) L1(14) | L1(4) L1(8) L1(6) L1(15) L1(16) L1(9) |
L3(9) = L1(9)⊕{[K1(8)⊕(L1(7)&L1(16))]&[K1(1)⊕(L1(16)&L1(9))]} | K1(8) K1(1) | L1(9) L1(7) L1(16) | L1(5) L1(6) L1(15) |
L3(10) = L1(10)⊕[L1(7)&L1(16)]⊕{[K1(9)⊕L1(7)⊕(L1(8)&L1(1))]&[K1(2)⊕L1(16)⊕(L1(1)&L1(10))]} | K1(9) K1(2) | L1(10) L1(7) L1(16) L1(8) L1(1) | L1(6) |
L3(11) = L1(7)⊕[L1(8)&L1(1)]⊕{[K1(10)⊕L1(8)]&[K1(3)⊕L1(1)]} | K1(10) K1(3) | L1(7) L1(8) L1(1) | L1(11) L1(2) L1(9) |
L3(14) = L1(14)⊕{[K1(13)⊕(L1(12)&L1(5))]&[K1(6)⊕(L1(5)&L1(14))]} | K1(13) K1(6) | L1(14) L1(12) L1(5) | L1(4) L1(10) L1(11) |
L3(15) = [L1(12)&L1(5)]⊕{[K1(14)⊕L1(12)]&[K1(7)⊕L1(5)]} | K1(14) K1(7) | L1(12) L1(5) | L1(15) L1(13) L1(6) L1(11) |
Round num | ||
0 | NULL | |
1 | | |
2 | | |
3 | | |
… | … | … |
Original Circuit | Optimized Circuit | |
---|---|---|
LUTs | 99 | 146 |
Registers | 116 | 162 |
Maximum frequency | 312 MHz | 277 MHz |
Throughput | 9.75 Mbps | 8.65 Mbps |
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Zhang, Y.; Wu, N.; Zhou, F.; Zhang, J.; Yahya, M.R. A Countermeasure against DPA on SIMON with an Area-Efficient Structure. Electronics 2019, 8, 240. https://doi.org/10.3390/electronics8020240
Zhang Y, Wu N, Zhou F, Zhang J, Yahya MR. A Countermeasure against DPA on SIMON with an Area-Efficient Structure. Electronics. 2019; 8(2):240. https://doi.org/10.3390/electronics8020240
Chicago/Turabian StyleZhang, Yuanyuan, Ning Wu, Fang Zhou, Jinbao Zhang, and Muhammad Rehan Yahya. 2019. "A Countermeasure against DPA on SIMON with an Area-Efficient Structure" Electronics 8, no. 2: 240. https://doi.org/10.3390/electronics8020240