A functional diagram of the proposed output power combiner is presented in
Figure 3. The circuit was designed based on the impedance requirements for each of the amplifiers at OPBO and at output power saturation. The upper portion of the output combiner is the Main Amplifier output structure which transforms the current modulated load impedance,
ZLoad_Main, into the optimum loads,
Zopt_OPBO and
Zopt_Sat. This section consists of a K-Inverting network which provides impedance inversion and an OMN which is required to absorb the parasitic drain capacitance. Since the K-Inverter provides the same functionality as the IIN, the two terms are used interchangeably in this paper. The optimum impedances
Zopt_OPBO and
Zopt_Sat are the load values required to optimize Power Added Efficiency (PAE) at OPBO and at output power saturation. The lower portion of the output combiner is the Auxiliary Amplifier output structure which transforms the active load,
ZLoad_Aux, into the optimum impedance,
Zopt_Sat, at peak power levels and provides open circuit conditions at OPBO.
The design process for this DPA includes an initial design based on separation of the two amplifiers into subcircuits using equivalent modulated loads for each branch. This process was outlined in reference [
9]. The initial assumption is that the modulating currents,
IMain and
IAux, are in phase at the junction node and produce real impedances. This initial assumption is sufficient to produce the structure of the OMNs and the K-Inverter along with their initial characteristic impedances and electrical lengths. A final optimization is required to minimize the loading effects which occur when the subcircuits are joined. These loading effects manifest themselves as a phase mismatch between
IMain and
IAux along with variation in their ratio. These effects introduce an imaginary component to the modulated active loads
ZLoad_Main and
ZLoad_Aux which varies with frequency.
3.1. K-Inverter Design
The K-Inverter used in most Doherty Power Amplifier designs is typically a quarter-wave transformer. For this design, the quarter-wave transformer was replaced by a broadband K-Inverting structure (see
Figure 4). The equivalent circuit for the new K-Inverter is shown in
Figure 4b. The 2-Port equivalent circuit consists of two transmission lines and a reactive Tee network.
The behavior of the 2-Port network is best described using the concept of image impedance and image phase. For a symmetrical 2-Port network, the image impedance is the load value required to produce an identical impedance value at the input port. The image phase is the delay a signal experiences when propagating through a 2-Port terminated with the image impedance. The image impedance and phase of the 2-Port are equivalent to the characteristic impedance and electrical length of a uniform transmission line. The structure in
Figure 4b behaves as an IIN provided that the image impedance is real over the band of interest and the image phase is an odd multiple of ±π/2. The conditions which guarantee this behavior are outlined in reference [
9,
10]. When these conditions are met, the input impedance is expressed as a function of the load and image impedance, K.
The design equations for the image impedance and the electrical transmission line lengths for the equivalent circuit are as follows:
The relationship between the normalized characteristic impedance,
K/
Zo, and the electrical length,
θ, is given in
Figure 5. By examining this figure, some insight can be gained as to why the K-Inverter equivalent circuit leads to a compact structure. If we compare the uniform transmission line implementation of the IIN to the proposed implementation in
Figure 4b, both implementations require a phase delay of π/2 to operate as an impedance inverter. For the transmission line implementation, this requires a quarter-wave line which is lengthy at lower frequencies. However, for the proposed structure, a phase delay of π/2 is guaranteed provided the equivalent circuit elements
Xa, Xb, Zo, and
θ satisfy the equations presented above. For this design, the normalized image impedance, K/Z
o, is 1.1. From
Figure 5, we see that this value can be obtained using θ values ranging from 18° to 43°. The transmission line lengths used in the K-Inverter equivalent circuit are θ/2; therefore, the range of electrical length values needed to implement the circuit in
Figure 4b is 9° to 21.5°. Since the electrical lengths used in the equivalent model largely determine the size of the distributed realization of the broadband K-Inverter, significant reductions in the output combiner size are achieved.
The solution to the above equations uses positive values for the series reactive element,
Xa, and a negative value for the shunt reactive element,
Xb. This choice of element values leads to positive transmission line lengths and a more realizable circuit. However, the presence of the negative shunt reactive element is a problem when implementing the design using distributed elements. Fortunately, the Tee -Network used in the broadband K-Inverter is structurally similar to a Type-C Brune Section, which is a 2-Port network commonly used in filter design [
11]. These structures are well documented and have several distributed realizations. Under certain conditions, the two reactive Tee networks are equivalent and the distributed realizations for the Brune Section can be applied. The reactive Tee- Networks for the equivalent K-Inverter and the Brune Section are given in
Figure 6a,b along with the equations that link the two structures. A Coupled Inductor representation of the Brune Section,
Figure 6c, is also included since the characteristic impedances for the distributed realization are given in terms of this model.
The Tee networks for the K-Inverter equivalent and Brune Section are similar except for the shunt elements. The shunt element for the Brune Section is the series inductor–capacitor combination,
Xs–Cs, which determines the real frequency zero for the network. The relationship between the two shunt elements is expressed in terms of the inductances
Xb, Xs, and the real frequency zero,
ωο, by
If the zero associated with the Brune Section is larger than the frequency of interest, then the effective shunt element appears negative and the series inductor–capacitor combination approximates the negative shunt element,
Xb, used in the K-Inverter network. In this frequency range, the Brune Section and the reactive tee network used in the broadband K-Inverter network are equivalent. This relationship limits the bandwidth of the proposed distributed implementation. The coupled inductor model for the Brune Section is shown in
Figure 6c. The model comprises the primary and secondary windings,
Lp and
Ls, along with the mutual inductance, M.
These expressions, along with Equation (4), provide a clear link between the reactive Tee-Network and the impedance values for the distributed realization. This is illustrated in
Figure 7.
In
Figure 7a, the equivalent circuit for the broadband K-Inverter is redrawn using the coupled inductor Brune Section model instead of the reactive tee network. The distributed realization of the outlined portion of this network is a coupled line structure loaded with open circuited stubs (
Figure 7b). The equations for the even- and odd-mode characteristic impedances and the characteristic impedances of the open circuited stubs are given below [
12,
13]. Equations (8) and (9) are used to determine the even- and odd-mode characteristic impedances of the coupled structure. The electrical length of the coupled structure is the same as the length—the θ/2 value used in the equivalent model in
Figure 7a.
The characteristic impedances for the open circuited stubs are given in Equations (9) and (10). The lengths for the stubs are adjusted to give the optimal performance over the desired bandwidth.
3.2. Main Amplifier Matching
The initial design of the Main Amplifier portion of the power combiner starts with the half circuit equivalent presented in
Figure 8. The amplifier is presented as a voltage-controlled current source with an output impedance and parasitic drain capacitance.
Zopt_OPBO and
Zopt_Sat are the desired impedances presented to the drain of the amplifier and
Zout_Main is the impedance looking into the Main Amplifier OMN. A reflection coefficient at the device–OMN interface was defined using the two impedances. The parameters which define the Main OMN were obtained by minimizing this reflection coefficient over the frequency band of interest. Referring to
Figure 8, the output impedance,
Zout_Main, is defined in terms of
ZLoad_Main, K, and the ABCD parameters associated with the Main OMN.
In Equation (12),
ZLoad_Main is defined as
For the initial design, it was assumed that
IAux and
IMain are in phase and the active load impedances are purely real. The Main OMN used in this design is a simple L-Network which provides compensation for the parasitic drain capacitance and DC bias for the device. The transmission matrix for this network is given as
These transmission matrix elements can be substituted into Equation (12) and used to define
Zout_Main.
The reflection coefficients at the device–Main OMN interface are defined in Equation (16) for the OPBO and output power saturation cases. These reflection coefficients are a function of the optimum impedances,
Zopt_OPBO and
Zopt_Sat, along with the output impedance
Zout_Main. Γ
Main_OPBO and Γ
Main_Sat are minimized by selecting the proper output impedance values, which are influenced by the L-Network variables
Z3,
θ3,
Z4, and
θ4.
The initial implementation of the Main Amplifier portion of the output combiner is given in
Figure 9 and the simulated output impedances for this structure are given in
Figure 10.
These impedance values were generated by simulating the response of the structure in
Figure 9 to the discrete
ZLoad_Main values of 50 Ω, 67 Ω, 85 Ω, and 100 Ω; these discrete load values represent the active load values at 6 dB OPBO, 3.5 dB OPBO, 1.5 dB OPBO, and output power saturation, respectively.
The simulated load values at the output of the OMN can be compared to the range of simulated loadpull values at each of the output power back-off points (
Table 1a). The Simulated Loadpull Results table consists of the min and max values for the real and imaginary parts of the load admittance which produce acceptable efficiency at each of the OPBO levels. The load definitions are given below.
These values were determined by noting the intersection of the Power and Efficiency contours at the discrete OPBO points and were further restricted by limiting the load Q to values corresponding to the desired bandwidth of the DPA. The range of simulated load values generated at the output of the matching network is displayed on the Smith Chart in
Figure 10 and presented in
Table 1b. The comparison of the two tables validates the design of the Main Amplifier portion of the output combiner.
3.3. Auxiliary Amplifier Matching
The half circuit equivalent for the Auxiliary Amplifier is given in
Figure 11. The process of determining the impedance transformations for the Auxiliary amplifier at OPBO and output power saturation is described below. First, a reflection coefficient was defined at the device–OMN interface and used to determine the network values for the Aux OMN.
The proposed matching network must meet the load requirements for the Auxiliary amplifier at OBPO and output power saturation. At OPBO levels, the Auxiliary amplifier is off and should appear as an open circuit at the summing node. At output power saturation levels, the load impedance is matched to the optimum load value. The impedance looking into the OMN was defined as
Zout_Aux and the equation is given in terms of the modulated load and the ABCD parameters for the matching network.
The modulated load impedance for the Auxiliary Amplifier is given in terms of the current ratio at the junction node and the system load impedance.
Finally, the reflection coefficient at the Auxiliary device–OMN interface is defined. Proper choice of the transmission matrix elements minimizes this function and meets the load requirements at output power saturation.
To meet the load requirements at OPBO, the impedance looking into Aux OMN at the
ZLoad_Aux end of the network must appear as an open circuit. This impedance is denoted as
Z∞ and can be expressed in terms of the transmission matrix element for Aux OMN and cold-fet impedance of the Auxiliary device,
ZAux_Cold.
The network parameters for Aux OMN were determined by satisfying Equations (22) and (23) simultaneously. A shunt transmission line and a stepped impedance network were used to implement this matching network,
Figure 12.
3.4. Optimization of the Complete Power Combiner
The design process described above assumes that the Main and Auxiliary currents are in phase. However, joining the matching networks changes the phase of the two currents at the junction node, which, in turn, changes the modulated loads
ZLoad_Main and
ZLoad_Aux by introducing an imaginary component. The half circuit equivalents for the Main and Auxiliary amplifiers can be used to generate expressions for the junction currents in terms of phase. The drain voltage and current for the main device was defined by introducing the total transmission matrix.
The total transmission matrix was constructed from the K-Inverter, OMN for the Main amplifier, and the parasitic drain capacitance and output impedance blocks.
The expression for the junction current,
IMain, was obtained from Equation (24) and is given below. By examining Equation (26), it is clear that the phase dependency of
IMain is a function of the network elements and the parasitic drain capacitance.
Similar results are presented for the Auxiliary amplifier, and the expression for the junction current, I
Aux is given.
By examining Equations (26) and (29), it is reasonable to conclude that the phase difference between the junction currents is produced by the difference in electrical lengths between the main and auxiliary portions of the output power combiner. The phase difference was minimized in the final design by simulating the entire output power combiner and optimizing the characteristic impedances and electrical lengths of the transmission line elements. The synthesized matching networks, along with a simplified schematic of the Main and Auxiliary devices, were used as part of the final optimization schematic (
Figure 13). The output impedance, drain capacitance, and drain current make up the output equivalent circuits for the Main and Auxiliary devices. A Data Acquisition Component provides the equivalent circuit values at each OPBO point and at discrete frequencies. Current probes were placed at the summing junction to monitor
IMain and
IAux. The ratio of the two currents was added to the list of parameters to optimize. The network parameters were adjusted to minimize the imaginary part of this ratio while still maintaining the proper current ratios and the impedance requirements for the Main and Auxiliary amplifiers over the frequency of interest and at each OPBO level.