A High-Efficiency K-band MMIC Linear Amplifier Using Diode Compensation

Abstract

This paper describes the design and measured performance of a high-efficiency and linearity-enhanced K-band MMIC amplifier fabricated with a 0.15 μm GaAs pHEMT processing technology. The linearization enhancement method utilizing a parallel nonlinear capacitance compensation diode was analyzed and verified. The three-stage MMIC operating at 20–22 GHz obtained an improved third-order intermodulation ratio (IM3) of 20 dBc at a 27 dBm per carrier output power while demonstrating higher than a 27 dB small signal gain and 1-dB compression point output power of 30 dBm with 33% power added efficiency (PAE). The chip dimension was 2.00 mm × 1.40 mm.

1. Introduction

GaAs MMIC is regarded as the premier power device for the microwave communication system [1] and phase array radar system [2] witnessed in recent decades. However, when facing high peak-to-average ratio (PAR) modulation schemes such as QPSK and OFDM, the nonlinearity of the power amplifier causes spectral reproduction and intermodulation distortion. When multi-signals are amplified within a single channel, the beat between carriers generates amplitude modulation [3].

To meet the linearity requirements in the point-to-point radio or satellite communications which usually operate with a high PAR and inconstant enveloped input signal, conventional designs have to work at a back-off output point compared to their saturated power level. Thus, several techniques have been employed to improve the efficiency in the low power region, such as the linear Doherty design, feed-forward technique, and envelop feedback. Some linear Doherty amplifier [4] and feed-forward designs [5] show a high linearity at an acceptable efficiency; however the complexity and cost of chips are not low. Class-J [6] was also reported to achieve a high linearity in the back-off region. Those technologies usually generate a high circuit complexity. Some literature has also reported on the possibility of inner chip nonlinear compensation methods based on diodes [7]. However, no concrete MMIC design has been proposed.

This paper presents a high-efficiency K-band MMIC linear power amplifier fabricated with a 0.15 μm GaAs pHEMT processing technology. A kind of linearizer circuit of diode nonlinear compensation was accomplished. The Y-parameter matrix method was used to analyze and deduce the dynamic characteristic of the parallel diode and FET network. Both simulation and measurement results show the linearity improvement of the circuit. As a result, the proposed linear amplifier achieved an excellent performance with more than a 1 W output power and 33% power-added efficiency at the 1-dB compression point while maintaining an IM3 better than 20 dBc at an output power of 27 dBm per carrier over a 20–22 GHz band.

2. Nonlinear Analysis and Diode Compensation

Table 1. The parameters of the 0.15 μm GaAs pHEMT process.

Parameter	Value	Parameter	Value
VTH (V)	−1.2	ft (GHz)	85
VBDG (V)	10	Gm_Peak (mS/mm)	495
Idmax (mA/mm)	650	Pdensity (W/mm)	0.8
Idss (mA/mm)	500	CMIM (pF/mm2)	400

shows the main parameter of the 0.15 μm GaAs pHEMT process. The equivalent circuit models of pHEMT and a diode are shown in Figure 1.

Using a diode depletion capacitance model [8], the values of C_gs and C_gd can be derived as

$$C_{gs}(v_{gs})=\frac{C_{gsb}}{\sqrt{1-\frac{v_{gs}}{v_{bi}}}}$$

(1)

$$C_{gd}(v_{gd})=\frac{C_{gdb}}{\sqrt{1-\frac{v_{gd}}{v_{bi}}}}$$

(2)

The functional model of a single-stage pHEMT amplifier can be represented by Figure 2.

In this model, V_S(ω) and Z_S(ω) constitute the Thevenin equivalent of the excitation source and the input matching network, and Z_L(ω) is the load impedance of the pHEMT. Assuming that the pHEMT is excited by a voltage, v_gs(A, t):

$$v_{gs}(A,t)={\displaystyle \sum _0^n{V}_{gsk}(A,\omega )\cdot \cos (}k{\omega }_{0}t)$$

(3)

where V_gsk represents the Fourier components of v_gs and A is the amplitude. By setting the dynamic charge between the gate and source determined by v_gs as Q_gs, i_gs can be derived as

$$i_{gs}(t)=\frac{\partial Q_{gs}[v_{gs}]}{\partial t}=C_{gs}[v_{gs}]\cdot \frac{\partial v_{gs}}{\partial t}$$

(4)

Then, we get the frequency domain representation of i_gs as

$$I_{gs}=[\frac{1}{2}{\displaystyle \sum _{-n}^n{C}_{gsk}(V_{gs},\omega )}]\cdot [\frac{1}{2}{\displaystyle \sum _{-n}^{n}jk}{\omega }_0{V}_{gsk}]$$

(5)

where C_gsk is the Fourier components of C_gs:

$$C_{gsk}=\frac{\omega }{2\pi }{\displaystyle {\int }_{-\pi /\omega }^{\pi /\omega }{C}_{gs}[v_{gs}]\cdot e^{-jk{\omega }_{0}t}}dt$$

(6)

Substituting (R4) into (R3), the fundamental component of i_gs would be

$$I_{gs1}=j{\omega }_0{C}_{gs0}{V}_{gs1}+\frac{1}{2}j2{\omega }_0{C}_{gs1}{}^{*}\cdot V_{gs2}-\frac{1}{2}j{\omega }_0{C}_{gs2}\cdot V_{gs1}{}^{*}+\dots$$

(7)

As a result, the fundamental v_gs(t) voltage V_gs1 (A) can be derived as

$$V_{gs1}=V_S(\omega )-j\omega Z_s(\omega )\{C_{gs0}\cdot V_{gs1}+C_{gs1}{}^{*}\cdot V_{gs2}-\frac{1}{2}{C}_{gs2}\cdot V_{gs1}{}^{*}+\dots \}$$

(8)

and solving (8) leads to

$$V_{gs1}=\frac{V_s(\omega )}{1+j\omega Z_s(\omega )\cdot C_{gs0}}$$

(9)

The term involving C_gs2 and V_gs2 is neglected as it is significantly smaller than the others. Incorporating the feedback capacitor C_gd into (9), we get

$$V_{gs1}=\frac{V_s(\omega )}{1+j\omega Z_s(\omega )\cdot [C_{gs0}+C_{gd}(1-A_v)]}$$

(10)

(10) reveals that C_gs and C_gd influence the phase of fundamental v_gs(t), which leads to AM/PM distortion. Using a similar method, we can derive the fundamental v_ds(t) voltage V_ds1 (A) as

$$V_{ds1}(A)\approx \frac{Z_L(\omega )\cdot I_{d1}(A)}{1+j\omega Z_L(\omega )\cdot [C_{ds0}(A)+C_{gd}(\frac{A_v-1}{A_v})]}$$

(11)

The term involving C_ds2 is neglected as it is significantly smaller than the others. Since the denominator of (11) is approximately equal to unity [9], as a result, there is no significant impact on AM/PM brought about by C_ds. From (10) and (11), it can be derived that the main contributors to the AM/PM distortion are the variations of C_gs and C_gd. According to the barrier capacitance effect, the value of C_gs is usually much bigger than that of C_gd. Therefore, the nonlinear characteristic of pHEMT is mainly contributed by C_gs, which approximately equals C_in. As shown in Figure 3, a Schottky diode is parallel in the gate and the drain of the output stage FET to compensate for the nonlinearity of C_gs.

The voltage between the reverse diode is

$$v_{diode}=v_{ds}-v_{gs}$$

(12)

The two-port Y-parameter matrix can be utilized to analyse the parallel network composed of the FET and diode. The matrix form of FET is as follows:

$$\left[\begin{array}{c}{i}_g\\ i_d\end{array}\right]=\left[\begin{array}{cc}{y}_{11}& y_{12}\\ y_{21}& y_{22}\end{array}\right]\left[\begin{array}{c}{v}_{gs}\\ v_{ds}\end{array}\right]$$

(13)

where

$$y_{11}=\frac{j\omega C_{gs}}{1+j\omega C_{gs}{r}_{gs}}+j\omega C_{gd}$$

(14)

$$y_{12}=-j\omega C_{gd}$$

(15)

$$y_{21}=\frac{g_m}{1+j\omega C_{gs}{R}_{gs}}-j\omega C_{gd}$$

(16)

$$y_{22}=\frac{1}{r_{ds}}+j\omega (C_{ds}+C_{gs})$$

(17)

Incorporating the diode barrier capacitance into the matrix,

$$y_{11}{}^{\prime }=\frac{j\omega C_{gs}}{1+j\omega C_{gs}{r}_{gs}}+j\omega (C_{gd}+C_{diode})$$

(18)

$$C_{in}{}^{\prime }=-\frac{1}{\omega \mathrm{Im}\left(\frac{1}{y_{11}{}^{\prime }}\right)}$$

(19)

C_in′ represents the input capacitance of the network. According to the previous analysis, the state of input capacitance mainly determines the nonlinear characteristics of the network. Thus, it is possible to perform distortion compensation utilizing the high-frequency C-V characteristic of the diode. As v_diode < 0, C_diode is dominated by depletion layer capacitance C_j, where

$$C_j=\frac{C_{j0}}{\sqrt{1-\frac{v_{diode}}{{\mathrm{\Phi }}_B}}}$$

(20)

where Φ_B is the junction built-in potential, so

$$C_{in}{}^{\prime }=\frac{{\left[\omega C_{gs}{R}_{gs}(C_{gd}+C_j)\right]}^2+{(C_{gs}+C_{gd}+C_j)}^2}{{(\omega C_{gs}{R}_{gs})}^2(C_{gd}+C_j)-(C_{gs}+C_{gd}+C_j)}$$

(21)

As the input RF power increases, the electric field within the FET channel is enhanced, which makes the swing of both v_gs and v_ds become higher. However, the negative swing of v_ds is limited by the knee voltage (V_knee) and the positive swing of v_gs is limited by the diffusion barrier voltage (V_diff). As a result, $\overline{v}$_ds grows higher while $\overline{v}$_gs grows lower. Consequently, $\overline{v}$_diode (3) becomes higher while $\overline{v}$_gs becomes lower. The voltage waveform versus input RF power is shown in Figure 4.

Therefore, substituting (1), (2), and (20) into (21) and combining the voltage analysis above, the characteristics of input capacitance can be shown as the curve in Figure 5.

The principles for the choice of diode periphery are as follows.

• The size of the diode should be large enough to compensate for the input capacitance of the pHEMT as the input power increases;
• The barrier capacitance of the diode should not be too large to over change the input characteristics of the HMET and generate excessive feedback between drain and gate.

Figure 6 shows that as the size of diode increases, the additional feedback becomes stronger. As a result, the MaxGain of the network decreases, which leads to lower linear gain. Therefore, combined with the C-V characteristics of the diode shown in Figure 5a, we gradually adjusted the diode size so that it could effectively compensate for the input capacitance of pHEMT while reducing the effect on the gain. The C-V characteristics of the selected 2 × 20 μm diode and the input capacitance of the network versus RF power are shown in Figure 7.

The parasitic parameter value of the selected pHEMT and diode is shown in

Table 2. The parasitic parameter value of the 8 × 100 μm pHEMT

Parameter	Value	Parameter	Value
rg (Ω)	1.5	Ld (pH)	8.5
rd (Ω)	1.2	Ls (pH)	0.7
rs (Ω)	0.2	Cpg (fF)	9.5
Lg (pH)	9.5	Cpd (fF)	17.5

and

Table 3. The parasitic parameter value of the 2 × 20 μm diode

Parameter	Value
rgs (Ω)	41.5
Cpg (fF)	89.0
Cps (fF)	33.5
Lgs (pH)	55.0

, respectively.

Converting (7) to the S-parameter matrix:

$$\left[\begin{array}{c}{b}_1\\ b_2\end{array}\right]=\left[\begin{array}{cc}{S}_{11}& S_{12}\\ S_{21}& S_{22}\end{array}\right]\left[\begin{array}{c}{a}_1\\ a_2\end{array}\right]$$

(22)

where

$$S_{11}=\frac{(1-Z_0{y}_{11})(1+Z_0{y}_{22})+y_{12}{y}_{21}{Z}_0{}^2}{\mathrm{\Psi }}$$

(23)

$$S_{12}=\frac{-2Y_{12}{Z}_0}{\mathrm{\Psi }}$$

(24)

$$S_{21}=\frac{-2Y_{21}{Z}_0}{\mathrm{\Psi }}$$

(25)

$$S_{22}=\frac{(1+Z_0{y}_{11})(1-Z_0{y}_{22})+y_{12}{y}_{21}{Z}_0{}^2}{\mathrm{\Psi }}$$

(26)

$$\mathrm{\Psi }=(1+Z_0{y}_{11})(1+Z_0{y}_{22})-y_{12}{y}_{21}{Z}_0{}^2$$

(27)

Using the S-parameter to derive the stability factor of the network:

$$k=\frac{1-{\left|S_{11}\right|}^2-{\left|S_{22}\right|}^2+{|\Delta |}^2}{2\left|S_{12}\right|\left|S_{21}\right|}$$

(28)

$$\Delta =S_{11}{S}_{22}-S_{12}{S}_{21}$$

(29)

The factor k > 1 is a necessary and sufficient condition for network stability. Since the diode compensation method generates additional feedback between the gate and drain, the stability of the network is enhanced compared with single FET. The conclusion can be verified by calculation or simulation. The simulation result of the stability factor is shown in Figure 8.

Consequently, because of the nonlinear effect of the diodes, the input capacitance of the network is compensated for as the input power increases, thus avoiding the degradation of linearity. As the diode is operated in an inverted connection, there is nearly no additional current or power loss in the circuit.

3. Circuit Design

The K-band MMIC linear amplifier is composed of three-stage FETs fabricated with a 0.15 μm gate length AlGaAs/GaAs pHEMT technology. The process exhibits a gate-drain breakdown voltage of 16.5 V and a cutoff frequency (f_T) of 90 GHz. The FETs for the power stage are 8 × 100 μm. Source-pull and load-pull simulations using a large signal model at a center frequency were taken to determine the optimal input and output impedances that lead to a higher output power and efficiency. The output matching network combining two FETs matches the fundamental load impedance based on the load-pull simulation. The interstage and input matching networks are designed to match the conjugated impedance and were optimized for low loss. The circuit of the amplifier configuration is shown in Figure 9. The simulation result of the amplifier is shown in Figure 10 and Figure 11.

Figure 10 and Figure 11 show the improvement of the amplifier linearity performance generated by the parallel diode circuit design.

4. Measurement Results

The fabricated three-stage K-band linear amplifier MMIC is shown in Figure 12. The MMIC size is as small as 2.00 × 1.40 mm² with a GaAs substrate thickness of 50 μm. Linear S-parameter and large signal measurements were performed at a drain voltage of 5 V and gate voltage of −0.8V on a wafer. Figure 13 shows the measured S-parameter of the MMIC from 19.5 GHz to 22.5 GHz. The design has achieved higher than a 26 dB small signal gain and better than a 10 dB input return loss. Figure 14 illustrates the measured output power and PAE for the amplifier at fixed input drive levels of +3.5 dBm under a continuous wave (CW). At the nominal supply of VD = 5 V and VG = −0.8 V, the amplifier demonstrates higher than 30 dBm P1dB with 33–35% PAE over a 20–22 GHz frequency. Very flat power and gain characteristics were achieved for this design. Further PAE improvement should be possible with a more precise power match by the result of a load-pull test.

Two-tone measurement of the amplifier has been performed with 10 MHz tone spacing under the drain voltage of 5 V and gate voltage of −0.8 V. The intermodulation distortion was measured on a wafer with 10 MHz two-tone spacing. The two carrier sources were connected to the chip through a power combiner with an isolator in order to reduce the intermodulation contributions of the setup. As shown in Figure 15, IMD3 better than 20 dBc and PAE higher than 33% were measured at an output power of 27 dBm per carrier over a 20–22 GHz band. Compared to the design without an inner paralleled diode configuration, there is more than a 5dB improvement of IMD3.

Table 4. Performance comparison of linear amplifiers.

Reference	Process	Frequency (GHz)	P−1dB (dBm)	PAE (%)	Gain (dB)	IMD3 (dBc)	Size (mm2)
[10]	0.15 µm GaAs	20–23	31	24	9.5	-	-
[11]	0.25 µm GaAs	22.8–23.5	28	15.3	25	-	2.52
[12]	0.25 µm GaAs	18–27	31.4	27	14	18	3.91
[13]	0.15 µm GaAs	17–20	28	30	21	14	2.96
[14]	0.15 µm GaAs	24–28	28	21	21	15	4.50
This work	0.15 µm GaAs	20–22	30	34	27	20	2.80

summarizes the performance comparison of this work with other published linear amplifiers working in close frequency ranges. The characteristics of the amplifier, including power, gain, efficiency, and IMD3, are better than the previously reported ones.

5. Conclusions

In this paper, a three-stage K-band 20–22 GHz high-efficiency linear MMIC power amplifier using 0.15 μm GaAs pHEMT technology is reported. The design utilizes an optimum paralleled diode circuit for inner chip linear compensation. The MMIC generates an output power of 30 dBm and PAE of 33% at −1 dB gain compression under CW operation and delivers a lower than −20 dBc IMD3 performance with 10 MHz tone spacing. The MMIC has a smaller size and more than a 5dB improvement of IMD3 was observed.