Optimization of the Cell Structure for Radiation-Hardened Power MOSFETs

Abstract

Power MOSFETs specially designed for space power systems are expected to simultaneously meet the requirements of electrical performance and radiation hardness. Radiation-hardened (rad-hard) power MOSFET design can be achieved via cell structure optimization. This paper conducts an investigation of the cell geometrical parameters with major impacts on radiation hardness, and a rad-hard power MOSFET is designed and fabricated. The experimental results validate the devices’ total ionizing dose (TID) and single event effects (SEE) hardness to suitably satisfy most space power system requirements while maintaining acceptable electrical performance.

1. Introduction

Power MOSFETs are widely applied in space power systems [1]. However, they are vulnerable to particle from galactic cosmic rays, solar flares, and radiation belts, which may cause total ionizing dose effects, single event gate rupture (SEGR) effects and single event burnout (SEB) effects [2,3]. There has been a substantial research on such radiation effects [4,5,6,7], whereas radiation hardening on power MOSFETs, the more necessary resolve, has only been discussed in a few articles [8,9,10,11,12] whose content mostly focused on a single hardening issue, such as SEB, SEGR, and TID. Apparently, these radiation effects, along with electrical performance, are essential considerations during the design and fabrication stage of a power MOSFET; moreover, many trade-offs should be decided when balancing between several electrical parameters and radiation survivability. This paper entails a description of the design and fabrication of TID-, SEB-, and SEGR-hardened power MOSFETs, on the basis of a careful optimization of the devices’ cell structure and doping profile. Experimental verifications conducted show excellent radiation hardness and acceptable electrical performance of such devices for space power systems.

2. Design Considerations

2.1. Cell Structure

A power MOSFET chip is composed of several regions, including cell region, termination structure, gate bus, and gate pad. Of these, the cell region determines many electrical parameters and typically accounts for the majority of the chip area. However, it is also the most vulnerable region to irradiation. Normally, SEGR, SEB, and TID effects should be simultaneously mitigated in the cell region, whereas in other regions, only one of these effects is considered.

The cell structures and geometrical parameters of a power MOSFET are detailed in classic textbooks on power semiconductors [13,14]. Such geometrical parameters, together with the doping profiles, determine most of the device’s electrical parameters, such as on-resistance (R_on), threshold voltage (V_th), and breakdown voltage (BV_ds). Nonetheless, the present study does not consider detailed discussions regarding the effect of these parameters on the performance of the device. However, the electrical performance must be reasonably reserved when radiation-hardened power MOSFETs are designed.

2.2. Oxide Thickness

Gate oxide thickness is affected by three major factors, namely threshold voltage, SEGR effects and TID effects, and secondary factors as device capacitance and electro-static discharge (ESD) robustness. TID effects are mitigated by keeping the gate oxide as thin as possible [15]. Conversely, a thin gate oxide exhibits a reduced ability to withstand the SEGR effects [16]. Most power MOSFETs are designed within a pre-irradiation threshold voltage (V_th) of 2–4 V. Certain radiation hardness requires V_th to remain within such specifications after receiving a specified dose, followed by high-temperature annealing. On this basis, the chosen V_th is greatly influenced by the shifting behaviors. The shifts could be negative or positive, depending on the dominant type of radiation-induced charge [15]. For negative-shifting-dominated cases, a higher V_th can save additional room for V_th shifting and is thus preferred. By contrast, for positive-shifting-dominated cases, a lower V_th is preferred for the same reason. Once the gate oxide t_OX is given, V_th can be adjusted by changing the doping density in the channel region.

Likewise, SEGR effects are mitigated by keeping the t_OX large enough to avoid dielectric breakdown. During a heavy ion strike, the dielectric strength is temporarily reduced. Models with more physical insight were proposed by Javanainen et al. [17], although a simple empirical expression with little physical justification is adopted in this work, as follows [16]:

$$E_{CRIT}=\frac{V_{GS}}{t_{OX}}= \frac{E_{BD}}{\left(1+\frac{Z}{44}\right)},$$

(1)

where E_CRIT is the critical electric field of gate oxide that must withstand heavy-ion injection; E_BD is the intrinsic dielectric breakdown strength of gate oxide, which is 10⁷ V/cm for most thermal oxides; and Z is the atomic number of the injected heavy ions.

In rad-hard power MOSFETs’ datasheets, SEE resistance ability is illustrated as a safe operating area under certain heavy-ion injection (SEE SOA) [18,19]. In principle, SEE SOA is expressed as a series of gate and drain voltage bias conditions. The negative gate bias is directly applied to the gate to contribute all its value to the gate dielectrics, whereas only a portion of the drain bias is coupled to the gate dielectrics after heavy-ion injection [20]. Therefore, the minimum gate oxide bounded by SEGR effects can be calculated as follows:

$$t_{OX,min}=\frac{\left(\alpha V_{DS}-V_{GS}\right)\left(1+\frac{Z}{44}\right)}{E_{BD}},$$

(2)

where α is the coupled ratio of drain voltage related to the device design, as discussed later. Note that the bias conditions considered here are the worst bias conditions for SEGR production and are, hence, used for SEGR testing. The shift in the threshold voltage due to TID effects is a major problem for all metal-oxide-semiconductor (MOS) devices. For power MOSFETs, the relatively thick gate oxide makes this issue more severe. The V_th shift has been attributed to two kinds of radiation-induced charges, namely oxide charges and interface traps [15]. Therefore, the V_th shift (ΔV_th) is the sum of the oxide-charge-induced negative shift, named ΔV_ot, and the interface-trap-induced positive shift, named ΔV_it. Both ΔV_ot and ΔV_it are strongly related to t_OX. The relationship can be expressed as follows [21]:

$$\Delta V_{ot,it}=\frac{1}{C_{OX}}\times \frac{-1}{t_{OX}}{{\displaystyle \int }}_0^{t_{OX}}{\rho }_{ot,it}\left(x\right)xdx,$$

(3)

where ρ_ot,it is the charge distribution of radiation-induced oxide-trapped or interface-trapped charge. Reduction of t_OX entails a two-fold effect. First, reducing t_OX can reduce the V_th shift for a given charge density, which is attributed to a larger C_OX resulting from a thinner t_ox. Second, it can reduce charge generation for a given dose, as shown in Equation (3). The integration term can be simplified by introducing a uniform charge generation for the oxide charge, resulting in the expression [22]:

$$\Delta V_{ot}=-\frac{\Delta Q_{ot}}{C_{OX}}=-\frac{q{g}_{0}D{t}_{OX}{Y}_h{\sigma }_h}{C_{OX}}=-\frac{q{g}_{0}D{Y}_h{\sigma }_h}{{\epsilon }_{OX}}{t}_{OX}^2,$$

(4)

where q is the electric charge (expressed in Coulomb), g₀ is the electron–hole pair generation rate in SiO₂ (in pairs/cm³/rad(SiO₂)), D is the total dose level in units of rad(SiO₂), Y_h is charge yield of holes, σ_h is trapping cross section for holes captured by hole traps in oxide, and ε_OX is the dielectric constant of SiO₂. Note that Y and σ are affected by the electric field presented during irradiation, and the trapped charges can also be annealed with elevated temperature.

Interface traps generation is much more complicated. However, protons are considered to play a key role in the formation of interface traps. Moreover, the process of proton generation in the oxide is intimately related to the transport of holes. By introducing the parameter Y_p, which is the product of N_D’H (concentration of hydrogen-containing defects) and σ_D’H (cross section for proton release from these defects) [23], ΔV_it can be expressed in a similar manner as ΔV_ot, as follows:

$$\Delta V_{it}=\frac{\Delta Q_{it}}{C_{OX}}=\frac{q{g}_{0}D{t}_{OX}{Y}_h{Y}_p{\sigma }_p}{C_{OX}}=\frac{q{g}_{0}D{Y}_h{Y}_p{\sigma }_p}{{\epsilon }_{OX}}{t}_{OX}^2,$$

(5)

where σ_p is the cross section of protons captured by the traps at interface. Note that for one to get a relatively simple solution, a uniform distribution of N_D’H (and, hence, the Y_p) in terms of space has been assumed, which may not be true for all cases. Moreover, N_D’H is space-and-time-dependent and σ_p is field-dependent. Therefore, a simple method for quantitatively calculating the radiation-induced interface traps for all cases seems impractical, if not impossible. However, as an analytical model, Equation (5) does reflect the relationship of the interface trap generation with the hole transport, as widely accepted by society. Combining Equations (4) and (5) allows the maximum t_OX bounded by the TID effects to be expressed as follows:

$$t_{OX,max}=\sqrt{\frac{\Delta V_{th,max}\times {\epsilon }_{OX}}{q{g}_{0}D{Y}_h\left|Y_p{\sigma }_p-{\sigma }_h\right|}},$$

(6)

where ΔV_th,max is the maximum allowed threshold shift. Note that even for a given dose, |Y_pσ_p − σ_h| varies with dose rate, bias condition, and temperature and is strongly related to the fabrication process. Given this limitation and the uncertainties, |Y_pσ_p − σ_h| remains a useful parameter to be extracted from the experimental perspective and can thus be used as a starting point in the device’s design. Manipulating Equations (2) and (6) yields the lower and upper bounds of t_OX. Once t_OX is chosen, channel doping density can be fixed with equations governing V_th.

2.3. JFET Region Width

Parameter α has been introduced in Section 2.2 to account for the coupling of drain voltage to the gate dielectric. Based on Equation (2), the lower bound of t_OX can be reduced with reduced α, which means that a larger range of t_OX is available at the design stage. Moreover, α has been demonstrated to correlate with JFET region width (L_JFET) and thus can be reduced, with a reduced L_JFET [10], as illustrated in Figure 1.

Although it greatly improves SEGR hardness, a small L_JFET creates a negative impact on R_on. The specific resistance contributed by the JFET region (R_JFET,SP) can be expressed as follows:

$$R_{JFET,SP}={\rho }_{JFET}{H}_{JP}\frac{L_{CELL}}{L_{JFET}},$$

(7)

where ρ_JFET is the resistivity of the JFET region, which is inversely proportional to JFET region doping; H_JP is body junction depth; L_CELL is the cell pitch; and L_JFET is the JFET region width. According to Equation (7), R_JFET,SP is inversely proportional to L_JFET; thus, decreasing L_JFET will greatly increase R_JFET,SP, leading to worse resistance. Fortunately, the JFET region’s resistance is only a portion of the total resistance. Therefore, the increasing on-resistance can be tolerated, as long as L_JFET is not extremely small. Nevertheless, the chosen L_JFET remains a critical element. A previous study [10] asserted that for 250 V power MOSFETs, L_JFET should be less than 5.8 µm to achieve a full V_DS range under zero gate bias. The JFET region should be carefully designed for SEGR-hardened devices.

2.4. P Body and P+ Well Doping

Several models have been proposed to describe the SEB process [24,25,26]. For instance, the parasitic BJT has been postulated to play a key role in SEB production. With the P-body region of the power MOSFET acting as the base region of the parasitic BJT, the body’s doping profile becomes essential for hardening the device against SEB effects. In general, larger P-body depth (H_JP) and higher doping concentrations (N_BODY), as well as a reduced length between N+ source edge and P+ well edge (L_BODY), are desirable for an SEB-hardened cell design. However, as expressed in Equation (7), a deeper P-body has negative effects on R_JFET,SP, whereas a high N_BODY or a short L_BODY may affect the channel doping concentration.

3. Results

TID- and SEE-hardened power MOSFETs were designed on account of the trade-offs mentioned above. The key geometrical parameters and doping concentrations essential for the design are summarized in

Table 1. Key geometrical parameters and doping concentrations for device design.

Symbol in Figure 1	Value	Unit
tox	80	nm
HJP	3	µm
LCELL	10	µm
LBODY	~2	µm
LJFET	~3	µm
NBODY	~5 × 1016	cm−3

. Buffer layer technology was employed to improve SEB hardness [11]. The values of other parameters were chosen as common non-rad-hard power MOSFET designs. The whole chip area was 12 mm², whereas the active area (cell region) was approximately 8.5 mm². Stripe cell topology [10] was considered.

The designed power MOSFETs were fabricated by Tianjin Zhonghuan Semiconductor Co., Ltd., with 6-inch wafers. Processes with high thermal budget, such as the P-body driven process, were adjusted prior to gate oxidation to improve TID hardness. Diced devices were packaged in TO-220. Ninety devices were randomly selected for testing under a Keysight B1506 power semiconductor analyzer. Figure 2 illustrates the distributions of the testing results, with median BV_ds around 120 V and median R_on around 44 mΩ. For this cell design, for a 120 V maximum blocking ability, the specific resistance was 3.74 mΩ-cm². All the V_th values fell in the range of 2.36–2.62 V, of which more than 80% were roughly 2.40–2.50 V (not depicted in the figure). The ESD endurance exceeded 2000 V in human body model (HBM) mode, and the maximum avalanche energy was 662.5 mJ.

Figure 3 illustrates the typical output and transfer curves, as measured with the Keysight B1506. The B1506 testing system has two modes, namely high-current and low-current modes. On the one hand, the high-current mode is able to test current up to 20 A; the plateau is caused by this limitation. However, this mode is not suitable for testing low current because of the leakage issue. On the other hand, the low-current mode is able to test current under a picoampere, although the maximum current in this mode is 1 A. The transfer curves in Figure 3 combined the results for both testing modes.

The fabricated devices were irradiated with Co-60 at the Shanghai Institute of Applied Physics, Chinese Academy of Sciences. The devices were placed on especially designed PCB boards, allowing separately the gate and drain node biases. The PCB boards were separated from the radiation source by approximately 30 cm, thus yielding a calculated dose rate of 100 rad(Si)/s. Additionally, the PCB boards were made to be as small as possible to minimize the dose rate inhomogeneous. Subsequently, the devices were irradiated under room temperature and then annealed at 100 °C for 168 h under the same bias condition after irradiation. For the gate bias condition (GB), the gate was biased at 12 V, with the drain and the source connected to ground. For the drain biased condition (DB), the drain was biased at 80 V, with the gate and the source connected to ground. Three devices were tested under each bias condition. Results of the TID experiment are displayed in Figure 4.

Based on the figure, the on-resistance and breakdown voltage indicated negligible change after 150 krad(Si) TID irradiation and 168 h annealing, for both bias conditions. I_dss also increased with the dose for GB and DB, whereas I_dss increased after annealing under GB and consequently decreased under DB. For the threshold voltage, V_th decreased with the dose for both bias conditions, but with different annealing behavior. More specifically, V_th rebounded to a value slightly higher than its initial value under GB, whereas the rebound was much less under DB. Nonetheless, for each bias condition, at 150 krad(Si) dose, the annealing-induced V_th shift was less than 0.25 V. The shift behaviors of V_th during irradiation and annealing are described further under the discussion section. The terminations used in these devices included a traditional floating ring and filed plate structure, with optimized parameters [9]. The small BV_ds and I_dss change (Figure 4) indicate that the design of the termination was also radiation-hardened.

SEE experiments were conducted at Institute of Modern Physics, Chinese Academy of Sciences. The chips were packaged in TO-39, with the cap removed. 794 MeV Xe ions with a surface linear energy transfer (LET) of approximately 66 MeV·cm²/mg were used. During the experiment, V_GS was set to 0 V, and V_DS was increased in steps of 10 V. The flux was roughly within 5000–10,000 ions/cm²s; the pass criteria was both gate and drain leakage current stay within the specification value after 2 × 10⁶ ions/cm² irradiation [19]. Neither SEB nor SEGR was observed under V_DS = 100 V with a V_GS = 0 V bias condition.

4. Discussion

In space applications, the dose rate is much lower than the high-dose rate (HDR) experiment typically performed in laboratory. Such disparity may cause a significant difference of |Y_pσ_p − σ_h| used in Equation (6) in the two cases. However, low-dose rate (LDR) experiments are relatively time-consuming and expensive. Therefore, the present study adopted an accelerated aging test to estimate the worst-case degradation of MOS devices [27,28], as it has been proven applicable to power MOSFETs [29]. Initially, the devices were irradiated with HDR for a relatively short time. Since the interface traps took a longer time to form, hole trapping in oxide defects dominated in this stage, thereby yielding |Y_pσ_p − σ_h| ≈ σ_h and a negative ΔV_th. In the annealing stage, the build-up of interface traps dominated while the trapped oxide charges decreased with time, yielding a recovery or even a rebound of ΔV_th. Therefore, the HDR+ high-temperature annealing procedure eliminated charge compensation in the LDR environment and produced worse (conserved) results. To further investigate the details of the behavior of radiation-induced charges, a mid-gap method was used to separate these two charges [30,31], where V_T is the threshold voltage extracted by using the maximum transconductance method. Here, note that V_T was different from V_th in Figure 4b, which was basically the gate voltage as the drain current reached 1 mA. Therefore, it was convenient for the engineer to monitor V_th. On the other hand, V_T has a physical meaning and is more accurate for parameter calculation. The mobility was extracted as follows:

$$\sqrt{I_D\left(sat\right)}=\sqrt{\frac{W{\mu }_n{C}_{OX}}{2L}}\left(V_{GS}-V_T\right),$$

(8)

where I_D(sat) is drain current in the saturation region, W is the total channel width, L is the channel length, and C_OX is the gate oxide capacitance. Since Figure 4 depicts that the sample-to-sample variations were acceptable, a single device was randomly selected to perform extraction for each bias condition.

Table 2. Extracted parameters for device pre-irradiation.

	Unit	Virgin		150 krad(Si)		Anneal
		Gate Bias	Drain Bias	Gate Bias	Drain Bias	Gate Bias	Drain Bias
VT	V	3.75	3.82	3.61	3.68	3.88	3.66
Vot	V	0.96	0.99	0.45	0.30	0.68	0.69
µn	cm2/V·s	319.34	339.00	273.30	252.45	219.05	279.15
ΔVT	V	0.00	0.00	−0.14	−0.14	0.13	−0.15
ΔVot	V	0.00	0.00	−0.51	−0.69	−0.28	−0.30
ΔVit	V	0.00	0.00	0.37	0.55	0.41	0.14
ΔNot	cm−2	0.00	0.00	1.37 × 1011	1.86 × 1011	0.76 × 1011	0.80 × 1011
ΔNit	cm−2	0.00	0.00	1.00 × 1011	1.48 × 1011	1.11 × 1011	0.39 × 1011
Δµn	cm2/V·s	0.00	0.00	−46.05	−86.85	−100.29	−59.85

presents the extracted parameters of the device pre-irradiation, at 150 krad(Si) irradiation, and after annealing.

The TID-induced oxide-charge density was 1.86 × 10¹¹ cm⁻² for the drain bias condition, whereby such oxide charges should lead to a −0.69 V V_T shift. However, the negative shift was partially compensated by an interface-trap-induced positive shift, resulting in a net shift of −0.14 V. For the GB, both ΔN_ot and ΔN_it were 30% less than those for the DB. During the annealing process, almost half the generated oxide charges were reduced for both bias conditions. Nevertheless, the annealing behaviors of N_it for both conditions were different; N_it increased by approximately 10% for the GB and reduced by roughly 75% for the DB. Such similarity between N_it and I_dss during the annealing stage indicates that the increasing trend for I_dss might be related to the generation of interface traps. Moreover, as expected, the N_it generation and annealing was qualitatively consistent with the extracted mobility value [32]. The data in Table 2 can be used to calculate Y_pσ_p and σ_h, as a starting point in the device design. However, these parameters are highly process-dependent and are, therefore, only valid for this specific process flow.

The parameter selection was further evaluated through fabrication of devices with t_OX = 100 nm, which were later subjected to TID experiments. For the other geometric parameters, the process flow and TID experiment setups were kept the same as those for the 80 nm samples. However, note that the oxidation time for the 100 nm samples was longer; thus, worse TID hardness could be expected because of the larger thermal budget and thicker t_OX, as illustrated in Figure 5. Here, the bias condition was the same as the gate bias condition described in Section 3. Much larger negative shifts and significant twists in the figure indicate both oxide charges and interface traps being much more in the 100 nm oxide thickness. Figure 6 illustrates the V_T shifts under the two bias conditions after 100 krad irradiation and annealing, where the shifts were higher with thicker t_OX, thus reflecting better SEGR hardness. A comparison of SEGR hardness of these devices is a future direction relative to the present study.

5. Conclusions

A rad-hard power MOSFET is appropriately designed through consideration of several radiation effects as TID, SEB, and SEGR, as well as a balance among electrical parameters as R_on, V_th and BV_ds. In this work, the effects of cell structure adjustment on the performance of a power MOSFET were examined, by first analyzing the design parameters. Next, a SEE- and TID-hardened power MOSFET was designed and fabricated by implementing the accompanying design rules. Results of the investigation confirmed the achievement of excellent radiation hardness and decent specific on-resistance for the device. Technically, the V_th shifts were less than 0.25 V for 150 krad(Si) irradiation and 168 h annealing. No SEE was observed under V_GS = 0 V and the V_DS = 100 V bias condition with LET = 66 MeV·cm²/mg under Xe ion irradiation. Further investigation on the TID experimental results indicated the estimated charge density induced by radiation and annealing. Moreover, devices with thicker gate oxide were fabricated as the counterpart for the parameter selection evaluation. Experiments with these devices showcased their great potential for application in space power systems.

As a general rule, radiation environments are different for various mission orbits. Notably, a spacecraft in van-Allen belts would suffer more from a TID effect, whereas a deep space mission would require high SEE-hardness devices. Additionally, devices in low-Earth orbits requires lower radiation hardness while they are expected to exhibit better electrical parameters. Hence, various devices with different electrical parameters and radiation hardness are required for different missions. The results in the present study provide an insight for the power semiconductor designer to balance the parameters involved and to design power MOSFET devices based on the application requirements.