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Article

Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches

Computer College, National University of Defense Technology, Changsha 410073, China
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Author to whom correspondence should be addressed.
Electronics 2019, 8(9), 950; https://doi.org/10.3390/electronics8090950
Submission received: 4 August 2019 / Revised: 21 August 2019 / Accepted: 25 August 2019 / Published: 28 August 2019
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)

Abstract

The southbound protocol of Software Defined Networking (SDN) enables the direct access into SDN switches which accelerates the innovation and deployment of network functions in the data plane. Correspondingly, SDN switches that support the new southbound protocol and provide high performance are developed continuously. Therefore, there is an increasing need for testing tools to test such equipment in terms of protocol correctness and performance. However, existing tools have deficiencies in flexibility for verifying the novel southbound protocol, time synchronization between the two planes, and supporting more testing functions with less resource consumption. In this paper, we present the concept of CPU & FPGA co-design Tester (CFT) for SDN switches, which provides flexible APIs for test cases of the control plane and high performance for testing functions in the data plane. We put forward an efficient scheduling algorithm to integrate the control plane and the data plane into a single pipeline which fundamentally solves the time asynchronization between these two planes. Due to the reconfigurable feature of our proposed pipeline, it becomes possible to perform different testing functions in one pipeline. Through a prototype implementation and evaluation, we reveal that the proposed CFT can verify the protocol correctness of SDN switches on the control plane while providing no-worse performance for tests on the data plane compared with commercial testers.
Keywords: SDN switch; testing tool; CPU & FPGA co-design; reconfigurable pipeline SDN switch; testing tool; CPU & FPGA co-design; reconfigurable pipeline

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MDPI and ACS Style

Jiang, Y.; Chen, H.; Yang, X.; Sun, Z.; Quan, W. Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches. Electronics 2019, 8, 950. https://doi.org/10.3390/electronics8090950

AMA Style

Jiang Y, Chen H, Yang X, Sun Z, Quan W. Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches. Electronics. 2019; 8(9):950. https://doi.org/10.3390/electronics8090950

Chicago/Turabian Style

Jiang, Yue, Hongyi Chen, Xiangrui Yang, Zhigang Sun, and Wei Quan. 2019. "Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches" Electronics 8, no. 9: 950. https://doi.org/10.3390/electronics8090950

APA Style

Jiang, Y., Chen, H., Yang, X., Sun, Z., & Quan, W. (2019). Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches. Electronics, 8(9), 950. https://doi.org/10.3390/electronics8090950

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