Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches
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Jiang, Y.; Chen, H.; Yang, X.; Sun, Z.; Quan, W. Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches. Electronics 2019, 8, 950. https://doi.org/10.3390/electronics8090950
Jiang Y, Chen H, Yang X, Sun Z, Quan W. Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches. Electronics. 2019; 8(9):950. https://doi.org/10.3390/electronics8090950
Chicago/Turabian StyleJiang, Yue, Hongyi Chen, Xiangrui Yang, Zhigang Sun, and Wei Quan. 2019. "Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches" Electronics 8, no. 9: 950. https://doi.org/10.3390/electronics8090950
APA StyleJiang, Y., Chen, H., Yang, X., Sun, Z., & Quan, W. (2019). Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches. Electronics, 8(9), 950. https://doi.org/10.3390/electronics8090950