A Novel Offset and Finite-Gain Compensated Switched-Capacitor Amplifier with Input Correlated Level Shifting

Abstract

A novel offset and finite-gain compensated differential switched-capacitor(SC) amplifier is presented. Incorporating the correlated double sampling (CDS) technique and input correlated level shifting (CLS) technique together, the DC offset and DC gain error of SC amplifier are further reduced by a factor of op-amp DC gain compared with the conventional offset and finite-gain compensated SC amplifier. The effectiveness of the new scheme has been analyzed and verified by extensive simulations. An SC amplifier with the proposed scheme is designed in 130 nm CMOS technology. Simulated results show that with an op-amp having a low DC gain of 30 dB and an input offset of 10 mV, the proposed SC amplifier achieves an output offset and DC-gain error of 154 µV and 0.05%, respectively, which are significantly improved compared with 1.155 mV and 0.42% achieved in the conventional SC amplifier.

1. Introduction

The switched-capacitor (SC) amplifier is widely used in various low-power, high-precision analog circuits, such as sample-and-hold circuits [1,2], instrumentation amplifiers for intelligent sensors in strain, pressure and temperature measurement [3], micro-electromechanical systems (MEMS) capacitive accelerometers [4], multi-parameter sensing micro-systems [5], and readout amplifiers for biomedical signal acquisition systems [6,7,8]. Those amplifiers should have a very low DC offset and DC gain error as the output signals detected by the sensors are low-frequency and low-level. Nevertheless, the performance of an SC amplifier is limited by several non-ideal effects, among which the finite DC gain of the op-amp is the most important one, which affects the amplifier’s output DC offset and gain error more seriously than other factors.

Temes, Martin, and Haug [9,10] proposed offset and finite-gain compensated SC amplifiers for low-frequency inputs in both single-ended and differential architectures. With the correlated double sampling (CDS) switching of the input capacitor and an output capacitor, the DC gain error is reduced and proportional to A⁻², and the output DC offset is reduced by a factor of A, where A is the DC gain of the op-amp. Therefore, the DC offset and DC gain error can only be further reduced by increasing the DC gain of the op-amp, which presents a difficulty for designing low-power, highly accurate analog circuits, especially at a low supply voltage for IoT and portable applications.

Recently, several techniques have been developed to alleviate the finite gain error of op-amps in SC circuits, such as comparator-based SC (CBSC) circuits [11,12], digital circuits-based SC circuits, which are also called zero-crossing-detectors-based (ZCD) SC circuits [13,14,15] and digital calibration algorithms [16,17,18]. However, CBSC circuits introduce large offset errors and linearity problems due to the output overshoots and voltage drop on switches [19]. Furthermore, these digital techniques are more complicated than switched-capacitor techniques, which have been proposed to increase the effective gain of op-amps, such as correlated level shifting (CLS) [20], cross-coupling CLS [21], sequential-CLS [22], charge-compensated CLS [23], and averaging-CLS [24]. The CLS technique has gained popularity in pipelined ADCs to reduce the gain error of residue amplifiers [20,21,24,25,26] and in inverter-based delta-sigma modulator to enhance the DC gain of the first stage integrator [27]. However, those CLS techniques are applied to the output of the op-amps, one CLS operation only makes the DC gain error proportional to A⁻² [20,27], while two CLS operations make the DC gain error proportional to A⁻³ [25] at the expense of increased current consumption for accurate settling within a reduced settling time. Moreover, the CLS technique does not remove offset when applied to the output of op-amp [20,21], unlike the CDS technique does [10,28,29].

Therefore, we propose a novel scheme combing the CDS technique and input CLS technique for SC amplifier to enhance the accuracy as well as to further reduce the offset even with low op-amp gain. Note that the concept of using CDS in combination with input CLS is first introduced in this paper. Unlike the concept of combining the chopper stabilization (CS) and output CLS techniques proposed in [30], the input CLS technique helps to reduce the DC offset as well as the DC gain error. It is based on the fact that reducing the amount of residue charge on the input capacitor helps the SC amplifier make a complete charge transfer from the input capacitor to the output capacitor. The rest of the paper is organized as follows. In Section 2, the conventional SC amplifier with CDS method is reviewed and the proposed input CLS-based SC amplifier structure is detailed and analyzed. The effectiveness of the new scheme has been analyzed and verified by extensive behavioral simulations compared with the conventional design of [10]. In Section 3, implementation details of the building block circuits are presented and simulation results are discussed as well. Section 4 draws the conclusions.

2. Input CLS-Based Switched-Capacitor Amplifier

2.1. Conventional CDS-Based SCAmplifier

Figure 1 shows the operation of the well-known differential SC amplifier [10]. Φ₁ and Φ₂ are two non-overlapping clock phases, while Φ₁ and Φ₂ cut off earlier than Φ_1d and Φ_2d respectively. During Φ₁, the differential input signals, as well as the offset and flicker noise, are sampled onto C₁, while the output voltage only changes by the op-amp input offset. During Φ₂, the charge is transferred from C₁ to C₂ through the feedback loop formed by C₂ and the op-amp.

According to [31], the transfer function of this amplifier at low frequency and DC output offset are given by the following Equations (1) and (2):

$$V_O\left(n\right)=\frac{\left(\frac{C_1}{C_2}\right)\times V_{IN}\left(n-\frac{1}{2}\right)}{1+\frac{\left(1+\frac{C_1}{C_2}\right)}{A^2}}$$

(1)

$$V_O=\frac{\left(1+\frac{C_1}{C_2}\right)\times V_{OS}}{\left(A+1\right)+\frac{\left(1+\frac{C_1}{C_2}\right)}{A}}$$

(2)

where $V_{IN}=V_{INP}-V_{INN}$, $V_{OS}$ is input referred offset of op-amp, A is the DC gain of op-amp. However, due to its finite DC gain, the op-amp sees a difference of $V_O/A$ between its input terminals, which results in a DC gain error and a DC offset of the SC amplifier to be proportional to A⁻² and A⁻¹, respectively.

2.2. Input CLS-Based Offset and Finite-Gain Compensated SC Amplifier

Figure 2a shows the schematic of the proposed SC amplifier. There are two main non-overlapping phases Φ₁ (sample) and Φ₂ (amplification). The phase Φ₂ is divided into two sub-phases: Φ₂₁ and Φ₂₂, during which the CDS operation and CLS operation occur, respectively, as shown in Figure 2b. During Φ₁, the input signal is sampled by C₁, while the offset is stored on C_OS. During Φ₂₁, the amplifier enters the CDS amplification phase. The charge is transferred from C₁ to C₂ with offset and DC gain error nearly the same as the conventional design, while the offset and the finite-gain induced error at the op-amp’s input are stored on C_CLS, whose bottom plate is connected to V_CM. During Φ₂₂, the bottom plate of C_CLS that is connected to the node X is shifting towards V_CM (virtual ground) by charge conservation of C_CLS. Therefore, the residue charge stored on C₁ is reduced from $C_1\times V_O/A$ to $C_1\times [V_O{}^{22}\left(n\right)-V_O{}^{21}\left(n\right)]/A$, where $V_O^{21}$ and $V_O^{22}$ are the output voltage in phase Φ₂₁ and Φ₂₂, respectively, and n is the discrete time index. Consequently, the charge transfer from C₁ to C₂ is more complete than the conventional technique in [10].

Figure 3 shows the detailed sample, CDS operation and CLS operation steps during phase Φ₁, Φ₂₁ and Φ₂₂, respectively. Here the even clock period n − i (i = 0, 1, 2, ...) corresponds to the Φ₂ phase and the odd clock period n – i/2 (i = 1, 3, 5, ...) corresponds to the Φ₁ phase. Figure 3a shows the sample step during Φ₁ at clock period n − 1/2, input signal $V_{IN}\left(n-1/2\right)$ is sampled by C₁ and C₂ is discharged, the charge stored at C_CLS is $C_{CLS}\times V_O{}^{21}\left(n-1\right)/A$. Considering the finite DC gain of op-amp, and node X and Y are treated as super nodes, as shown in Figure 3b, the following Equations (3) and (4) can be derived according to nodal charge analysis to show the voltage relations of the circuit at the end of Φ₂₁ within clock period n.

$$C_1\times V_{\mathrm{IN}}\left(n-\frac{1}{2}\right)-C_{OS}\times \frac{V_O{}^1\left(n-\frac{1}{2}\right)}{A}=C_1\times \left[-V_X{}^{21}\left(n\right)\right]+C_2\times \left[V_O{}^{21}\left(n\right)-V_X{}^{21}\left(n\right)\left]+C_{\mathrm{OS}}\times \right[-\frac{V_O{}^{21}\left(n\right)}{A}-V_X{}^{21}\left(n\right)\right].$$

(3)

$$C_{CLS}\times \left[\frac{V_O{}^{21}\left(n\right)}{A}-\frac{V_O{}^{21}\left(n-1\right)}{A}\left]=C_{OS}\times \right[-\frac{V_O{}^{21}\left(n\right)}{A}-V_X{}^{21}\left(n\right)+\frac{V_O{}^1\left(n-\frac{1}{2}\right)}{A}\right]$$

(4)

where $V_X^{21}$ represents the voltage of node X in phase Φ₂₁, and $V_O^1$ represents the output voltage in phase Φ₁.

At the beginning of phase Φ₂₂, the bottom plate of C_CLS is connected to node X as shown in Figure 3c, the correlated level shifting operation occurs, and the voltage relations of the circuit at the end of Φ₂₂ can be obtained by charge conservation of C_CLS and nodal charge analysis as Equations (5) and (6) shown below:

$$-C_1\times V_X{}^{21}\left(n\right)+C_2\times \left[V_O{}^{21}\left(n\right)-V_X{}^{21}\left(n\right)\right]=-C_1\times V_X{}^{22}\left(n\right)+C_2\times \left[V_O{}^{22}\left(n\right)-V_X{}^{22}\left(n\right)\right]$$

(5)

$$C_{\mathrm{CLS}}\times \left[-\frac{V_O{}^{22}\left(n\right)}{A}-V_X{}^{22}\left(n\right)\right]=-C_{\mathrm{CLS}}\times \frac{V_O{}^{21}\left(n\right)}{A}$$

(6)

where $V_X^{22}$ and $V_O^{22}$ represent the voltage of node X and the output voltage in phase Φ₂₂ respectively.

According to Equations (3)–(6), we can derive the following Equation (7):

$$C_1\times V_{IN}\left(n-\frac{1}{2}\right)=C_{CLS}\times \frac{V_O{}^{21}\left(n\right)-V_O{}^{21}\left(n-1\right)}{A}+\left(C_1+C_2\right)\times \frac{V_O{}^{22}\left(n\right)-V_O{}^{21}\left(n\right)}{A}+C_2\times V_O{}^{22}\left(n\right)$$

(7)

For low frequency especially DC input, $V_O{}^{21}\left(n\right)=V_O{}^{21}\left(n-1\right)$ when output voltage arrives its final value, then Equation (4) and Equation (7) can be simplified to the following Equations (8) and (9):

$$V_X{}^{21}\left(n\right)=-\frac{V_O{}^{21}\left(n\right)}{A}+\frac{V_O{}^1\left(n-\frac{1}{2}\right)}{A}$$

(8)

$$V_O{}^{22}\left(n\right)=\frac{C_1}{C_2}\times V_{IN}\left(n-\frac{1}{2}\right)-\frac{C_1+C_2}{C_2}\times \frac{V_O{}^{22}\left(n\right)-V_O{}^{21}\left(n\right)}{A}$$

(9)

Obviously seen from Equation (9), the gain error is proportional to the correlated output voltage differences at the end of phase Φ₂₂ and Φ₂₁.

As shown in Figure 3d, node Y is treated as super node, then charge conservation in this super node implies the following Equation (10) during Φ₁ at clock period n + 1/2.

$$C_{OS}\times \left[V_X{}^{21}\left(n\right)+\frac{V_O{}^{21}\left(n\right)}{A}\right]+C_3\times V_O{}^{22}\left(n\right)=C_{OS}\times \frac{V_O{}^1\left(n+\frac{1}{2}\right)}{A}+C_3\times [V_O{}^1\left(n+\frac{1}{2}\right)+\frac{V_O{}^1\left(n+\frac{1}{2}\right)}{A}]$$

(10)

Choosing $C_{OS}=C_3$, Equation (10) can be simplified as Equation (11):

$$V_O{}^1\left(n+\frac{1}{2}\right)\times \left(\frac{2}{A}+1\right)=\frac{V_O{}^{21}\left(n\right)}{A}+V_O{}^{22}\left(n\right)+V_X{}^{21}\left(n\right)$$

(11)

For DC input, $V_O{}^1\left(n+\frac{1}{2}\right)=V_O{}^1\left(n-\frac{1}{2}\right)$ when the output voltage reaches the final value. Therefore by substituting Equation (8) into Equation (11), and Equation (4) into Equation (3), the following Equations (12) and (13) are obtained:

$$V_O{}^1\left(n-\frac{1}{2}\right)=\frac{V_O{}^{22}\left(n\right)}{1+\frac{1}{A}}$$

(12)

$$C_1\times V_{IN}\left(n-\frac{1}{2}\right)+\left(C_1+C_2\right)\times \frac{V_O{}^1\left(n-\frac{1}{2}\right)}{A}=[\frac{C_1+C_2}{A}+C_2]\times V_O{}^{21}\left(n\right)$$

(13)

Finally, the transfer function of this amplifier at low frequency can be given by the following Equation (14), according to Equation (9), Equation (12) and Equation (13).

$$V_O{}^{22}\left(n\right)=\frac{\left(\frac{ C_{1 }}{C_2}\right)\times V_{IN}\left(n-\frac{1}{2}\right)}{1+\frac{{\left(C_1+C_2\right)}^2}{A\left(A+1\right)\left[C_2{}^2\left(A+2\right)+2C_1\times C_2\right]}}$$

(14)

Seen from the denominator of Equation (14), the DC gain error becomes proportional to A⁻³ rather than A⁻².

Besides reducing the DC gain error caused by the finite DC gain of the op-amp, the proposed scheme can also reduce the DC offset significantly. Similar to the above DC gain error analysis, the output DC offset can also be determined by the same method. Considering the input referred offset of the op-amp V_OS as shown in Figure 4, the following Equations (15)–(18) can be derived according to nodal charge analysis and charge conservation of C_CLS to show the voltage relations of the circuit at the end of phase Φ₂₁, Φ₂₂ and Φ₁.

$$C_{OS}\times \left[\frac{V_O{}^1\left(n-\frac{1}{2}\right)}{-A}+V_{OS}\right]=C_1\times \left[-V_X{}^{21}\left(n\right)\right]+C_2\times \left[V_O{}^{21}\left(n\right)-V_X{}^{21}\left(n\right)\right]+C_{OS}\times \left[-\frac{V_O{}^{21}\left(n\right)}{A}+V_{OS}-V_X{}^{21}\left(n\right)\right]$$

(15)

$$C_{CLS}\times \left[\frac{V_O{}^{21}\left(n\right)}{A}-\frac{V_O{}^{21}\left(n-1\right)}{A}\left]=C_{OS}\times \right[-\frac{V_O{}^{21}\left(n\right)}{A}+V_{OS}-V_X{}^{21}\left(n\right)+\frac{V_O{}^1\left(n-\frac{1}{2}\right)}{A}-V_{OS}\right]$$

(16)

$$C_{CLS}\times \left[-\frac{V_O{}^{22}\left(n\right)}{A}+V_{OS}-V_X{}^{22}\left(n\right)\left]=C_{CLS}\times \right[-\frac{V_O{}^{21}\left(n\right)}{A}+V_{OS}\right]$$

(17)

$$C_{OS}\times \left[V_X{}^{21}\left(n\right)+\frac{V_O{}^{21}\left(n\right)}{A}-V_{OS}\right]+C_3\times V_O{}^{22}\left(n\right)=C_{OS}\times \left[\frac{V_O{}^1\left(n+\frac{1}{2}\right)}{A}-V_{OS}\right]+C_3\times [V_O{}^1\left(n+\frac{1}{2}\right)+\frac{V_O{}^1\left(n+\frac{1}{2}\right)}{A}-V_{OS}]$$

(18)

Note that Equation (5) is still effective at the end of phase Φ₂₂ for DC offset analysis. Choosing $C_{OS}=C_3$, Equation (18) can be simplified as Equation (19):

$$V_O{}^1\left(n+\frac{1}{2}\right)\times \left(\frac{2}{A}+1\right)=\frac{V_O{}^{21}\left(n\right)}{A}+V_O{}^{22}\left(n\right)+V_X{}^{21}\left(n\right)+V_{OS}$$

(19)

For DC offset analysis, $V_O{}^{21}\left(n\right)=V_O{}^{21}\left(n-1\right)$, $V_O{}^1\left(n+\frac{1}{2}\right)=V_O{}^1\left(n-\frac{1}{2}\right)$ when the output voltage reaches its final value. Therefore according to Equation (5), Equations (15)–(17), and Equation (19), we can obtain the following simplified Equations (20)–(22):

$$V_O{}^{22}\left(n\right)=\frac{C_1+C_2}{C_2}\times \frac{V_O{}^{21}\left(n\right)-V_O{}^{22}\left(n\right)}{A}$$

(20)

$$\left(C_1+C_2\right)\times \frac{V_O{}^1\left(n-\frac{1}{2}\right)}{A}=[\frac{C_1+C_2}{A}+C_2]\times V_O{}^{21}\left(n\right)$$

(21)

$$V_O{}^1\left(n-\frac{1}{2}\right)=\frac{V_O{}^{22}\left(n\right)+V_{OS}}{1+\frac{1}{A}}$$

(22)

Thus the output DC offset can be deduced from Equations (20)–(22) and is given by Equation (23):

$$V_O{}^{22}=\frac{\left(\frac{ C_1+C_2}{1+A}\right)\times V_{OS}}{\frac{ C_1+C_2}{A\left(A+1\right)}+2C_2+\frac{A{C}_2{}^2}{ C_1+C_2}}$$

(23)

According to Equation (23), the output DC offset of SC amplifier is approximately ${\left(1+C_1/C_2\right)}^2\left[V_{OS}/(A^2+A\right)]$, which is proportional to A⁻² but not A⁻¹.

From the above analysis, the proposed scheme for SC amplifier reduces the output DC offset and DC gain error each to $\left(1+C_1/C_2\right)/A$ times of those in the conventional design in [10].

The proposed SC amplifier can also be implemented in differential architecture as shown in Figure 5. The transfer function of this amplifier at low frequency and output DC offset are the same as Equation (14) and Equation (23), respectively, where $V_{IN}=V_{INP}-V_{INN}$, $V_O^{22}=V_{OP}^{22}-V_{ON}^{22}$, $V_{OP}^{22}$ and $V_{ON}^{22}$ are the output differential signals in phase Φ₂₂.

2.3. Simulation Results

The normalized gain error as a function of frequency is plotted in Figure 6, which compares with the gain error of the conventional SC amplifier for nominal gains of unity, three and nine respectively in behavioral simulation by using block-level models in Cadence Spectre. Both of the two SC amplifiers are in differential architecture. The switches and op-amp are both using behavioral models. The op-amp is assumed to have 30 dB DC gain. As the curves illustrate, the DC gain error of the proposed design is smaller than the conventional one and the improvement is substantial for higher nominal gain cases. It can also be seen that the frequency responses of the proposed design are superior to the conventional one, e.g., the gain error of the new design is smaller than 1.2 dB for frequency up to f_s/4, where f_s is sampling frequency, while that of the conventional design is 5.3 dB, for a nominal gain of nine.

To verify the above analysis, circuit-level behavioral simulations were conducted on the conventional and proposed SC amplifier respectively. Both of the them are in differential architecture. Figure 7 shows the power spectrums of the proposed and conventional designs for a 2.246 kHz sinusoidal input signal (V_IN = 20 mV_pp,diff) with a nominal gain of three ($C_1/C_2=3)$, where the op-amp gain and input referred offset are assumed to be 30 dB and 10 mV, respectively. The theoretical output DC offset of the conventional and proposed designs are 1.2599 mV and 0.1237 mV, respectively, according to Equation (2) and Equation (23). The theoretical DC gain of conventional and proposed designs are 2.9880 (9.508 dB) and 2.9988 (9.538 dB), respectively, according to Equation (1) and Equation (14), which indicates the DC gain error is improved from 0.4% to 0.04%. It can be seen from the power spectrum curves that the output DC offset of the proposed design is around 20 dB lower than the conventional design, and the DC gain is improved from 9.51 dB to 9.54 dB for nominal gain of 3 (9.542 dB), which are in accordance with the theoretical analysis.

3. Circuit Implementation

To verify the effectiveness of the proposed scheme, the SC amplifier of Figure 5 is implemented in 130 nm CMOS triple-well process with metal-insulator-metal (MIM) capacitors and high-resistivity poly resistors. The conventional SC amplifier of Figure 1 is also realized for comparison. The switches are realized by NMOS transistors (W/L = 10 µm/0.12 µm). The capacitor sizes used in Figure 1 are $C_1=2.4 pF$, $C_2=0.8 pF$, while the capacitor sizes used in Figure 5 are $C_1=2.4 pF$, $C_2=0.8 pF$, $C_3=C_{OS}=0.8 pF$, $C_{CLS}=0.8 pF$ for a nominal gain of 3.

Figure 8 shows the schematic of the op-amp used in both SC amplifiers. It is a standard fully differential single-stage op-amp. The simulation results show that the amplifier achieves a 30.3 dB open-loop DC gain, 33 MHz UGF, and phase margin of 90° with 1.6 Pf load capacitor.

Figure 9 shows the clock generation circuit for generating the seven clock phases: two non-overlapping clock phases Φ₁ and Φ₂, two delayed clock phases Φ_1d and Φ_2d for charge injection elimination, Φ₃ and sub-phase Φ₂₁ for CDS amplification, sub-phase Φ₂₂ for input correlated level shifting. The simulated non-overlapping time of Φ₁ and Φ₂ is 4 ns, and the non-overlapping time of Φ₂₁ and Φ₂₂ is 2 ns. Although the op-amp in Figure 5 is left open-loop during those non-overlapping intervals, the glitches appear at the output of op-amp at the clock transitions are eliminated due to the fully differential amplifier architecture. Note that the proposed SC amplifier requires more complicated timing schemes compared with the conventional one, which may lead to an increase of power consumption. However, the power consumption of the clock generator is around 1.67 µA for input CLK frequency of 800 kHz by transistor-level simulation. Hence, a further reduction of the power consumption of the clock generator can be achieved by optimizing the size of the logic cell. Furthermore, the maximum clock frequency is reduced compared with the conventional one. However, the proposed SC amplifier is aimed for low-frequency and low-level signal detection. Therefore, the effect of the reduced maximum sampling frequency is small.

Figure 10 shows the simulated output waveforms of the proposed and conventional designs with a nominal gain of 3. The supply voltage V_DD is 1.2 V and the V_CM is 0.6 V. The clock signal CLK is at 800 kHz for generating 400 kHz clock signals of Φ₁, Φ₂, Φ₃, Φ_1d, and Φ_2d, 800 kHz clock signals of Φ₂₁ and Φ₂₂. For output DC offset simulation, a voltage source of 10 mV is inserted at the inverting input terminal of the op-amp. It can be seen from Figure 10a that the output DC offset of the proposed design is 154 µV during Φ₂₂, which is further reduced by a factor of 7.5 compared with the conventional design of 1.155 mV during Φ₂. The Figure 10b shows the output waveforms for 2.246 kHz, 20 mV_pp,diff sinusoidal input signal. The conventional SC amplifier output is 59.75 mV, while that of the proposed SC amplifier is 59.97 mV, much closer to the ideal output of 60 mV. Hence, the simulated DC gain error of the proposed design is 0.05%, which is significantly improved by a factor of 8.4 compared with the conventional design of 0.42%. Seen from the above simulation results, the output DC offset and DC gain error improvements of the proposed design are close to the theoretical value of $A/\left(1+C_1/C_2\right)$ compared with the conventional design.

A specification summary of simulation results are given in

Table 1. Simulation results and comparison of SC amplifier.

Parameters	This Work	Conventional Design [10]
DC gain error	0.05%	0.42%
Output DC offset	154 µV	1.155 mV
DC gain of op-amp	30 dB	30 dB
Nominal gain of SC amplifier	3	3
Input offset of op-amp	10 mV	10 mV
Supply voltage	1.2 V	1.2 V
Number of Switches	22	12

. The results show that the proposed SC amplifier achieves an output offset and DC-gain error of 154 µV and 0.05%, respectively with an op-amp of 30 dB DC gain and 10 mV input offset, which are significantly improved compared with the 1.155 mV and 0.42% achieved in the conventional SC amplifier. It can be also seen from Table 1 that the number of switches of the proposed SC amplifier is more than the conventional one, which may increase the layout area. However, this can be alleviated by optimizing the switches size.

Table 2. With other reported SC amplifiers.

Paper	Type	Output DC Offset	DC Gain Error
[10]	CDS	$V_{OS}\times \left(1+C_1/C_2\right)/\mathrm{A}$	$\left(1+C_1/C_2\right)/{\mathrm{A}}^2$
[20]	CLS	$V_{OS}$	$1/{\left(A\beta \right)}^2$*
[25]	2×CLS	$V_{OS}$	$1/{\left(A\beta \right)}^3$*
[22]	3×CLS	$V_{OS}$	$1/{\left(A\beta \right)}^4$*
This work	CDS+ Input CLS	$V_{OS}\times {\left(1+C_1/C_2\right)}^2/A^2$	${\left(1+C_1/C_2\right)}^2/{\mathrm{A}}^3$

^*β is the feedback factor (β < 1) and Aβ is the loop gain of SC amplifier used in MDACs or S/H circuit.

shows the comparison results with other reported SC amplifiers based on theoretical analysis. It can be easily found that the proposed SC amplifier achieves excellent performance in both output the DC offset and DC gain error.

4. Conclusions

A novel offset and finite-gain compensation scheme that combines the CDS technique and the input CLS technique for SC amplifiers has been presented. The DC offset and DC gain error of the proposed design are proportional to A⁻² and A⁻³, respectively, which are 1/A of those in the conventional SC amplifier of [10]. Compared with the CLS technique applied to the output of the op-amp, the proposed compensation scheme achieves a better performance in the output DC offset cancellation.

The effectiveness of the proposed design has been verified through the circuit level simulations by using a 130 nm CMOS process. The simulation results are in good agreement with the transfer function-based analysis.