Modified Topology for Three-Phase Multilevel Inverters Based on a Developed H-Bridge Inverter

Abstract

This paper proposes a modified three-phase inverter from the developed H-bridge structure having multilevel functionality. The proposed topology can generate 7-levels of phase voltages and 13-levels of line voltages. Simple control methods such as fundamental frequency control method can be applied to the proposed topology. By adding three single-phase transformers, galvanic isolation is created for use in three-phase Dynamic Voltage Restorer systems. The proposed three-phase inverter utilizes less number of components; dc sources, semiconductor switches and driver circuits. Lower rated power switches with reduced blocking voltages are also used. These attributes make the proposed topology less complex in-terms of architecture and control. Comprehensive analysis of the proposed three-phase multilevel inverter and other presented topologies are investigated with respect to levels of output voltage, driver circuit quantity, dc voltage count, total component quantity and standing voltage. Details of the appropriate control technique employed is explained. Finally, practicability of the proposed inverter is validated by simulation using EMTDC/PSCAD software and experimental prototype.

1. Introduction

Multilevel inverters (MLIs) have been in existence for well over three decades now and continue to receive maximum attention from researchers in industry and academia because they are regarded as being more advantageous when compared to their conventional predecessors the two-level inverters [1]. These advantages are minimum switching losses, reduced harmonic content, minimum electromagnetic interference, application of lower rated switches, decreased voltage stress on switches, high quality output waveform, medium and high power compatibility and high efficiency [2,3]. Multilevel inverters are well suited for application in renewable energy systems, electric drives, hybrid electric vehicles, flexible alternating current transmission systems (FACTS) [4,5], dynamic voltage restorers (DVRs), reactive power compensation and high voltage direct current (HVDC) [6]. The majority of these applications require three-phase multilevel inverters for medium to high power system applications. Multilevel inverters are generally categorized into three topologies: cascaded H-bridge (CHB) MLI, diode clamped (DC) MLI and the flying capacitor (FC) MLI. Other topologies of multilevel inverters are modular MLI [7] and hybrid MLI topologies.

Current trends in multilevel inverter development seek to maximize the efficiency of the various MLI topologies by improving the topological structures as well as the control techniques. Minimizing the component count, especially power switches and DC sources [8,9,10] while increasing the stepped output voltages are critical features of any improved MLI topology. A hybrid clamped ML inverter is presented by the authors in [11]; this topology offers a minimum component count when compared to similar converters, the structure is mainly composed of 24 switches, one DC source and six capacitors. It also offers better performance and minimum converter cost. A single DC source 7-level inverter is presented in [12], where the component count for each phase are 12 switches, one DC source and three capacitors. This topology is derived from the combination of T-type and active neutral point clamped (NPC) converters. A novel active NPC 7-level inverter is presented in [13]; the basic unit of each phase is composed of 18 switches, four capacitors and one DC source, which translates to a high component count in the three-phase structure. A three-phase cascaded symmetric MLI having a reduced DC source count is presented in [14]. Two DC sources are required for the entire three-phase while each phase is composed of one full-HB and two half-HB, galvanic isolation is provided by a three-phase transformer, minimum component count is achieved with this topology however, the stepped output voltage is 5-levels. Addition of a half HB to each phase will produce 7-levels of output voltage.

A hybrid controlled cascaded MLI is presented in [15] which utilizes the subtraction and addition of sources method to achieve multilevel functionality. Only positive polarity is generated with this method, and a HB topology is required to generate both polarities of voltage. The presented three-phase topology has 10 switches and two DC sources for each phase. Amalgamation of a T-type and a HB structure produces a cascaded MLI. This topology is suitable for high power density and low voltage applications. Each phase is composed of eight switches, three capacitors and one DC source [16]. Two MLI converters are presented in [17]; the first converter has one DC source whiles the second converter has three DC sources, the converter structures are similar. Each converter has 14 switches and three capacitors and generates 7-levels. A 7-levels minimum common-mode voltage converter is presented in [18], the structure of which is composed of one DC source, 10 switches and three capacitors for each phase. A new multilevel inverter structure presented by [19] is composed of one three-phase HB and three single-phase HB structures, to obtain increased multilevel functionality, an auxiliary three-phase HB structure is added to the basic unit, so the phase output voltages are not evenly distributed between positive and negative cycles. Without any auxiliary circuit, 18 switches and four DC sources are used to generate 7-levels having one negative voltage component. A 9-levels modular MLI topology is presented in [20]; the hybrid cascaded structure is composed of 24 switches, one DC source and multiple capacitors. A novel NPC converter with minimum component count when compared to other NPC topologies is presented in [21], this topology generates output voltage of 7-levels for a three-phase system. Eight switches and two capacitors constitute the component total in each phase while 24 switches, eight capacitors and one DC source make-up the component total in the three phase system. A novel 7-levels MLI topology is presented in [22], where the component count is 12 unidirectional switches, six bidirectional switches (diode bridge) and six DC sources. A hybrid cascaded three-phase MLI is presented in [23]. The structure is composed of HB and FC topologies utilizing one DC source, 24 switches and five capacitors.

A newly developed three-phase inverter topology having less number of components is proposed in this paper. The proposed topology generates 7-levels of load voltage for each phase and 13-levels of load voltage for line-to-line voltages. The proposed topology only needs a simple control method. Detailed descriptions of the proposed topology with emphasis on component count, blocking voltage, inverter power losses and switching states are provided. To show the advantages of the proposed topology, a comparative investigation of the proposed inverter and other recently presented topologies in terms of switch count, DC-source count, IGBT count and driver circuit count is provided. Finally, simulation and laboratory results are produced to validate the performance of the proposed topology.

2. Proposed Topology

The structure of the proposed three-phase 7-levels inverter is shown by Figure 1. The proposed topology is a further development of the presented structure in [24] which is suitable for single-phase cascaded MLI applications hence the need to develop a topology for three-phase applications. The extension technique is used in developing the three-phase MLI which reduces the dc voltage quantity from six to four. From voltage point of view, the proposed three-phase topology is composed of 18 unidirectional switches and four DC sources. Each phase is made-up of six switches and two isolated DC sources. When compared to other presented topologies, the proposed topology offers the best trade-off between component count and levels of output voltage. In the proposed topology of Figure 1b, by using three single-phase transformers, it is possible to have galvanic isolation between the sources and loads. One application of this topology is in DVR systems to protect the sensitive loads against sag and swell.

Operation of the proposed three-phase inverter is similar to that of a conventional H-Bridge. Diagonally gated switches produce positive or negative output voltages while upper or lower gated switches generate the sum of voltages in each phase. The switching pattern of the proposed three-phase inverter is indicated in

Table 1. Phase Switching Pattern.

State	Switches	VA	Switches	VB	Switches	VC
I	Sa2, Sa3, Sa6	Vdc	Sb2, Sb3, Sa5	Vdc	Sc2, Sc3, Sc6	Vdc
II	Sa1, Sa4, Sa6	2Vdc	Sb1, Sb4, Sa5	2Vdc	Sc1, Sc4, Sc6	2Vdc
III	Sa1, Sa3, Sa6	3 Vdc	Sb2, Sb4, Sa5	3 Vdc	Sc1, Sc3, Sc6	3Vdc
IV	Sa1, Sa3, Sa5 Sa2, Sa4, Sa6	0	Sb1, Sb3, Sa5 Sb2, Sb4, Sa6	0	Sc1, Sc3, Sc5 Sc2, Sc4, Sc6	0
V	Sa1, Sa4, Sa5	−Vdc	Sb1, Sb4, Sa6	−Vdc	Sc4, Sc1, Sc5	−Vdc
VI	Sa2, Sa3, Sa5	−2Vdc	Sb2, Sb3, Sa6	−2Vdc	Sc2, Sc3, Sc5	−2Vdc
VII	Sa2, Sa4, Sa5	−3Vdc	Sb1, Sb3, Sa6	−3Vdc	Sc2, Sc4, Sc5	−3Vdc

. Phase A output voltages are produced when S_a2, S_a3 and S_a6 conducts, positive V_dc output voltage is generated, when S_a1, S_a4 and S_a6 conducts positive 2 V_dc output voltage is generated, when S_a1, S_a3 and S_a6 conducts, positive 3 V_dc output voltage is generated. Similarly, when S_a1, S_a4 and S_a5 conducts, negative V_dc output voltage is generated, when S_a2, S_a3 and S_a5 conducts negative 2 V_dc output voltage is generated, when S_a2, S_a4 and S_a5 conducts, negative 3V_dc output voltage is generated. Zero output voltage is generated by simultaneously gating any of the following group of switches S_a1, S_a3 and S_a5 or S_a2, S_a4 and S_a6. This process is repeated for the other phases to generate the output voltage of the three-phase inverter. The switches utilized in the proposed topology have subscript descriptions to determine the phase they belong to, hence S_a1, S_a2, etc. corresponds to switches in phase A. S_b1, S_b2 etc. corresponds to switches in phase B and S_c1, S_c2 etc. corresponds to switches in phase C. The output voltages for phases A, B and C are given by V_A, V_B and V_C respectively whiles the line-to-line voltages are given by V_AB, V_BC and V_CA. To generate the desired 7-levels of output voltage in each phase, the magnitude of the input dc voltages should vary i.e., V₁ should not equal to V₂ and ${\mathrm{V}}_2\ne {\mathrm{V}}_3,{\mathrm{V}}_3\ne {\mathrm{V}}_4$; if the magnitudes of input dc voltages are equal, 5-levels of output voltage will be generated. Asymmetric feature of the dc sources ensures higher levels of output voltage. Also the polarity connections of the dc sources should be antiparallel or should have a series connection when analyzed from both sides of the converter for each phase. The symmetric characteristics (for the various phases) of the input voltages provides equal conditions for all the phases of the converter. The dc voltage equation is given by:

$$\begin{array}{l}{\mathrm{V}}_2{=\mathrm{V}}_4{=\mathrm{V}}_{\mathrm{dc}}\\ {\mathrm{V}}_1{=\mathrm{V}}_3{=2\mathrm{V}}_{\mathrm{dc}}\end{array}$$

(1)

The proposed topology requires the following component count:

$$\begin{array}{l}{\mathrm{N}}_{\mathrm{switches}}=18\\ {\mathrm{N}}_{\mathrm{Driver}}=18\\ {\mathrm{N}}_{\mathrm{DC}-\mathrm{Source}}=4\\ {\mathrm{N}}_{\mathrm{Level}}=7\end{array}$$

The above listed parameters N_switches, N_Driver, N_DC-Source and N_Level corresponds to switch count, driver circuit count, dc source count and number of levels, respectively.

Considering Figure 1b, the pole voltages at V_AN, V_BN and V_CN are determine from the equations below:

$$\begin{array}{l}{\mathrm{V}}_{\mathrm{AB}}{=\mathrm{V}}_{\mathrm{AN}}{-\mathrm{V}}_{\mathrm{BN}}\\ {\mathrm{V}}_{\mathrm{BC}}{=\mathrm{V}}_{\mathrm{BN}}{-\mathrm{V}}_{\mathrm{CN}}\\ {\mathrm{V}}_{\mathrm{CA}}{=\mathrm{V}}_{\mathrm{CN}}{-\mathrm{V}}_{\mathrm{AN}}\end{array}$$

(2)

According to Figure 1b, it is clear that:

$$\begin{array}{l}{\mathrm{V}}_{\mathrm{AN}}{=\mathrm{V}}_{\mathrm{A}}\\ {\mathrm{V}}_{\mathrm{BN}}{=\mathrm{V}}_{\mathrm{B}}\\ {\mathrm{V}}_{\mathrm{CN}}{=\mathrm{V}}_{\mathrm{C}}\end{array}$$

(3)

Considering the Equations (2) and (3), Equation (2) can be rewritten as follows:

$$\begin{array}{l}{\mathrm{V}}_{\mathrm{AB}}{=\mathrm{V}}_{\mathrm{A}}{-\mathrm{V}}_{\mathrm{B}}\\ {\mathrm{V}}_{\mathrm{BC}}{=\mathrm{V}}_{\mathrm{B}}{-\mathrm{V}}_{\mathrm{C}}\\ {\mathrm{V}}_{\mathrm{CA}}{=\mathrm{V}}_{\mathrm{C}}{-\mathrm{V}}_{\mathrm{A}}\end{array}$$

(4)

The maximum phase output voltages and stepped voltages are given by:

$${\mathrm{V}}_{\mathrm{A}}{= \mathrm{V}}_{\mathrm{B}}{= \mathrm{V}}_{\mathrm{C}}= \pm {3\mathrm{V}}_{\mathrm{dc}} (0, \pm {\mathrm{V}}_{\mathrm{dc}}, \pm {2\mathrm{V}}_{\mathrm{dc}}, \pm {3\mathrm{V}}_{\mathrm{dc}})$$

(5)

The maximum the line to line output stepped voltages are given by:

$${\mathrm{V}}_{\mathrm{AB}}{=\mathrm{V}}_{\mathrm{BC}}{=\mathrm{V}}_{\mathrm{CA}}{=6\mathrm{V}}_{\mathrm{dc}}(0,\pm {\mathrm{V}}_{\mathrm{dc}},\pm {2\mathrm{V}}_{\mathrm{dc}},\pm {3\mathrm{V}}_{\mathrm{dc}},\pm 4_{\mathrm{dc}},\pm {5\mathrm{V}}_{\mathrm{dc}},\pm {6\mathrm{V}}_{\mathrm{dc}})$$

(6)

Power ratings of semiconductor switches is a critical factor which determines the cost of an inverter, operational cost (mostly power losses) and maintenance cost thus it’s desirable to employ lower rated switches to minimize these financial obligations. The blocking voltage of a switch is the maximum magnitude of voltage of either polarity that must be blocked by the switch when opened (not conducting) whiles the sum of the blocked voltages by the various switches employed in an inverter constitutes the standing voltage of the inverter. The Blocking voltage equations for each phase ($1\varphi$) and three-phase ($3\varphi$) of the proposed inverter are given below:

$$\begin{array}{l}{\mathrm{V}}_{1\varphi ,\mathrm{Block}}{=4(\mathrm{V}}_1{+\mathrm{V}}_2)\\ {\mathrm{V}}_{3\varphi ,\mathrm{Block}}{=3\mathrm{V}}_{1\varphi ,\mathrm{Block}}{=12(\mathrm{V}}_1{+\mathrm{V}}_2)\end{array}$$

(7)

2.1. Inverter Losses

The overall power losses of the proposed three-phase inverter topology are determined by three parameters known as switching power losses, blocking voltage power losses and conduction power losses. The blocking voltage power losses can be ignored because off-state currents of semiconductors switches are negligible.

2.1.1. Switching Losses

Switching power losses of semiconductor power switches arise during the states of turn-on and turn-off of each switch. Switching power losses of the proposed multilevel inverter are expressed in terms of lost energy during the period of turn-on and turn-off, therefore let E_on and E_off represent these two states respectively. The total switching energy losses is given by P_SW. V_sw is the switch voltage when off, I and I’ are the switch currents before and after switch turn on and off respectively. t_on and t_off are the turn-on time and turn-off time, respectively:

$${\mathrm{E}}_{\mathrm{on},\mathrm{k}}={\displaystyle \underset{0}{\overset{{\mathrm{t}}_{\mathrm{on}}}{\int }}\mathrm{v}\left(\mathrm{t}\right)\mathrm{i}\left(\mathrm{t}\right)\mathrm{dt}={\displaystyle \underset{0}{\overset{{\mathrm{t}}_{\mathrm{on}}}{\int }}\left[\left(\frac{{\mathrm{I}}^{’}}{{\mathrm{t}}_{\mathrm{on}}}\mathrm{t}\right)\left(-\frac{{\mathrm{V}}_{\mathrm{sw},\mathrm{k}}}{{\mathrm{t}}_{\mathrm{on}}}{(\mathrm{t}-\mathrm{t}}_{\mathrm{on}})\right)\right]\mathrm{dt}=\frac{1}{6}{\mathrm{V}}_{\mathrm{sw},\mathrm{k}}{\mathrm{I}}^{’}{\mathrm{t}}_{\mathrm{on}}}}$$

(8)

$${\mathrm{E}}_{\mathrm{off},\mathrm{k}}={\displaystyle \underset{0}{\overset{{\mathrm{t}}_{\mathrm{off}}}{\int }}\mathrm{v}\left(\mathrm{t}\right)\mathrm{i}\left(\mathrm{t}\right)\mathrm{dt}={\displaystyle \underset{0}{\overset{{\mathrm{t}}_{\mathrm{off}}}{\int }}\left[\left(\frac{{\mathrm{V}}_{\mathrm{sw},\mathrm{k}}}{{\mathrm{t}}_{\mathrm{off}}}\right)\left(-\frac{\mathrm{I}}{{\mathrm{t}}_{\mathrm{off}}}{(\mathrm{t}-\mathrm{t}}_{\mathrm{off}})\right)\right]\mathrm{dt}=\frac{1}{6}{\mathrm{V}}_{\mathrm{sw},\mathrm{k}}{\mathrm{It}}_{\mathrm{off}}}}$$

(9)

$${\mathrm{P}}_{\mathrm{SW}}=\mathrm{fs}{\displaystyle \sum _{\mathrm{k}=1}^{\mathrm{Nswitch}}\left({\displaystyle \sum _{\mathrm{i}-1}^{\mathrm{Non},\mathrm{k}}\mathrm{Eon},\mathrm{k}+{\displaystyle \sum _{\mathrm{i}=1}^{\mathrm{Noff},\mathrm{k}}\mathrm{Eoff},\mathrm{k}}}\right).}$$

(10)

2.1.2. Conduction Losses

Conduction losses of a semiconductor power switch occurs during the on-state of the switch, each power switch of the proposed inverter is composed of one transistor and antiparallel connected diode. The conduction power losses P_C is expressed as the sum of the transistor power losses P_C,T and the diode power losses P_C,D. R_T and R_D are the resistances of the transistor and diodes respectively whiles V_T and V_D are the voltages of the transistors and diodes respectively. The average conduction power losses of Equations (13) and (14) are obtained by integrating Equations (11) and (12) for a period. The period of conduction varies when the load characteristics and control methods are considered:

$${\mathrm{P}}_{\mathrm{C},\mathrm{T}}{\left(\mathrm{t}\right)=[\mathrm{V}}_{\mathrm{T}}{+\mathrm{R}}_{\mathrm{T}}\mathrm{i}\left(\mathrm{t}\right)\left]\mathrm{i}\right(\mathrm{t})$$

(11)

$${\mathrm{P}}_{\mathrm{C},\mathrm{D}}{\left(\mathrm{t}\right)=[\mathrm{V}}_{\mathrm{D}}{+\mathrm{R}}_{\mathrm{D}}\mathrm{i}\left(\mathrm{t}\right)\left]\mathrm{i}\right(\mathrm{t})$$

(12)

$${\mathrm{P}}_{\mathrm{C},\mathrm{T}}=\frac{1}{2\mathsf{\pi }}{\displaystyle \underset{0}{\overset{2\mathsf{\pi }}{\int }}{\mathrm{n}}_{\mathrm{T}}}{\left(\mathrm{t}\right)[\mathrm{VT}+\mathrm{R}}_{\mathrm{T}}\mathrm{i}\left(\mathrm{t}\right)\left)\mathrm{i}\right(\mathrm{t}\left)\right]\mathrm{d}\left(\mathsf{\omega }\mathrm{t}\right)$$

(13)

$${\mathrm{P}}_{\mathrm{C},\mathrm{D}}=\frac{1}{2\mathsf{\pi }}{\displaystyle \underset{0}{\overset{2\mathsf{\pi }}{\int }}{\mathrm{n}}_{\mathrm{D}}{\left(\mathrm{t}\right)\left[\right(\mathrm{VT}+\mathrm{R}}_{\mathrm{D}}\mathrm{i}\left(\mathrm{t}\right)\left)\mathrm{i}\right(\mathrm{t}\left)\right]\mathrm{d}\left(\mathsf{\omega }\mathrm{t}\right)}$$

(14)

Total inverter power loss P_LOSS is given by:

$${\mathrm{P}}_{\mathrm{Loss}}{=\mathrm{P}}_{\mathrm{sw}}{+\mathrm{P}}_{\mathrm{C}}$$

(15)

Therefore the efficiency $\eta$ of the inverter is evaluated by:

$$\mathsf{\eta }=\frac{{\mathrm{P}}_{\mathrm{out}}}{{\mathrm{P}}_{\mathrm{in}}}=\frac{{\mathrm{P}}_{\mathrm{in}}{-\mathrm{P}}_{\mathrm{Loss}}}{{\mathrm{P}}_{\mathrm{in}}}$$

(16)

3. Comparison with Other 7-Levels Inverters

This section presents a detailed comparison of the proposed topology’s power circuit with other recently presented three-phase 7-levels inverters as well as the three conventional multilevel inverter topologies (NPC, CHB and FC). This comparison is done with respect to the component count; IGBTs, diodes, capacitors, dc sources, transformers and driver circuit circuits. All references of comparison have seven levels of output voltage except for [20] which has 9-levels.

Table 2. Comparative analysis of proposed topology and other presented topologies.

Topology	Nlevel	NIGBT	NDC	NDriver	NMD	NCD	NCF	NC	NT	NTotal
Proposed	7	18	4	18	18	0	0	0	1	59
[11]	7	36	1	36	36	0	0	6	1	116
[12]	7	36	2	36	36	0	0	9	0	119
[13]	7	54	1	54	55	0	0	17	0	181
[14]	7	30	3	30	30	0	0	0	1	94
[15]	7	30	6	30	30	0	0	0	0	96
[16]	7	24	1	24	30	0	0	9	0	88
[17]	7	14	3	14	12	0	0	3	0	46
[18]	7	30	2	30	30	0	0	9	0	101
[19]	7	18	6	18	18	0	0	0	0	60
[20]	9	24	4	24	24	0	0	8	0	84
[21]	7	24	1	24	24	0	0	8	0	81
[22]	7	18	6	18	36	0	0	0	0	78
[23]	7	24	1	24	24	0	0	5	0	78
NPC	7	36	1	36	36	90	0	6	0	205
FC	7	36	1	36	36	0	45	6	0	160
CHB	7	36	9	36	36	0	0	0	0	117

Note: N_level: Number of levels, N_IGBT: number of IGBT, N_DC: Number of dc sources, N_driver: Number of driver circuits, N_MD: Number of main diodes, N_CD: Number of clamping diodes, N_CF: Number of clamping capacitors, N_C: Number of capacitors, N_T: number of transformers, N_TOTAL: Total number of components.

presents the detailed comparative summary; it can be seen that the proposed topology offers minimum component count in all parameters of comparison except for number of dc sources. MLI with minimum component quantity yields the following advantages; reduced converter losses, reduced size and volume and reduced inverter cost. The general progress made by researchers over the past years in reducing the component quantity of multilevel inverters is exhibited by the great difference in the total component count between the conventional MI topologies and the other references as shown by N_Total column of Table 2.

Table 3. Comparison Based Equations.

Topology	NIGBT	NDriver	NMC	NDC	NTotal
Y-Proposed	2(n + 2)	2(n + 2)	-	n − 3	(8n + 3)
Y1 [11]	6(n − 1)	6(n − 1)	n − 7	n − 6	(16n + 6)
Y2 [12]	6(n − 1)	6(n − 1)	n + 3	n − 5	17n
Y3 [13]	(10n − 15) − 1	(10n − 15) − 1	2n + 3	n − 6	(27n − 8)
Y4 [14]	3(2n − 4)	3(2n − 4)	-	n − 4	(13n + 3)
Y5 [15]	3(2n − 4)	3(2n − 4)	-	n − 1	(13n + 5)
Y6 [16]	3n + 3	3n + 3	n + 3	n − 6	(12n + 4)
Y7 [18]	3(2n − 4)	3(2n − 4)	n + 3	n − 5	(14n + 3)
Y8 [19]	2(n + 2)	2(n + 2)	-	n − 3	3(2n + 4) + 6
Y9 [20]	3n + 3	3n + 3	n + 1	n − 3	12n
Y10 [21]	3n + 3	3n + 3	n + 1	n − 6	3(4n − 1)
Y11 [22]	2(n + 2)	2(n + 2)	-	n − 1	3(4n − 2)
Y12 [23]	3n + 3	3n + 3	n − 2	n − 5	3(4n −6)
Y13 [NPC]	6(n − 1)	6(n − 1)	n − 1	n − 5	6(5n + 1) − (n + 4)
Y14 [CHB]	6(n − 1)	6(n − 1)	n − 1	n − 5	(22n + 6)
Y15 [FC]	6(n − 1)	6(n − 1)	-	n + 3	3(6n − 2) − 3

shows the mathematical relationship between the level count (n) and the other parameters of comparison which are utilized in plotting the graphs of Figure 2, Figure 3, Figure 4 and Figure 5. The four parameters used in plotting the graph of comparison are quantity of IGBTs, the quantity of driver circuit, the quantity of dc sources and finally the total component count. These parameters are utilized as against the number of levels to plot the various graphs. The stepped output voltage counts in the proposed topology and presented topologies of Table 3 are all 7-levels.

Figure 2 shows the graph of comparison of IGBT quantity between the proposed topology and other presented topologies of Table 3 with respect to level count. As shown by the graph, the proposed topology together with two other references [19,22] requires the least number of IGBTs to generate the desired 7-levels. The number of IGBTs and diodes are equal in all topologies under review because of the use of unidirectional switches, however the diode clamped topology requires extra diodes for voltage clamping purposes.

Figure 3 shows the comparison of driver circuit quantity between the proposed topology and other presented topologies of Table 3 with respect to level count. The required driver circuit quantity is dependent on the quantity of switches been utilized; this is because each switch requires an independent driver circuit. For all unidirectional based switches, the driver circuit quantity will always equal to the number of IGBTs. It is evident from the graph of Figure 3 and that of Figure 2 that the proposed topology together with references [19,22] requires the least quantity of driver circuits.

Variation of total component quantity (N_TOTAL) between the proposed topology and other aforementioned topologies of Table 3 is shown by Figure 4. Similar to the other abovementioned comparison parameters, the proposed topology requires the least quantity of components as against the other presented topologies. However, the graph of the proposed topology and reference [19] are same for Figure 4 because the difference in total component count is 1 as shown in Table 2. The maximum number of total component count is found in the three conventional topologies of CHB, NPC and FC where NPC and CHB have the highest and the least component count respectively.

The final parameter of comparison is illustrated by Figure 5. Here the number of dc sources required is compared between the proposed topology and the other topologies of Table 3. The conventional topologies of CHB, NPC and FC each requires nine, one and one DC sources respectively, the proposed topology requires four DC sources. However, it’s worth mentioning that no clamping capacitors or blocking diodes are required in the proposed topology but FC and NPC topologies require capacitors to provide the different levels of stepped voltages. Hence there’s a trade-off between the dc source count and the capacitor count by the proposed and presented topologies.

4. Simulation and Experimental Results

To prove the practicability of the proposed topology, simulation and experimental results are provided. The power circuit of the proposed three-phase MLI as shown in Figure 1b with an RL load is built in PSCAD/EMTDC software and a prototype is implemented by using the topology shown in Figure 1a. Switching techniques have the basic functions of producing quality stepped voltages, minimize harmonic content and reduce switching power losses [25]. Fundamental frequency modulation technique is employed as the switching mechanism for the proposed inverter because it offers minimum switching losses when compared to other PWM techniques such as the sinusoidal PWM technique [26,27]. The parameters utilized for simulation and experimental setup are indicated in

Table 4. Parameters for simulation and implementation.

Parameter	Value
Input voltage Vdc	V1 = V3 = 20 V, V2 = V4 = 10 V
Output Resistance R	100 Ω
Output Inductance L	55 mH
Switching Frequency fs	4 kHz
Output Frequency fo	50 Hz
Modulation Index	1

. In simulated topology, the turns ratio of transformers is considered ${\mathrm{N}}_1/{\mathrm{N}}_2=1$.

4.1. Simulation Results

Simulation investigation of the proposed three-phase 7-levels multilevel inverter is carried out by building and simulating the power circuit of the proposed topology in PSCAD/EMTDC software. The generated output waveforms are illustrated by Figure 6, Figure 7, Figure 8 and Figure 9. The phase voltages are illustrated by Figure 6, with an input voltages of 10 V and 20 V for each phase, the generated seven level output or load voltages with peak to peak magnitude of ± 30 V are plotted together with the desired sinusoidal reference voltage. As shown in Figure 6, va corresponds to phase A load voltage, vb corresponds to phase B load voltage and vc correspond to phase C load voltage whiles the corresponding reference voltages are represented by Refa, Refb and Refc, respectively, the incremental step magnitude is ± 10 V. The load currents are illustrated by Figure 7 where Ia, Ib and Ic correspond to phases A, B and C load currents respectively, the maximum magnitude of the load currents is 300 mA. The generated line to line load voltage which is composed of thirteen levels (13-levels) with peak to peak magnitude of ± 60 V is illustrated by Figure 8, where vab corresponds to line to line voltage between phase A and B, vbc corresponds to line to line voltage between phase B and C and vca corresponds to line to line voltage between phase C and A whiles the corresponding reference voltages are represented by Refab, Refbc and Refca, respectively, the incremental step magnitude is ± 10 V.

Figure 9 shows the blocking voltage of switches in Phase A. The blocked voltage of the four main switches is dependent on the reverse connected dc sources whiles the blocked voltage of the lower and upper switches is the sum of the two voltage sources (V₁ + V₂ = 30 V). The symmetric features of the inverter provide same characteristics for all phases. Using Equation (6) and the simulation parameters (V₁ = V₃ = 20 V and V₂ + V₄ = 10 V), the standing voltage of the proposed inverter for single phase and three-phase modes are 120 V and 360 V, respectively.

4.2. Experimental Results

To prove the validity of the simulation results, a laboratory setup is built. The photo of experimental setup is shown in Figure 10. Due to the use of the same conditions for three phases, the output voltage and current waveforms are shown for first phase. Figure 11 shows the waveforms of voltage and current for phase A. Comparing this figure with Figure 6 and Figure 7, it is clear that there is good agreement between the simulation and experimental results. Figure 12 shows the voltage across the switches S_a1, S_a3 and S_a5. The validity and practicality of the proposed inverter is affirmed by given theories, simulation results, and experimental prototype.

5. Conclusions

A modified three-phase inverter based on developed H-bridge topology is proposed in this paper. The proposed three-phase MLI topology is realized with less number of components, namely 18 unidirectional switches and four DC voltage sources. In the proposed topology, there is no need to use capacitors. This means that there is no need to use complicated control methods to balance the voltage across capacitors. The main advantages of the proposed topology are less component count hence reduced inverter volume and size, reduced inverter cost, less inverter losses and application of lower rated switches. Fundamental frequency modulation technique was applied in generating 7-levels of load voltage for each phase and 13-levels of load voltage for line-to-line voltages. Comparative analysis of the proposed topology and other recently presented topologies with respect to the component count were investigated and it was evident that the proposed topology required less number of components. Computation of the blocking voltage was also explained theoretically and validated with simulation results. Finally, simulation and experimental results are used to reconfirm the accuracy of theoretical results.