Research on Hex Programmable Interconnect Points Test in Island-Style FPGA

Abstract

With the decreasing size of manufacturing process, the scale of island-style field programmable gate array (FPGA) becomes larger, which leads to the increasing complexity of FPGA routing resources, especially hex programmable interconnect points (PIPs). Hex PIPs which span six tiles of the island-style FPGA have complex interconnect rules. Accordingly, research on complete hex PIPs test is rarely involved in the study of routing resources test. Therefore, this paper analyzes the hex PIPs architecture of the island-style FPGA, summarizes the interconnect rules of the hex PIPs mathematically in a two-dimensional coordinate system, and presents two proper test algorithms at the same time. The hex PIPs are divided into three directions, that is, horizontal, vertical, and oblique. According to the proposed coordinate equations, a cycle test structure in the horizontal and vertical directions and a test structure with partial-cascade patterns in the oblique direction are designed respectively. It is concluded that the proposed methods can achieve 100% fault coverage for the hex PIPs test in all directions, and the configuration number for hex lines test with the same methods is significantly decreased than previous researches.

1. Introduction

Field programmable gate array (FPGA) has been widely used in product design and prototype design [1,2]. The advantages of FPGA including high performance, fast time-to-market, low cost, long-term maintenance, design flexibility, and so forth. With the continuous improvement of FPGA performance and cost-effectiveness, there are more and more products based on FPGA [3]. Routing resources, also called interconnect resources, are the principal programmable resources of the island-style FPGA. The configuration bits of the routing resources usually account for more than 80% of the total configuration memory bits of the island-style FPGA. Furthermore, this number goes up to 90% in some modern FPGAs, and the area of the routing resources covers more than that of the logic resources [4].

Routing resources include single lines, single programmable interconnect points (PIPs), double lines, double PIPs, hex lines, hex PIPs, and so forth. Early studies for routing resources performed the test pattern generator (TPG) and the output response analyzer (ORA) externally [5,6]. With the characteristic of rapid hardware diagnosis, build-in self-test (BIST) was gradually used to test single lines [7]. It implemented the TPG and the ORA by configurable logic block (CLB) resources, thus greatly reducing the consumption of I/O resources [8,9,10,11,12]. Sun et al. [8] proposed a parity-based BIST approach for Xilinx 4000 series FPGAs. It required six configurations to complete the test of single lines. Tahoori [13] proposed a research on single lines and single PIPs with MAX Flow algorithm, whereas Bai et al. [14] extended the application of the MAX Flow algorithm to Virtex5 for double lines test with huge number of configurations. Zhao et al. [15] tested single lines and single PIPs separately with improved depth first search (DFS) algorithm. The test was completed with 16 configurations, which was fewer than the number of the configurations in Tahoori [13]. For double lines test, an effective method was proposed in Dixon [16], in which the test was completed with 17 configurations in both horizontal and vertical directions. For more complex hex lines test, YAO [17] proposed a solution in which the number of configurations in the horizontal direction and the vertical direction were eight and 16, respectively. However, both methods shown in Dixon [16] and YAO [17] ignored the PIPs test in the oblique direction. Banik [18,19] proposed an application-dependent test scheme which has low test coverage because it only tests the used interconnect resources. In addition, Ruan [20,21] proposed a method for all interconnect resource test based on graph theory algorithms but with more configuration times. Briefly speaking, the test for the complete hex PIPs is rarely involved in researches on routing resource test except Ruan [20,21].

This paper focuses on the solution for the hex PIPs test of the island-style FPGA. The fault model in this paper is open fault of PIPs and interconnected lines, which can be represented as stuck-at 0 and stuck-at 1. The main contributions of this paper are three-fold:

• An analytical model with several coordinate equations is established to evaluate the propagation of the hex lines. The proposed model can be used to summarize the interconnect rules of the hex PIPs.
• Two coordinate methods for design of high coverage test patterns with corresponding test algorithms are presented.
• In addition to the hex PIPs test, the hex lines test is also covered without any additional effort. Moreover, compared with YAO [17], the configuration number required for the hex lines test is reduced from 24 to four.

The rest of the paper is organized as follows. Preliminaries and background are provided in Section 2. Section 3 describes the analytical model in a two-dimensional coordinate system. Section 4 presents the coordinate methods for hex PIPs test. Then, test algorithms and experimental results are given in Section 5. Finally, conclusions are drawn in Section 6.

2. Preliminaries and Background

A typical island-style FPGA consists of an array of logic blocks surrounded by programmable routing resources and programmable I/O blocks, as shown in Figure 1. A logic block with its corresponding matrix is named as a tile.

Routing resources can be divided into lines and PIPs. A large number of PIPs form a matrix, in which the lines are connected to each other through the PIPs. According to the propagating distance, lines are classified into single lines (see Figure 2), double lines (see Figure 3), and hex lines (see Figure 4). The single lines route the matrix signals to the adjacent matrices. The double lines route the matrix signals along four directions to each two contiguous matrices, and the hex lines route the matrix signals along four directions to each six contiguous matrices.

The hex lines can be classified into four categories: eastward lines, westward lines, northward lines, and southward lines. Figure 5 shows a simplified switch matrix in which the lines are named by a combination of numbers and letters. The initial letter indicates the direction (e.g., E means eastward), the adjacent number indicates the type of the line (e.g., 6 means the hex line), the following parameter indicates the direction of data (e.g., MID or END indicates data importing, and BEG indicates data exporting), and the last number indicates the relative position among the hex lines in the same matrix.

The hex lines can connect to each other via the hex PIPs and can enter the switch matrix of other tiles via the middle point (i.e., at the line with the MID mark) or the ending point (i.e., at the line with the END mark). There are six tiles between the starting point (i.e., at the line with the BEG mark) and the ending point, and three tiles between the starting point and the middle point. The relative position of the hex lines will not be changed during the propagation in the same direction. Take “Horizontal PIP: E6END0 → E6BEG0” and “Vertical PIP: S6END1 → S6BEG1” as examples, the last numbers do not change. However, for the propagation in the oblique direction, the last number in the name of the connected lines may be different. Take “Oblique PIP: E6END1 → N6BEG0” as an example, these two hex lines have different last numbers.

The four edges of the island-style FPGA contain loop-back PIPs, through which the hex lines propagate to the opposite direction. In addition, the direction of the hex lines can be reversed only after passing through the loop-back PIPs, and the relative positions of the hex lines will not be changed. Furthermore, the loop-back PIPs will not change the number of tiles spanned by the hex lines, as shown in Figure 6.

3. HEX PIP Modelling

To summarize the interconnect rules of the hex PIPs, a two-dimension coordinate system based on tiles is set up as shown in Figure 7. For a $(m+1)\times (n+1)$ tile array, the starting point $O(0,0)$ of the coordinate system is in the lower left, and the ending point $E(m,n)$ of the coordinate system is in the upper right. Each tile contains a switch matrix and a function block. According to the type of the logic blocks shown in Figure 1, tiles can be categorized as CLB tile, IOB tile, BRAM tile, DCM tile, and so forth. For the interconnection relationships between the switch matrices and the logic blocks, different types of tiles imply different types of interconnections. However, since the interconnections among the hex lines are fixed, all tiles can be regarded as identical.

This paper takes the hex lines and their PIPs into account exclusively. Each hex line contains three elements, that is, the coordinates of the starting point, the ending point, and the middle point. It is assumed that the coordinate of the tile where a hex line beginning to propagate is $A(i,j)$. Then a set of mathematical equations for calculating the coordinates of the middle point and the ending point can be divided into four cases.

Case 1: Propagation towards the left.   

For the middle point:

$$(x\left(i\right),y\left(j\right))=\left\{\begin{array}{cc}(i-3,j)\hfill & (i>2)\hfill \\ (2-i,j)\hfill & (i\le 2).\hfill \end{array}\right.$$

(1)

For the ending point:

$$(x\left(i\right),y\left(j\right))=\left\{\begin{array}{cc}(i-6,j)\hfill & (i>5)\hfill \\ (5-i,j)\hfill & (i\le 5).\hfill \end{array}\right.$$

(2)

Case 2: Propagation towards the right.   

For the middle point:

$$(x\left(i\right),y\left(j\right))=\left\{\begin{array}{cc}(i+3,j)\hfill & (i<m-2)\hfill \\ (2m-i-2,j)\hfill & (i\ge m-2).\hfill \end{array}\right.$$

(3)

For the ending point:

$$(x\left(i\right),y\left(j\right))=\left\{\begin{array}{cc}(i+6,j)\hfill & (i<m-5)\hfill \\ (2m-i-5,j)\hfill & (i\ge m-5).\hfill \end{array}\right.$$

(4)

Case 3: Propagation towards the top.   

For the middle point:

$$(x\left(i\right),y\left(j\right))=\left\{\begin{array}{cc}(i,j+3)\hfill & (j<n-2)\hfill \\ (i,2n-j-2)\hfill & (j\ge n-2).\hfill \end{array}\right.$$

(5)

For the ending point:

$$(x\left(i\right),y\left(j\right))=\left\{\begin{array}{cc}(i,j+6)\hfill & (j<n-5)\hfill \\ (i,2n-j-5)\hfill & (j\ge n-5).\hfill \end{array}\right.$$

(6)

Case 4: Propagation towards the down.   

For the middle point:

$$(x\left(i\right),y\left(j\right))=\left\{\begin{array}{cc}(i,j-3)\hfill & (j>2)\hfill \\ (i,2-j)\hfill & (j\le 2).\hfill \end{array}\right.$$

(7)

For the ending point:

$$(x\left(i\right),y\left(j\right))=\left\{\begin{array}{cc}(i,j-6)\hfill & (j>5)\hfill \\ (i,5-j)\hfill & (j\le 5).\hfill \end{array}\right.$$

(8)

Similarly, if the coordinates of the middle point or the ending point are known, the position of the starting point can also be deduced by the inverse operation of the above Equations (1)–(8).

4. The Proposed Methods for the HEX PIPs Test

4.1. How to Test Vertical & Horizontal PIPs

When the hex lines propagate continuously in the horizontal or vertical direction, a cycle structure will eventually be formed. The corresponding equation for this cyclic structure in the horizontal direction is described as follows:   

$$\begin{array}{cc}\hfill & \left(x\right(i),y(j\left)\right)=\hfill \\ \hfill & \left\{\begin{array}{cc}(i-6p,j)\hfill & (i-6p\le 5)\hfill \\ (5-i+6p+6q,j)\hfill & (5-i+6p+6q\le m-5)\hfill \\ (2m+i-6p-6q-10,j)\hfill & (5-i+6p+6q>m-5).\hfill \end{array}\right.\hfill \end{array}$$

(9)

For $A(i,j)$ in Figure 7, according to Equation (2), if the hex line propagates to the left along the horizontal direction without crossing the loop-back area, the coordinate of the ending point is $(i-6p,j)$, where p is the number of repetitions propagated before crossing the left-side loop-back area. After that, the coordinate of the ending point becomes $(5-i+6p+6q,j)$, where q is the number of repetitions propagated after crossing the left-side loop-back area but before crossing the right-side loop-back area. When the loop-back operation occurs twice, it means the hex line will propagate from the right to the left. Then the coordinate of the ending point becomes $(2m+i-6p-6q-10,j)$, and the horizontal distance between this point and $A(i,j)$ is

$$\begin{array}{cc}\hfill D_H& =2m+i-6p-6q-10-i\hfill \\ \hfill & =2m-4-6\times (p+q+1).\hfill \end{array}$$

(10)

where, $p+q+1$ is a positive integer. Obviously, the X-axis coordinate of the nearest point B to $A(i,j)$ is

$$X_B=i+D_H\%6=i+(2m-4)\%6,$$

(11)

where % means residual operation.

If $(2m-4)\%6\ne 0$, multiple rounds of propagation are needed to make the final ending point back to $A(i,j)$. Therefore, the number of iterations is defined as

$$M=\left\{\begin{array}{cc}3\hfill & (2m-4)\%6\ne 0\hfill \\ 1\hfill & (2m-4)\%6=0.\hfill \end{array}\right.$$

(12)

where $[M\times (2m-4\left)\right]\%6=0$.

Similarly, in the vertical direction, the Y-axis coordinate of the nearest point C which is closest to $A(i,j)$ is

$$Y_C=j+D_V\%6=j+(2n-4)\%6.$$

(13)

After N rounds of propagation, an end-to-end cycle structure will be formed, where $[N\times (2n-4\left)\right]\%6=0$. The value of N is defined as

$$N=\left\{\begin{array}{cc}3\hfill & (2n-4)\%6\ne 0\hfill \\ 1\hfill & (2n-4)\%6=0.\hfill \end{array}\right.$$

(14)

A large number of cycles described above can be established to cover all hex lines and hex PIPs in the horizontal and vertical directions. However, such cycle structure cannot be controlled and observed because of having no input and output terminals. Therefore, glue logics used to apply test stimulus and control the transmission of the measured signal need to be inserted as shown in Figure 8. The glue logic which is a buffer in this paper is usually implemented by LUT (look-up table) in the CLB tile. In addition, a PIP should be removed from each cycle. The input and output terminals are provided to the enclosed cycle, and then the unclosed cycle can be further cascaded with other similar structure. After being cascaded through the cycle structure, all hex PIPs in the horizontal and vertical directions are testable.

4.2. How to Test Oblique PIPs

As described in the traditional test structure shown in Figure 9, the PIPs under test, like the single line cascade pattern in Wang et al. [6], constitute an end-to-end cascade structure.

Since parts of the hex lines have no PIP in the oblique direction, propagating along the oblique direction will inevitably be connected to a dead end, where the cascade structure can no longer be extended. Hence, it is impossible to construct traditional cascade structure for the hex PIPs in the oblique direction.

Taking into account that the hex PIPs in the oblique direction can hardly be cascaded in the entire circuit, this paper presents a new test structure, through which the hex PIPs can be tested in parallel ways, as shown in Figure 10. Coordinate method is also used to construct such structure. The new test structure contains three parts, that is, stimulus transmission path, PIPs under test, and response transmission path.

A flip-flops chain with taps constitutes the stimulus transmission path. Each flip-flop outputs to the next one along the chain to carry the stimuli, whereas the stimuli are sent through the taps in the chain to the corresponding PIPs. Then the PIPs under test obtain global controllability through the flip-flops chain with taps.

Since the test response cannot be output in parallel without sufficient IO resources, this paper refers to the scanning chain test structure in DFT (design for test) to design the response transmission path. A 2:1 multiplexer with a control terminal is inserted at the input of each flip-flop in the chain. By these multiplexers, the response transmission path can alternately implement parallel input and serial output, which makes the tested PIPs globally observable.

The two flip-flop chains shown in Figure 10 can be implemented in CLB tiles. The hex PIPs under test are connected to these two flip-flop chains for rich observability and controllability. The tile position of the flip-flops is calculated by the coordinate method, and the coordinates of the corresponding flip-flops in the stimulus transmission path are obtained by the Equations (1)–(8).

However, it is difficult to cascade the hex PIPs in the oblique direction globally, partial-cascade plan with enclosed cycle is a good choice. Figure 11 divides the island-style FPGA into different regions. All these sections are loop-back areas except section A. The distribution of partial-cascade structure is divided into three cases, that is, in section A, connected with tiles at the boundary, and connected with tiles at the corner.

If the island-style FPGA is borderless, the partial-cascade structure can migrate to anywhere. However, since the imaginary tiles outside the boundary indicated by the dotted line cannot be tested, as shown in Figure 12, the planned partial-cascade structure cannot be realized anymore in the loop-back areas. It is necessary to reconstruct the partial-cascade structure in the loop-back areas. Take the right boundary (Section D) and the upper right boundary (Section H) as examples, as shown in Figure 13, the corresponding test structures need to be reconstructed to connect to other parts of the partial-cascade structures in section A.

Assume that the coordinate of the new starting point is $\left(x\right(i),y(j\left)\right)$, according to Equation (4), the coordinates of the two adjacent tiles for Section D shown in Figure 13a are $(2m-i-5,j)$ and $(2m-i-5,j+6)$, respectively. Similarly, according to Equation (4) or Equation (6), the coordinate of the upper right tile for Section H shown in Figure 13b is $(2m-i-5,j)$ or $(i,2n-j-5)$, depending on the convenience of the designer.

Through these partial-cascade structures, an enclosed cycle can be formed again, which is very helpful for the generation of test patterns. Furthermore, all the coordinates of the corresponding tiles can be obtained by the Equations (1)–(8).

5. Experiments

The proposed method is general for the island-style FPGA with similar hex PIPs structures. For comparison with YAO [17], this paper selects the Virtex4 series XC4VLX60 of Xilinx as the target device. The automatic routing algorithms were designed by the coordinate equations of the hex lines and implemented by C programs. Meanwhile, a fault injection system shown in Figure 14 was developed to validate the proposed algorithms. The fault injection in this paper is mainly to simulate the s-a-open fault, by removing any number of the PIPs in the XDL file to form any number of s-a-open faults.

The FPGA implementation is designed by Verilog Editor and ChipScope ILA, and synthesized by ISE tools, based on the principles described in this paper. The fault injection flow from concept to generating the configuration bitstream of the FPGA is also shown in Figure 14. The number of configurations means the number of bitstreams loaded into the corresponding FPGA. Moreover, the total number of hex PIPs and the number of covered PIPs can be calculated by checking the XDLRC file and the XDL file of the ISE tools, respectively. By using the automatic routing algorithms, all proposed test patterns can be implemented and 100% fault coverage of the hex lines and the hex PIPs can be guaranteed.

5.1. Test for the Horizontal & Vertical PIPs

Figure 15 shows the architecture of the XC4VLX60, including various types of tiles arranged in 61 columns and 128 rows, where $m=60$ and $n=127$. Since $(2m-4)\%6\ne 0$ and $(2n-4)\%6\ne 0$, according to Equations (12) and (14), the number of iterations in the horizontal and vertical directions are all three ($M=3$, $N=3$). In addition, each row of the XC4VLX60 contains 60 mutually independent hex lines, there will be 20 independent end-to-end cycles in one row ($cycles=60/M$). Similarly, each column of the XC4VLX60 contains 60 mutually independent hex lines, there will be 20 independent end-to-end cycles in one column ($cycles=60/N$).

Table 1. PIPs in the horizontal and vertical directions in one XC4VLX60 tile.

Horizontal PIPs		Vertical PIPs
E → E	W → W	S → S	N → N
E6END1 → E6BEG1	W6END0 → W6BEG0	S6END1 → S6BEG1	N6END0 → N6BEG0
E6END2 → E6BEG0	W6END0 → W6BEG2	S6END2 → S6BEG0	N6END0 → N6BEG2
E6END2 → E6BEG2	W6END1 → W6BEG1	S6END2 → S6BEG2	N6END1 → N6BEG1
E6END3 → E6BEG1	W6END1 → W6BEG3	S6END3 → S6BEG1	N6END1 → N6BEG3
E6END3 → E6BEG3	W6END2 → W6BEG2	S6END3 → S6BEG3	N6END2 → N6BEG2
E6END4 → E6BEG2	W6END2 → W6BEG4	S6END4 → S6BEG2	N6END2 → N6BEG4
E6END4 → E6BEG4	W6END3 → W6BEG3	S6END4 → S6BEG4	N6END3 → N6BEG3
E6END5 → E6BEG3	W6END3 → W6BEG5	S6END5 → S6BEG3	N6END3 → N6BEG5
E6END5 → E6BEG5	W6END4 → W6BEG4	S6END5 → S6BEG5	N6END4 → N6BEG4
E6END6 → E6BEG4	W6END4 → W6BEG6	S6END6 → S6BEG4	N6END4 → N6BEG6
E6END6 → E6BEG6	W6END5 → W6BEG5	S6END6 → S6BEG6	N6END5 → N6BEG5
E6END7 → E6BEG5	W6END5 → W6BEG7	S6END7 → S6BEG5	N6END5 → N6BEG7
E6END7 → E6BEG7	W6END6 → W6BEG6	S6END7 → S6BEG7	N6END6 → N6BEG6
E6END8 → E6BEG6	W6END6 → W6BEG8	S6END8 → S6BEG6	N6END6 → N6BEG8
E6END8 → E6BEG8	W6END7 → W6BEG7	S6END8 → S6BEG8	N6END7 → N6BEG7
E6END9 → E6BEG7	W6END7 → W6BEG9	S6END9 → S6BEG7	N6END7 → N6BEG9
E6END9 → E6BEG9	W6END8 → W6BEG8	S6END9 → S6BEG9	N6END8 → N6BEG8
None	W6END9 → W6BEG9	None	N6END9 → N6BEG9

lists the total 70 PIPs in the horizontal and vertical directions in one XC4VLX60 tile. In order to make the proposed end-to-end cycles observable and controllable, glue logics are inserted through the nearest CLB tiles. Figure 16 shows a cycle structure with the glue logic implemented by the adjacent CLB. For a non-CLB tile, for example, BRAM tile, IOB tile, and so forth, the glue logic is provided by the CLB tile located in other rows or columns, as shown in Figure 17. The fault coverage for PIP test can be calculated by

$$FaultCoverage=\frac{PI{P}_{total}-PI{P}_{lost}}{PI{P}_{total}}$$

(15)

where $PI{P}_{total}$ represents the total number of PIP being tested and $PI{P}_{lost}$ represents the number of PIP lost.

For PIP test in the horizontal direction, there are 20 end-to-end cycles in one row, each cycle contains one glue logic, so the number of PIP lost is $20\times 128=2560$. Meanwhile, the number of the hex PIPs in one direction in a tile of the XC4VLX60 is 35, the total number of hex PIPs in the horizontal and vertical directions in the XC4VLX60 can be obtained by

$$PI{P}_{total\_1}=35\times (m+1)\times (n+1)=273,280.$$

(16)

Therefore, the fault coverage of one time FPGA configuration is

$$FaultCoverag{e}_h=\frac{273,280-2560}{273,280}=99.06\%.$$

(17)

Furthermore, by moving the glue logics to the adjacent tiles and configuring the FPGA again, the fault coverage loss caused by the original glue logics can be compensated, so that the fault coverage can reach 100%.

Similarly, for PIP test in the vertical direction, the number of PIP lost is $20\times 61=1220$, and the fault coverage of one time FPGA configuration is

$$FaultCoverag{e}_v=\frac{273,280-1220}{273,280}=99.55\%.$$

(18)

An algorithm for the hex PIPs test in the horizontal direction is shown in Algorithm 1, which is similar to that in the vertical direction. Test patterns are generated through this algorithm in the horizontal and vertical directions respectively, as shown in Figure 18 and Figure 19. With two of such configurations, the fault coverage for hex PIPs test in the horizontal and vertical directions can reach 99.06% and 99.55%, respectively. With four of such configurations, the fault coverage for the hex PIPs test can reach 100%, and the additional two are dedicated for the deleted PIPs due to the glue logic insertion. In addition, since all PIPs in the horizontal and vertical directions shown in Figure 4 can be tested, the fault coverage for the hex lines test can also reach 100% with four of such configurations.

Table 2. Summary of the configuration number & fault coverage in the horizontal and vertical directions.

Resources	Total PIP Number	Configuration Number	Covered PIPs	Fault Coverage
Horizontal PIPs	273,280	1	270,720	99.06%
& Horizontal lines		2	273,280	100%
Vertical PIPs	273,280	1	272,060	99.55%
& Vertical lines		2	273,280	100%

summarizes the test results of the configuration number and the fault coverage during the fault injection test in the horizontal and vertical directions.

Algorithm 1 Automatic routing algorithm in the horizontal direction.

1: Create an FPGA netlist 2: repeat 3:  construct the cycles in top row 4:  repeat 5:   calculate the PIP coordinate in a cycle 6:   list the PIPs in another netlist 7:  until the cycle is established 8:  delete one PIP in the netlist of the cycle 9: until all PIPs in the row except the deleted ones are included in the cycles 10: add components used for glue logic 11: add PIPs to connect the glue logics and the cycles 12: repeat 13:  the Y coordinate of all PIPs in netlist minus 1 14: until the Y coordinate of all PIPs in netlist is 0 15: repeat 16:  the Y coordinate of all components in netlist minus 1 17: until the Y coordinate of all components in netlist is 0

5.2. Test for the Oblique PIPs

Table 3. PIPs in the oblique direction in one XC4VLX60 tile.

From East	From West	From South	From North
None	W0 → N2	None	N0 → E1
None	W0 → S2	None	N0 → W1
E1 → N0	W1 → N3	None	N1 → E2
E1 → S0	W1 → S3	None	N1 → W2
E2 → N1	W2 → N4	S2 → E0	N2 → E3
E2 → S1	W2 → S4	S2 → W0	N2 → W3
E3 → N2	W3 → N5	S3 → E1	N3 → E4
E3 → S2	W3 → S5	S3 → W1	N3 → W4
E4 → N3	W4 → N6	S4 → E2	N4 → E5
E4 → S3	W4 → S6	S4 → W2	N4 → W5
E5 → N4	W5 → N7	S5 → E3	N5 → E6
E5 → S4	W5 → S7	S5 → W3	N5 → W6
E6 → N5	W6 → N8	S6 → E4	N6 → E7
E6 → S5	W6 → S8	S6 → W4	N6 → W7
E7 → N6	W7 → N9	S7 → E5	N7 → E8
E7 → S6	W7 → S9	S7 → W5	N7 → W8
E8 → N7	None	S8 → E6	N8 → E9
E8 → S7	None	S8 → W6	N8 → W9
E9 → N8	None	S9 → E7	None
E9 → S8	None	S9 → W7	None

lists the total 68 PIPs in the oblique direction in one XC4VLX60 tile. Because one tile can only accommodate up to four different routes, one configuration can cover only four oblique PIPs. Therefore, traditional test methods require 17 configurations to complete the test of 68 PIPs in the oblique direction.

The proposed method designs four kinds of partial-cascade patterns for the oblique PIPs test, as shown in Figure 20, where k represents the hex line number. Based on two of these test patterns, most of the PIPs in Table 3 can be covered, and all PIPs can be divided into four groups, as shown in 

Table 4. Test patterns in the oblique direction in one XC4VLX60 tile.

Group No.	Configuration Number	Test Patterns
1	2	E1 → N0 → W1 → S3 → E1       E2 → N1 → W2 → S4 → E2
		E3 → N2 → W3 → S5 → E3       E4 → N3 → W4 → S6 → E4
		E5 → N4 → W5 → S7 → E5       E6 → N5 → W6 → S8 → E6
		E7 → N6 → W7 → S9 → E7
2	2	N2 → E3 → S2 → W0 → N2       N3 → E4 → S3 → W1 → N3
		N4 → E5 → S4 → W2 → N4       N5 → E6 → S5 → W3 → N5
		N6 → E7 → S6 → W4 → N6       N7 → E8 → S7 → W5 → N7
		N8 → E9 → S8 → W6 → N8
3	2	E8 → N7 → W8       E9 → N8 → W9       W0 → S2 → E0
		N0 → E1 → S0         N1 → E2 → S1
4	1	W7 → N9       S9 → W7

.

According to Figure 10, an oblique PIP test point needs two flip-flops and one LUT. However, there are only eight filp-flops and eight LUTs in one XC4VLX60 tile. For the group one in Table 4, the cascade path is “$E\left(k\right)\to N(k-1)\to W\left(k\right)\to S(k+2)$” (See Figure 20a), requiring 14 flip-flops to form seven test rings. Therefore, it needs to be configured at least twice, otherwise the filp-flops will be inadequate. Similarly, for the group two in Table 4, the cascade path is “$N\left(k\right)\to E(k+1)\to S\left(k\right)\to W(k-2)$” (See Figure 20c). It also needs to be configured twice because the corresponding test patterns need 14 flip-flops too. In addition, the group three in Table 4 requires 10 filp-flops to form five test half-rings and needs to be configured twice, and the group four in Table 4 requires four filp-flops and needs to be configured only once. Furthermore, a sufficient number of configurations means sufficient LUT resources, so there is no need to worry about the glue logic insertion.

Since the number of the hex PIPs in the oblique direction in a tile of the XC4VLX60 is 68, the total number of hex PIPs in the oblique direction in the XC4VLX60 can be obtained by

$$PI{P}_{total\_2}=68\times (m+1)\times (n+1)=530944.$$

(19)

According to Table 4, the cumulative tests of different groups will be carried out in turn, and the corresponding fault coverages are   

$$\begin{array}{c}\hfill \left\{\begin{array}{c}FaultCoverag{e}_1=\frac{7\times 4\times (m+1)\times (n+1)}{530944}=41.18\%\hfill \\ FaultCoverag{e}_2=\frac{14\times 4\times (m+1)\times (n+1)}{530944}=82.35\%\hfill \\ FaultCoverag{e}_3=\frac{(14\times 4+10)\times (m+1)\times (n+1)}{530944}=97.06\%\hfill \\ FaultCoverag{e}_4=\frac{(14\times 4+12)\times (m+1)\times (n+1)}{530944}=100\%.\hfill \end{array}\right.\end{array}$$

(20)

An algorithm for the hex PIPs test in the oblique direction is shown in Algorithm 2. Moreover, since the middle PIPs which are not considered in this paper have similar structure with the hex PIPs in the oblique direction, this algorithm can also be applied to the middle PIPs test.

Algorithm 2 Automatic routing algorithm in the oblique direction, which can also be used for the middle PIPs test.

1: Create an FPGA netlist 2: add components in all CLB tiles 3: repeat 4:  configurate the component with two flip-flops and one 2:1 multiplexer 5: until all components are configurated 6: repeat 7:  connect global clock line to one component 8: until all components are connected to the clock line 9: repeat 10:  connect two adjacent flip-flops in the x-axis 11: until all flip-flops in the x-axis are connected end-to-end 12: repeat 13:  connect the input of flip-flops in the y-axis with the output of the adjacent multiplexer 14:  connect the output of flip-flops in the y-axis with the input of the adjacent multiplexer 15: until all flip-flops in the y-axis are connected to the corresponding multiplexers 16: repeat 17:  Select the test pattern in sequence in all sets of partial-cascade patterns, for example, $E\left(k\right)\to S(k-1)\to W(k-3)\to N(k-1)$ 18:  For$(k=0,k<10,k+1)$ 19:  repeat 20:   construct the partial-cascade structure from a tile 21:   repeat 22:    set one tile as the starting point 23:    calculate the coordinate of the next point 24:   until the partial-cascade structure is completed 25:  until all tiles are covered 26: until all patterns are used

Test patterns are generated through this algorithm in the oblique direction, as shown in Figure 21. Figure 22 shows the details of the PIPs in the oblique direction in a single tile. With six of such configurations, the fault coverage for the hex PIPs test in the oblique direction can reach 97.06%. With seven of such configurations, the fault coverage can reach 100%.

Table 5. Summary of the configuration number & fault coverage in the oblique direction.

Resources	Total PIP Number	Configuration Number	Covered PIPs	Fault Coverage
Oblique PIPs	530,944	2	218,624	41.18%
		4	437,248	82.35%
		6	515,328	97.06%
		7	530,944	100%

summarizes the test results of the configuration number and the fault coverage during the fault injection test in the oblique direction.

6. Conclusions

This paper focuses on the hex PIPs in routing resource test of the island-style FPGA and improves the test efficiency of the hex lines. Accordingly, this paper establishes the coordinated model of hex routing resources, and presents the effective cycle test structure in the horizontal and vertical directions and the test structure with partial-cascade patterns in the oblique direction. These test patterns can be generated automatically by the proposed two algorithms.

Table 2 and Table 5 summarize the test results of the configuration number and the fault coverage during the fault injection test. For the XC4VLX60, a total of four configurations are needed to achieve 100% fault coverage for the hex lines, which is much less than that in YAO [17]. To achieve 100% fault coverage for the hex PIPs, a total of 11 configurations are needed. Furthermore, since the double lines and the double PIPs have similar structure with the hex lines and the hex PIPs in the horizontal and vertical directions, whereas the middle PIPs have similar structure with the hex PIPs in the oblique direction, the proposed methods can be applied to the test of these routing resources.