Next Article in Journal
Energy-Efficient Ternary Multipliers Using CNT Transistors
Previous Article in Journal
Energy Storage Power and Energy Sizing and Specification Using HSSPFC
 
 
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Article

Equivalent Circuit Based Performance Coupling Analysis Method for Lead Wire Interconnection with Defects

1
CETC No.38 Research Institute, Hefei 230088, China
2
Key Laboratory of Electronic Equipment Structure Design, Ministry of Education, Xidian University, Xi’an 710071, China
*
Authors to whom correspondence should be addressed.
Electronics 2020, 9(4), 642; https://doi.org/10.3390/electronics9040642
Submission received: 1 March 2020 / Revised: 8 April 2020 / Accepted: 10 April 2020 / Published: 13 April 2020
(This article belongs to the Section Circuit and Signal Processing)

Abstract

:
There are a large number of interconnections in the microwave module, among which the lead wire interconnection is widely used. Under the environmental load, the solder joint of the lead wire interconnection often appears to have cracks and other defects, which directly affect the return loss and insertion loss when transmitting electrical signals through solder joints, and indirectly affect the performance of the microwave module. For this reason, the segmented modeling method is realized by segmenting the lead wire interconnection structure into two parts in this paper, and the equivalent circuit model of the lead wire interconnection with the cracked solder joint is established using the equivalent circuit method. The correlation mechanism of the shape of the solder joint of the lead wire interconnection is studied, and formulas for predicting electrical performance based on return loss and insertion loss are derived. This paper realizes the prediction of the electrical performance of the lead wire interconnection with the defect, and can provide a reference for engineers and technicians.

1. Introduction

With the development of electronic equipment towards high frequency, high density, and high reliability, the requirements for assembly interconnection among modules in microwave components are becoming higher [1], especially as a lead wire interconnection method in typical interconnection processes. Because electronic equipment often works under the environment of high and low continuous of changing temperature and strong vibration load, it often causes cracks in the solder joint of high frequency microwave components [2,3]. In addition, under high frequency conditions, the parasitic capacitance of the solder joint cannot be ignored. The self-inductance of the solder joint still exists under high frequency conditions, and the AC resistance in the equivalent circuit model of the solder joint is related to the working frequency. Skin effect changes the current distribution inside the solder joint of lead wire interconnection at a high frequency, which easily leads to the increase of the transmission line impedance and the increase of signal transmission loss. More importantly, the impedance discontinuity caused by defects of the solder joint will lead to further deterioration of the signal transmission quality. Therefore, the effect of morphology and geometry parameters of the solder joint on the electromagnetic signal transmission in the high frequency band must be further studied. The morphology and geometric parameters of solder joints change directly owing to the crack, so the effect of solder joint cracks on signal transmission performance has become one of the key factors to be considered in design and service.
At present, the existing research can be summarized into three aspects: accurate characterization of solder joint shape, prediction of solder joint transmission performance, and influence mechanism between solder joint defects and reliability. Zhu et al. studied the prediction method of PLCC (plastic leaded chip carrier) solder joint shape and the factors influencing the fatigue life of solder joint [4]. Liang et al. characterized the bonding wire and built a three-dimensional model using HFSS (high frequency structure simulator) to study the transmission performance of the bonding wire [5]. Putaala et al. predicted the high frequency performance of the ball grid array device under thermal cycling loading by means of software simulation [6]. Shao et al. studied the relationship between solder joints location and fatigue life of PBGA (plastic ball grid array package) under vibration impact and showed that the solder joints in the center of the specimen was more prone to crack defects [7]. Xiao et al. studied the reliability analysis technology of SiP (system-in-package) based on PoF (physics of failure), and analyzed the failure mode and mechanism of SiP [8]. Tian et al. studied the effect of bonding wire shape parameters on transmission performance, and proposed an equivalent circuit model of bonding wire [9]. Kwon et al. proposed a method to predict the effective life of interconnection joints using radio frequency impedance analysis, and a prediction method based on interconnection model, which use impedance analysis and particle filter to detect and predict interconnection faults quantitatively [10,11]. Finally, Yoon et al. proposed a diagnosis compensation method based on the digital signal representation to evaluate the defects of the solder joint [12].
Currently, there is a lack of research on the coupling mechanism between morphology parameters, and signal transmission performance of interconnection structures. To solve this problem, this paper makes a parametric characterization of the solder joint when there is a defect (the crack) in the lead wire interconnection, and studies the influence of the crack of the solder joint on the electrical performance of the lead wire interconnection. The equivalent circuit with cracked solder joints is constructed, the formula for predicting the electrical performance of the lead wire interconnection with the crack is deduced from the theoretical level, and the accuracy of the results of the prediction formula is verified by software simulation.

2. Analysis of Structure Characteristics of the Lead Wire Interconnection

Lead wire interconnections are mainly divided into the coaxial joint, lead wire, microstrip line, dielectric substrate, and solder joint, as shown in Figure 1. In the environment of high and low temperature continuous change and strong vibration load, the main failure mode of the solder joint in the high-frequency microwave module is crack, and the connection part between the solder joint and the microstrip line is often broken from the outside to the inside [13,14], which is difficult to observe with the naked eye and can only be observed by special instruments, as shown in Figure 2.
In order to study the effect of the crack on the electrical performance of the lead wire interconnection, a parameterized characterization model is needed. Because there is no mathematical characterization method for the lead wire interconnection at present, in order to achieve the correlation analysis between the shape and performance of the lead wire interconnection, the shape function relationship of lead wire interconnection needs to be further studied. The solder joint of lead wire interconnection is divided into two parts for parameterized characterization modeling and impedance analysis, as shown in Figure 3 (see Appendix Table A1 and Figure A1).
For the first part of the solder joint, the shape function fitting of the solder joint is divided into several cases according to the solder side climb height (see Appendix Table A2). The cross section of the lead wire interconnection is shown in Figure 4. As the cross section of the solder joint can generally be approximated to a symmetric structure, the function fitting of one half of the curves is analyzed here, and the other half is taken as a mirror of the function to establish the overall parameterized model, as shown in Figure 5.
Because the structure of solder joint is symmetrical, it is assumed that the crack propagates from right to left in this paper. In addition, because the position of the crack in the solder joint of the lead wire interconnection is often the contact position between the solder joint and the microstrip line, showing the characteristic of layered tearing, it can be assumed that the crack is a uniform thickness, along the length direction of the contact part between the solder joint and the microstrip line, and the internal medium is a square groove of air. On this basis, the crack height can be set to h and the crack width to w, and the model can be established as shown in Figure 6.

3. Performance Prediction Method of the Solder Joint with the Crack Based on Equivalent Circuit Method

The structure of lead wire interconnection is continuous and the connection mode is similar to that of transmission lines. It can be divided into feed impedance Z0, coaxial impedance Z1, solder joint Ⅰ impedance Z3, solder joint Ⅱ impedance Z4, and microstrip line impedance Z5 (as shown in Figure 7). In order to achieve the mathematical characterization of the correlation between shape and performance of lead wire interconnection, it is necessary to introduce the transmission line theory; the classical transmission line theory generally solves the impedance of transmission line for the uniform transmission line. Therefore, the transmission line of the part of the solder joint can be approximated as the uniform transmission line when deriving the mathematical relationship.
Among them, feed impedance Z0, coaxial line impedance Z1, microstrip line impedance Z4, and load impedance Z5 can be calculated directly, while the geometry of the signal transmission path will change owing to the defect in solder joint Ⅰ and solder joint Ⅱ, which will result in the change of the characteristic impedance of the area including the solder joint. As the crack decreases the width of the signal path, the series inductance and loop inductance sensed by the signal increase, resulting in discontinuous inductance. It is impossible to calculate directly. Its equivalent circuit model needs to be established to derive the calculation formulas of Z2 and Z3.

3.1. Extraction of Equivalent Circuit Parameters of the Solder Joint with the Crack

It is assumed that the crack propagates inward from the right side. Figure 8 below shows the geometrical representation of the solder joint with a crack. In the graph, h is the height of the crack, w is the width of the crack, W2 is the width of the solder joint, and L3+b is the length of the solder joint.
On the basis of the above analysis, in order to further determine the equivalent circuit parameters when there is a crack in the solder joint of the lead wire interconnection, the shape of the solder joint of the lead wire interconnection with the defect is divided into continuous part and discontinuous part.
For the continuous part, the shape of the solder joint is the same as that of the intact solder joint. The solder joint above the microstrip line only has inductance, which is represented by L(W2−w). In the discontinuous part, owing to the existence of the crack, the parasitic capacitance Cw cuts off the inductance Lw of this part and connects with the microstrip line directly. The equivalent inductance Lcr in the transmission line theory is obtained by connecting the continuous part and the disconnected part in parallel. The inductance Lcr and the parasitic capacitance C generated in the microstrip line and the grounding plate form the transmission line model of the cracked solder joint of lead wire interconnection (as shown in Figure 9).
The capacitance Cw is generated on the surface below the cracked solder joint and on the upper surface of the transmission line in the crack area. Its value depends on the crack height h and crack width w, the intermediate medium material is air, and its relative dielectric constant ε0 = 1. When the crack length is l, the capacitance Cw can be expressed as follows:
C w = ε 0 l w 4 π k h
Owing to the existence of the crack, the original intact lead wire interconnection is divided into two parts. The inductance of the cracked part and the ground are separated by the crack. The equivalent circuit is the series of the inductance Lw and the capacitance Cw. The other part of the solder joint remains intact, so here it is equivalent to L(W2−w). Because the crack gap is small, the inductance of the two parts is approximated as part of the inductance of the intact solder joint, which is expressed as follows:
L w = w W 2 L
L ( W 2 w ) = W 2 w W 2 L
Owing to the complexity of accurate calculation of surface inductance of microstrip line at a high frequency, an approximate calculation of microstrip inductance is often used in engineering to improve efficiency. At a high frequency, the skin effect of the microstrip line is significant, resulting in redistribution of the conductor current, the conductor inductance concentrates on the external inductance, and the internal inductance is almost zero when the frequency is much higher than the frequency at which the skin depth is comparable to the geometric thickness. Therefore, the inductance of the solder joint at a high frequency can be approximated to its external inductance. At a high frequency, the empirical formula of self-inductance Ls of the microstrip line is as follows:
L s ( t , l , w 0 ) = μ t 2 π [ ln ( 2 t w 0 + l ) + 1 2 + 2 9 ( w 0 + l t ) ]
where l is the routing length, w0 is the routing width, and t is the routing thickness.
The mutual inductance between the conductor and the grounding surface is also caused by the presence of a return current on the grounding surface. Because the calculation of the mutual inductance is complex, it is difficult to form an empirical formula with engineering application value. For the solder joint of lead wire interconnection, the mutual inductance is mainly related to the length of the relative surface and the thickness of the conductor. Taking the length of the relative surface and the thickness of the conductor as independent variables, and taking the mutual inductance Lm as the dependent variable, the fitting function is as follows:
L m ( t , l ) = 3.26 × 10 7 l + 5.13 × 10 8 t 6.36 × 10 6 l t 4.13 × 10 10
Therefore, the formula for calculating the inductance L (Unit: H) of the solder joint is as follows:
L ( t , l , w 0 ) = L s ( t , l , w 0 ) L m ( t , l )
The difference between the capacitance of a microstrip transmission line and a flat capacitor is that the corresponding areas of good conductors are not the same. In the flat capacitor calculation formula,
C = Q U = ε r S 4 π k d ,
S is the product of the area of the upper and lower good conductors of the microstrip line, then multiplied by a weight function Δ c ( l , t ) , which is related to the thickness of the microstrip line. The assumption is as follows:
C = ε r ( w 0 + w 1 ) Δ c ( l , t ) 4 π k d
With the relative plane length l and the conductor thickness t as independent variables and the capacitance weight coefficient Δ c ( l , t ) as dependent variables, the fitting function is as follows:
Δ c ( l , t ) = 2.35 × 10 6 + 0.2461 l + 8.022 × 10 3 t + 25.15 l t
Therefore, the calculation formula of the capacitance C (Unit: F) of the microstrip line can be obtained as follows:
C ( t , l ) = ε r ( w 0 + w 1 ) ( 2.35 × 10 6 + 0.2461 l + 8.022 × 10 3 t + 25.15 l t ) 4 π k d
On the basis of the above conclusions, the formula for calculating the impedance when there is a crack in the lead wire interconnection is obtained as follows:
Z = R + j ω L ( W 2 w ) 1 ω 2 C w L w 1 ω 2 C w L j ω C
However, this formula derives from the premise that the whole part of the connection between the solder joint and the microstrip line needs to show the inductive Lcr in the presence of the crack. Only in this way can the equivalent circuit structure match the equivalent circuit structure of the microstrip transmission line, and it is applicable to the formula for calculating the impedance of the microstrip transmission line. This limit can be expressed as a mathematical formula:
1 ω 2 C w L w 1 ω 2 C w L > 1

3.2. Calculation Method of Electrical Performance of the Solder Joint with the Crack

On the basis of the above analysis, the solder joint of lead wire interconnection is divided into four parts and the formula for calculating the impedance of the solder joint is derived. If the feed impedance Z0 and the load impedance Z5 are both 50 Ω, the reflection coefficients of each part can be calculated separately according to the formula for calculating the reflection coefficient. The calculation relationship is shown in Figure 9. The specific calculation formula is as follows:
Γ = | Z 0 Z L Z 0 + Z L |
According to the definition of the reflection coefficient, it is the ratio of the intensity of the reflection wave to the intensity of the incident wave. If the intensity of the incident wave is expressed as P, and the intensities of the reflection wave at each solder joint are expressed as P1, P2, P3, P4, and P5, respectively, then the reflection coefficients of each part can be expressed as the form shown in Figure 10, and the intensity of the reflection wave at the solder joint of the lead wire interconnection can be ignored with respect to the intensity of the incident wave. Therefore, the expressions of each reflection coefficient can be obtained as follows:
Γ n = | Z n 1 Z n Z n 1 + Z n | = P n P 1 n 1 P n , n = 1 , 2 , 3 , 4 , 5
where the feed impedance Z0 and load impedance Z5 are both 50 Ω, Z 1 = 60 μ r ε r ln ( R 2 R 1 ) , Z 4 = R + j ω L j ω C , and Z2 and Z3 can be calculated by Equation (11).
According to the above, for the lead wire interconnection, the reflection coefficients of each connection part can be approximately integrated into the equivalent reflection coefficient of the whole lead wire interconnection, and the calculation formula is as follows:
Γ = P 1 + P 2 + P 3 + P 4 + P 5 P = ( Γ 1 + Γ 2 + Γ 3 + Γ 4 + Γ 5 ) Γ 1 ( Γ 2 + Γ 3 + Γ 4 + Γ 5 ) Γ 2 ( Γ 3 + Γ 4 + Γ 5 ) Γ 3 ( Γ 4 + Γ 5 ) Γ 4 Γ 5 + Γ 1 Γ 2 ( Γ 3 + Γ 4 + Γ 5 ) + ( Γ 1 Γ 3 + Γ 2 Γ 3 ) ( Γ 4 + Γ 5 ) + Γ 4 Γ 5 ( Γ 1 + Γ 2 ) + Γ 3 Γ 4 Γ 5 Γ 1 Γ 2 Γ 3 ( Γ 4 + Γ 5 ) Γ 4 Γ 5 ( Γ 1 Γ 2 + Γ 1 Γ 3 + Γ 2 Γ 3 ) + Γ 1 Γ 2 Γ 3 Γ 4 Γ 5
On the basis of the equivalent reflection coefficient of the lead wire interconnection, the return loss of the lead wire interconnection can be calculated according to Equation (16) and the insertion loss of the lead wire interconnection can be calculated according to Equation (17).
R L = 10 ln ( Γ 2 )
I L = 10 ln ( 1 Γ 2 )

4. Verification and Discussion

In order to further verify the accuracy of the calculation formula for predicting the electrical performance of the lead wire interconnection in the presence of defect, according to the combined data selected from the orthogonal experimental design, which has the characteristic of optimal coverage for the combination situation [15,16], a parameterized characterization model for the defective lead wire interconnection was used. Six parameters with more considerations in the debugging design were selected as variables, and a six-factor seven-level orthogonal table was established to generate 49 sets of test items representing all possible situations (see Appendix Table A3).
In this paper, the frequency point f = 10 GHz is selected for comparison and validation, through the performance analysis of the HFSS software in the frequency range of 1–40 GHz. The lead wire interconnection model with different geometric parameters is established as shown in Figure 11, after adding the radiation boundary condition and the wave port excitation, the corresponding analysis is set to solve the frequency of the simulation. The return loss is obtained as shown in Figure 12, and the insertion loss is obtained as shown in Figure 13. Then, the performance prediction results are calculated by using the prediction formula obtained in Section 2 based on the parameter values of each test item. The comparison is shown in Appendix Table A4, because the characterization formula used in the parameterized modeling of HFSS is more complex. Some parameter combinations will result in structural conflicts that cannot be verified and eliminated.
It can be seen from the results in Appendix Table A4 that, for the defective lead wire interconnection, at 10 GHz, the results obtained by using the electrical performance prediction formula are compared with those obtained by HFSS simulation. The average error of return loss is 2.4564 dB with the variance of 1.0348; the average error of insertion loss is 0.1072 dB with the variance of 0.1076. Therefore, the formula deduced in this paper for the performance prediction of lead wire interconnection with the defect has high accuracy. From Figure 12 and Figure 13, additionally, it can be seen that when the frequency is greater than 30 GHz, the electrical performance index of the lead wire interconnection fluctuates dramatically. By analyzing the performance prediction formula when there is the defect in the interconnect point, it can be seen that the effect of frequency on the impedance of the lead wire interconnection increases, and the solder joints in high frequency band will not be applicable.
The existence of the crack changes the signal transmission path and aggravates the loss of signal transmission. Figure 14a,b show S11 and S21 values for different crack widths, respectively. In order to obtain clear graphics and accurate data, the frequency ranges from 5 GHz to 10 GHz are intercepted. It can be seen that S11 increases with frequency and S21 decreases with frequency. S11 increases with the increase of the crack width w when other structural parameters of the lead wire interconnection remain unchanged (initial value, shown as Table A1) and only the crack width is changed. For example, at 7.5 GHz, S11 is −19.12 dB when the crack width w is 0.3 mm and −18.17 dB when the crack width w is 0.5 mm; the latter is 0.95 dB greater than the former. Meanwhile, S21 is also affected by the crack width. S21 decreases with the increase of the crack width w. At 7.5 GHz, S21 is −0.087 dB when the crack width w is 0.3 mm and S21 is −0.097 dB when the crack width w is 0.5 mm. It is obviously necessary to control the occurrence of the crack in engineering practice.
Figure 15a,b show the values of S11 and S21 for different lead wire lengths, respectively. Similarly, in the frequency range from 5 GHz to 10 GHz, S11 increases with the increase of frequency and S21 decreases with the increase of frequency. When the other structure parameters of the lead wire interconnection are unchanged (initial value, shown as Table A1), the crack width w is fixed at 0.3 mm, only the length of the lead wire is changed, and S11 decreases with the decrease of the length of the lead wire L3. For example, at 7.5 GHz, S11 is −18.97 dB when the lead wire length L3 is 1.3 mm, while S11 is −17.74 dB when the lead wire length L3 is 1.5 mm; the difference is 1.23 dB. Moreover, S21 increases with the decrease of the lead wire length L3, S21 is −0.09 dB when the lead wire length L3 is 1.0 mm, and S21 is −0.11 dB when the lead wire length L3 is 1.5 mm. Therefore, a shorter lead wire length can be selected appropriately in engineering practice to reduce the performance degradation when the crack occurs in the interconnection. However, it should be noted that a shorter lead wire length may lead to insufficient mechanical strength of the interconnection and shorter fatigue life under vibration and thermal cycling conditions.

5. Conclusions

On the basis of the equivalent circuit method and the three-dimensional model of lead wire interconnection, the formulas for calculating the impedance of solder joints in the presence of defect are given, and then the formulas for calculating the return loss and insertion loss are derived. The influence of the geometrical parameters of the cracked lead wire interconnection on the signal transmission characteristics is discussed. The prediction results of electrical performance of the cracked solder joint are verified by simulation. Further, the theoretical derivation results are in good agreement with the simulation results. The results can be used to predict the electrical performance of defective solder joints in engineering practice for reference by engineering technicians. Meanwhile, the purpose of this paper is to provide a theoretical prediction method for transmission performance of the lead wire interconnection with cracked solder joint. In the next stage, it is possible to consider accumulating the measured data of transmission performance of the lead wire interconnection with cracked solder joint in engineering practice to compare and verify.

Author Contributions

Conceptualization, Z.W. and L.W.; methodology, Z.W. and C.W.; validation, L.W.; formal analysis, Z.W., K.Y., and S.L.; data curation, K.Y. and S.L.; writing—original draft preparation, Z.W., K.Y., and S.L.; writing—review and editing, Z.W., L.W., and C.W.; supervision, L.W.; project administration, L.W.; Funding acquisition, Z.W. and C.W. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by National Natural Science Foundation of China under Grant 51975447 and U1737211, Natural Science Foundation of Shaanxi Province under Grant 2018JZ5001, Youth Science and Technology Star Project of Shaanxi Province under Grant No. 2018KJXX-047, and Youth Innovation Team of Shaanxi Universities under Grant 201926.

Conflicts of Interest

The authors declare no conflict of interest.

Appendix A

Table A1. Lead wire interconnection parameters.
Table A1. Lead wire interconnection parameters.
Structural UnitPhysical ParameterStructural Parameter
MaterialRelative PermittivityLoss TangentParameterVariablePreset Value (mm)
Dielectric substrateAl2O39.92 × 10−4LengthL16
WidthW14.5
ThicknessH10.635
microstrip lineAu10LengthL26
WidthW20.6
ThicknessH20.02
LeadDiameterD10.3
LengthL31.2
Solder jointSn37Pb6310End heighta0.4
End lengthb0.3
Side heightc0.4
Section widthd0.6
Coaxial jointInsulator41.35 × 10−5LengthL41.6
DiameterD21.8
CrackAir1/Widthw0.3
Heighth0.01
Figure A1. Lead wire interconnection.
Figure A1. Lead wire interconnection.
Electronics 09 00642 g0a1
Table A2. Parameterized characterization.
Table A2. Parameterized characterization.
Solder Joint ShapeCharacterization Function
Electronics 09 00642 i001
H 3 < c < H 3 + D 1 / 2
Case 1
Characterization function 1:
z = c 2 c o s ( 2 π d 2 f ( x ( D 1 2 ) 2 ( D 1 2 + H 3 c ) 2 ) ) + c 2
x ( ( D 1 2 ) 2 ( D 1 2 + H 3 c ) 2 , d 2 )
Electronics 09 00642 i002
H 3 + D 1 / 2 < c < H 3 + D 1
Case 2
Characterization function 1:
z = ( D 1 2 + H 3 ) s i n ( 2 π ( 2 d 2 D 1 4 e ) ( x d + D 1 2 + e ) ) + ( D 1 2 + H 3 )
x ( D 1 2 + e , d 2 )
Characterization function 2:
z = ( c D 1 2 H 3 ) c o s ( 2 π 2 D 1 + 4 e 4 ( D 1 2 ) 2 ( D 1 2 + H 3 c ) 2 ( x ( D 1 2 ) 2 ( D 1 2 + H 3 c ) 2 ) ) + D 1 2 + H 3 x ( ( D 1 2 ) 2 ( D 1 2 + H 3 c ) 2 , D 1 2 + e )
Electronics 09 00642 i003
H 3 + D 1 < c
Case 3
Characterization function 1:
z = ( D 1 2 + H 3 ) s i n ( 2 π ( 2 d 2 D 1 4 e ) ( x d + D 1 2 + e ) ) + ( D 1 2 + H 3 )
x ( D 1 2 + e , d 2 )
Characterization function 3:
z = ( c D 1 2 H 3 ) c o s ( 2 π 2 D 1 + 4 e x ) + H 3 + D 1 2
x ( 0 , D 1 2 + e )
Electronics 09 00642 i004
End of solder joint
z = a 2 cos ( π b y ) + a 2
y ( 0 , b )
Table A3. Six-factor seven-level orthogonal table.
Table A3. Six-factor seven-level orthogonal table.
Serial NumberL3W2dH1wac
10.9 mm0.45 mm0.45 mm0.485 mm0 mm0.16 mm0.16 mm
20.9 mm0.5 mm0.5 mm0.535 mm0.1 mm0.21 mm0.21 mm
30.9 mm0.55 mm0.55 mm0.585 mm0.2 mm0.26 mm0.26 mm
40.9 mm0.6 mm0.6 mm0.635 mm0.3 mm0.31 mm0.31 mm
50.9 mm0.65 mm0.65 mm0.685 mm0.4 mm0.36 mm0.36 mm
60.9 mm0.7 mm0.7 mm0.735 mm0.5 mm0.41 mm0.41 mm
70.9 mm0.75 mm0.75 mm0.785 mm0.6 mm0.46 mm0.46 mm
81 mm0.45 mm0.45 mm0.535 mm0.2 mm0.31 mm0.36 mm
91 mm0.5 mm0.5 mm0.585 mm0.3 mm0.36 mm0.41 mm
101 mm0.55 mm0.55 mm0.635 mm0.4 mm0.41 mm0.46 mm
111 mm0.6 mm0.6 mm0.685 mm0.5 mm0.46 mm0.16 mm
121 mm0.65 mm0.65 mm0.735 mm0.6 mm0.16 mm0.21 mm
131 mm0.7 mm0.7 mm0.785 mm0 mm0.21 mm0.26 mm
141 mm0.75 mm0.75 mm0.485 mm0.1 mm0.26 mm0.31 mm
151.1 mm0.45 mm0.45 mm0.585 mm0.4 mm0.46 mm0.21 mm
161.1 mm0.5 mm0.5 mm0.635 mm0.5 mm0.16 mm0.26 mm
171.1 mm0.55 mm0.55 mm0.685 mm0.6 mm0.21 mm0.31 mm
181.1 mm0.6 mm0.6 mm0.735 mm0 mm0.26 mm0.36 mm
191.1 mm0.65 mm0.65 mm0.785 mm0.1 mm0.31 mm0.41 mm
201.1 mm0.7 mm0.7 mm0.485 mm0.2 mm0.36 mm0.46 mm
211.1 mm0.75 mm0.75 mm0.535 mm0.3 mm0.41 mm0.16 mm
221.2 mm0.45 mm0.45 mm0.635 mm0.6 mm0.26 mm0.41 mm
231.2 mm0.5 mm0.5 mm0.685 mm0 mm0.31 mm0.46 mm
241.2 mm0.55 mm0.55 mm0.735 mm0.1 mm0.36 mm0.16 mm
251.2 mm0.6 mm0.6 mm0.785 mm0.2 mm0.41 mm0.21 mm
261.2 mm0.65 mm0.65 mm0.485 mm0.3 mm0.46 mm0.26 mm
271.2 mm0.7 mm0.7 mm0.535 mm0.4 mm0.16 mm0.31 mm
281.2 mm0.75 mm0.75 mm0.585 mm0.5 mm0.21 mm0.36 mm
291.3 mm0.45 mm0.45 mm0.685 mm0.1 mm0.41 mm0.26 mm
301.3 mm0.5 mm0.5 mm0.735 mm0.2 mm0.46 mm0.31 mm
311.3 mm0.55 mm0.55 mm0.785 mm0.3 mm0.16 mm0.36 mm
321.3 mm0.6 mm0.6 mm0.485 mm0.4 mm0.21 mm0.41 mm
331.3 mm0.65 mm0.65 mm0.535 mm0.5 mm0.26 mm0.46 mm
341.3 mm0.7 mm0.7 mm0.585 mm0.6 mm0.31 mm0.16 mm
351.3 mm0.75 mm0.75 mm0.635 mm0 mm0.36 mm0.21 mm
361.4 mm0.45 mm0.45 mm0.735 mm0.3 mm0.21 mm0.46 mm
371.4 mm0.5 mm0.5 mm0.785 mm0.4 mm0.26 mm0.16 mm
381.4 mm0.55 mm0.55 mm0.485 mm0.5 mm0.31 mm0.21 mm
391.4 mm0.6 mm0.6 mm0.535 mm0.6 mm0.36 mm0.26 mm
401.4 mm0.65 mm0.65 mm0.585 mm0 mm0.41 mm0.31 mm
411.4 mm0.7 mm0.7 mm0.635 mm0.1 mm0.46 mm0.36 mm
421.4 mm0.75 mm0.75 mm0.685 mm0.2 mm0.16 mm0.41 mm
431.5 mm0.45 mm0.45 mm0.785 mm0.5 mm0.36 mm0.31 mm
441.5 mm0.5 mm0.5 mm0.485 mm0.6 mm0.41 mm0.36 mm
451.5 mm0.55 mm0.55 mm0.535 mm0 mm0.46 mm0.41 mm
461.5 mm0.6 mm0.6 mm0.585 mm0.1 mm0.16 mm0.46 mm
471.5 mm0.65 mm0.65 mm0.635 mm0.2 mm0.21 mm0.16 mm
481.5 mm0.7 mm0.7 mm0.685 mm0.3 mm0.26 mm0.21 mm
491.5 mm0.75 mm0.75 mm0.735 mm0.4 mm0.31 mm0.26 mm
Table A4. Accuracy verification at 10 GHz.
Table A4. Accuracy verification at 10 GHz.
Serial NumberReturn Loss/dBInsertion Loss/dBValidity
Simulation ResultsCalculation ResultsErrorSimulation ResultsCalculation ResultsErrorPart ⅠPart Ⅱ
1/15.9780 //0.1111 /1.0139 1.0167
217.9571 16.3727 1.5844 0.1068 0.1013 0.0055 1.0446 1.0558
316.4051 13.8190 2.5862 0.1294 0.1841 0.0547 1.0650 1.0920
417.9541 14.5171 3.4370 0.1030 0.1563 0.0533 1.0894 1.1262
519.0317 15.2787 3.7531 0.1052 0.1307 0.0255 1.1132 1.1589
619.4982 16.6674 2.8308 0.0812 0.0946 0.0133 1.1392 1.1907
718.2652 18.2409 0.0243 0.1035 0.0656 0.0379 1.1659 1.2220
815.3195 11.9561 3.3634 0.1619 0.2860 0.1241 1.0744 1.0922
916.1931 12.9885 3.2046 0.1221 0.2239 0.1018 1.1045 1.1259
1017.0233 14.1723 2.8510 0.1120 0.1694 0.0574 1.1351 1.1582
1119.2189 20.3768 1.1579 0.0863 0.0400 0.0463 1.1993 1.1895
1220.4360 18.8434 1.5926 0.0712 0.0571 0.0142 1.2227 1.2417
13/15.5474 //0.1228 /1.0125 1.0147
1412.0726 8.7999 3.2727 0.3154 0.6139 0.2986 1.0426 1.0499
1518.9619 15.8054 3.1565 0.0911 0.1156 0.0245 1.1855 1.1534
1614.2343 12.4607 1.7736 0.2159 0.2537 0.0378 1.1877 1.2080
1714.4892 12.6883 1.8009 0.1931 0.2404 0.0473 1.2195 1.2401
18/13.7957 //0.1851 /1.0144 1.0152
1918.3588 14.5316 3.8272 0.0976 0.1557 0.0581 1.0503 1.0515
2012.3906 9.0221 3.3685 0.2922 0.5812 0.2890 1.0864 1.0858
2113.0065 11.8690 1.1375 0.2576 0.2920 0.0344 1.1410 1.1186
2213.9923 11.9306 2.0616 0.2147 0.2878 0.0730 1.2752 1.2269
23/15.4593 //0.1253 /1.0186 1.0157
2421.7364 20.9971 0.7393 0.0617 0.0347 0.0270 1.0726 1.0526
2521.2326 19.3577 1.8749 0.0632 0.0506 0.0125 1.1167 1.0872
2712.1025 8.9417 3.1608 0.2895 0.5928 0.3033 1.1798 1.1636
2813.1501 9.4724 3.6777 0.2648 0.5204 0.2556 1.2191 1.1966
2915.9970 13.0230 2.9740 0.1261 0.2221 0.0960 1.0690 1.0531
3015.6680 13.2340 2.4340 0.0620 0.4013 0.3393 1.1156 1.0876
3116.0931 12.2845 3.8086 0.1317 0.2645 0.1329 1.1618 1.1331
3211.9428 8.7362 3.2066 0.2978 0.6237 0.3259 1.2133 1.1669
3312.9265 9.7057 3.2208 0.2597 0.4915 0.2318 1.2686 1.1995
3414.5851 14.1034 0.4817 0.1881 0.1722 0.0159 1.4028 1.2315
35/12.1096 //0.2758 /1.0203 1.0140
3613.9838 13.1706 0.8133 0.2183 0.2145 0.0039 1.1998 1.1327
3722.8578 19.8572 3.0006 0.0505 0.0451 0.0054 1.3363 1.1660
3814.1754 12.3011 1.8742 0.2074 0.2635 0.0561 1.3899 1.1981
3912.7699 10.3853 2.3846 0.2727 0.4168 0.1441 1.3791 1.2296
40/9.8794 //0.4712 /1.0208 1.0144
4112.3959 10.4702 1.9258 0.2914 0.4083 0.1170 1.0721 1.0490
42/10.5308 //0.4024 /1.1258 1.0871
43/11.7659 //0.2993 /1.3559 1.1895
44/9.1207 //0.5672 /1.4341 1.2202
45/9.9298 //0.4654 /1.0244 1.0148
46/9.8990 //0.4689 /1.0868 1.0543
47/14.2993 //0.1645 /1.1839 1.0901
48/14.4873 //0.1574 /1.2515 1.1241
49/12.2327 //0.2678 /1.2805 1.1568
Average of return loss error2.4564 Average of insertion loss error0.1072
Variance of return loss error1.0348 Variance of insertion loss error0.1076

References

  1. Hsiang, L.; Loh, W.K.; Yee, E.; Seong, L.; Ling, L. Influence of Package Assembly Process on Solder Joint Reliability—An Application of Component Level Shock Methodology. In Proceedings of the 2006 International Conference on Electronic Materials and Packaging, Hong Kong, China, 11–14 December 2006. [Google Scholar] [CrossRef]
  2. Lu, T.; Zou, Y.; He, X.; Qiu, B.; Xiao, H.; Zhou, B. Research on Vibration Reliability of DIP Surface-Mounted Solder Joint after Pin Bend. In Proceedings of the 2018 19th International Conference on Electronic Packaging Technology (ICEPT), Shanghai, China, 8–11 August 2018. [Google Scholar] [CrossRef]
  3. Wu, P.L.; Wang, P.H.; Chiang, K.N. Empirical Solutions and Reliability Assessment of Thermal Induced Creep Failure for Wafer Level Packaging. IEEE Trans. Device Mater. Reliab. 2019, 19, 126–132. [Google Scholar] [CrossRef]
  4. Zhu, J.; Wu, Z. Study on PLCC Lead Free Solder Joint’s Thermal Reliability Based on Shape Prediction and Response Surface Methodology. Adv. Mater. Res. 2013, 706, 1697–1700. [Google Scholar] [CrossRef]
  5. Liang, Y.; Huang, C.; Wang, W. Modeling and Characterization of the Bonding-Wire Interconnection for Microwave MCM. In Proceedings of the 2010 11th International Conference on Electronic Packaging Technology High Density Packaging, Xi’an, China, 16–19 August 2010. [Google Scholar] [CrossRef]
  6. Putaala, J.; Nousiainen, O.; Komulainen, M.; Kangasvieri, T.; Jantunen, H.; Moilanen, M. Influence of Thermal-Cycling-Induced Failures on the RF Performance of Ceramic Antenna Assemblies. IEEE Trans. Compon. Packag. Manuf. Technol. 2011, 1, 1465–1472. [Google Scholar] [CrossRef]
  7. Shao, J.; Zhang, H.; Chen, B. Experimental Study on the Reliability of PBGA Electronic Packaging under Shock Loading. Electronics 2019, 8, 279. [Google Scholar] [CrossRef] [Green Version]
  8. Xiao, H.; Liu, S.; Li, Y. Reliability Analysis of System-in-Package Module Based on Physics of Failure. In Proceedings of the 2018 19th International Conference on Electronic Packaging Technology (ICEPT), Shanghai, China, 8–11 August 2018. [Google Scholar] [CrossRef]
  9. Tian, W.; Cui, H.; Yu, W. Analysis and Experimental Test of Electrical Characteristics on Bonding Wire. Electronics 2019, 8, 365. [Google Scholar] [CrossRef] [Green Version]
  10. Kwon, D.; Azarian, M.H.; Pecht, M. Remaining-Life Prediction of Solder Joints Using RF Impedance Analysis and Gaussian Process Regression. IEEE Trans. Compon. Packag. Manuf. Technol. 2015, 5, 1602–1609. [Google Scholar] [CrossRef]
  11. Kwon, D.; Yoon, J. A model-based prognostic approach to predict interconnect failure using impedance analysis. J. Mech. Sci. Technol. 2016, 30, 4447–4452. [Google Scholar] [CrossRef]
  12. Yoon, J.; Shin, I.; Park, J.; Kwon, D. A Prognostic Method of Assessing Solder Joint Reliability Based on Digital Signal Characterization. In Proceedings of the 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 26–29 May 2015. [Google Scholar] [CrossRef]
  13. Darveaux, R. Effect of Simulation Methodology on Solder Joint Crack Growth Correlation. In Proceedings of the 50th Electronic Components and Technology Conference, Las Vegas, NV, USA, 21–24 May 2000. [Google Scholar] [CrossRef]
  14. Darveaux, R. Effect of simulation methodology on solder joint crack growth correlation and fatigue life prediction. Trans. Am. Soc. Mech. Eng. J. Electron. Packag. 2002, 124, 147–154. [Google Scholar] [CrossRef] [Green Version]
  15. Dong, R.; Xiao, B.; Fang, Y. The theoretical analysis of orthogonal test designs. J. Anhui Inst. Archit. 2004, 6, 029. [Google Scholar]
  16. Su, H.; Yao, Z. Fuzzy analysis method for multi-index orthogonal test. J. Nanjing Univ. Aeronaut. Astronaut. 2004, 36, 29–33. [Google Scholar]
Figure 1. Structure schematic of lead wire interconnection.
Figure 1. Structure schematic of lead wire interconnection.
Electronics 09 00642 g001
Figure 2. Crack of the solder joint.
Figure 2. Crack of the solder joint.
Electronics 09 00642 g002
Figure 3. Segmentation model of the lead wire interconnection.
Figure 3. Segmentation model of the lead wire interconnection.
Electronics 09 00642 g003
Figure 4. Cross section of the lead wire interconnection.
Figure 4. Cross section of the lead wire interconnection.
Electronics 09 00642 g004
Figure 5. Overall structure of the solder joint of the lead wire interconnection.
Figure 5. Overall structure of the solder joint of the lead wire interconnection.
Electronics 09 00642 g005
Figure 6. Parameterized model of the solder joint with the crack.
Figure 6. Parameterized model of the solder joint with the crack.
Electronics 09 00642 g006
Figure 7. Structure decomposition diagram of lead wire interconnection.
Figure 7. Structure decomposition diagram of lead wire interconnection.
Electronics 09 00642 g007
Figure 8. Simplified diagram of the cracked solder joint.
Figure 8. Simplified diagram of the cracked solder joint.
Electronics 09 00642 g008
Figure 9. Transmission line model of the lead wire interconnection with the defect.
Figure 9. Transmission line model of the lead wire interconnection with the defect.
Electronics 09 00642 g009
Figure 10. Energy transfer between parts of lead wire interconnection.
Figure 10. Energy transfer between parts of lead wire interconnection.
Electronics 09 00642 g010
Figure 11. High frequency structure simulator (HFSS) simulation model.
Figure 11. High frequency structure simulator (HFSS) simulation model.
Electronics 09 00642 g011
Figure 12. Trend of S11 with frequency under different structural parameters.
Figure 12. Trend of S11 with frequency under different structural parameters.
Electronics 09 00642 g012
Figure 13. Trend of S21 with frequency under different structural parameters.
Figure 13. Trend of S21 with frequency under different structural parameters.
Electronics 09 00642 g013
Figure 14. (a) S11 of lead wire interconnection with different crack widths; (b) S21 of lead wire interconnection with different crack widths.
Figure 14. (a) S11 of lead wire interconnection with different crack widths; (b) S21 of lead wire interconnection with different crack widths.
Electronics 09 00642 g014
Figure 15. (a) S11 of lead wire interconnection with different lead wire lengths; (b) S21 of lead wire interconnection with different crack lead wire lengths.
Figure 15. (a) S11 of lead wire interconnection with different lead wire lengths; (b) S21 of lead wire interconnection with different crack lead wire lengths.
Electronics 09 00642 g015

Share and Cite

MDPI and ACS Style

Wang, Z.; Wang, L.; Yu, K.; Liu, S.; Wang, C. Equivalent Circuit Based Performance Coupling Analysis Method for Lead Wire Interconnection with Defects. Electronics 2020, 9, 642. https://doi.org/10.3390/electronics9040642

AMA Style

Wang Z, Wang L, Yu K, Liu S, Wang C. Equivalent Circuit Based Performance Coupling Analysis Method for Lead Wire Interconnection with Defects. Electronics. 2020; 9(4):642. https://doi.org/10.3390/electronics9040642

Chicago/Turabian Style

Wang, Zhihai, Lu Wang, Kunpeng Yu, Shaoyi Liu, and Congsi Wang. 2020. "Equivalent Circuit Based Performance Coupling Analysis Method for Lead Wire Interconnection with Defects" Electronics 9, no. 4: 642. https://doi.org/10.3390/electronics9040642

APA Style

Wang, Z., Wang, L., Yu, K., Liu, S., & Wang, C. (2020). Equivalent Circuit Based Performance Coupling Analysis Method for Lead Wire Interconnection with Defects. Electronics, 9(4), 642. https://doi.org/10.3390/electronics9040642

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop