Characterization of Single Event Cell Upsets in a Radiation Hardened SRAM in a 40 nm Bulk CMOS Technology

Abstract

A large amount of data needs to be stored in integrated circuits when data are being processed. The integrated circuits contain a large amount of static random access memory (SRAM) due to its high level of integration and speed. SRAM units should be as small as possible to achieve higher storage density. In this work, the features of single cell upsets (SCUs) and multiple cell upsets (MCUs) in a full custom SRAM are tested for a 40 nm bulk CMOS technology node, and Ge (linear energy transfer (LET) = 37.3 MeV cm²/mg), Cl (LET = 13.1 MeV cm²/mg), Al (LET = 8.6 MeV cm²/mg), O (LET = 3.1 MeV cm²/mg), and Li (LET = 0.5 MeV cm²/mg) particles are used. The test results show that the total single cell upset events are 2,000,147, 1,124,269, 413,100, 311,311, and 47,815 under the irradiation of Ge, Cl, Al, O, and Li, respectively. Moreover, due to single event upset reversal mechanism, multiple cell upsets significantly decrease. The total multiple cell upset events are 10, 4, 0, 0, and 0 under the irradiation of Ge, Cl, Al, O, and Li, respectively. There are a lot of single cell upsets appearing under Ge, Cl, Al, O, and Li exposure. The number is increasing with increasing LET, which means that well contacts still need optimization in the full custom SRAM. Close spacing of well contacts or increasing contacts are the approaches used to drain the excess carriers quickly, and error detection and correction (EDAC) is used for SRAM technology. The features show that SCUs have become a major source of soft errors for the full custom SRAM. Combining close spacing of well contacts with error detection and correction (EDAC) and a well engineering scheme are used to reduce single cell upsets, although there are a few MCUs which are inevitable. Radiation hardened by design schemes needs to be further improved.

1. Introduction

With the development of technology, the design for high performance microprocessors has become more complex, among which the storage system, accounting for 70% of the total area of the microprocessor, is the core part of the microprocessor. A major portion of the area of digital integrated circuits based on silicon is devoted to the storage of data values and program instructions. Most transistors in high-performance microprocessors are devoted to cache memory. The situation is even more dramatic at the system level, such as in high-performance work stations and computers, where the ratio is estimated to further increase [1]. The demand for storage as part of integrated circuit has skyrocketed. Obviously, high-density data storage integrated circuits will be one of the primary concerns of a contemporary digital system or circuit designer. Static random access memory (SRAM) is widely used in integrated circuits due to its high level of integration and speed. SRAM units should be as small as possible to achieve higher storage density. Until now, single event cell upset (SCU) in SRAM is a major source of soft errors. Soft errors in integrated circuits are mitigated by either redundant cell or error detection and correction (EDAC) codes [2]. In order to ensure the reliability of unit operation, certain requirements are put forward for the size. For static random access memory, changes associated with the evolution of the complementary metal oxide semiconductor (CMOS) technology process have had a considerable influence on the irradiation effects due to ionizing effects of particles, ions, and cosmic rays in space and terrestrial environments [3]. As a result, multiple cell upsets (MCUs) and single cell upsets (SCUs) are becoming major issues for the reliability of SRAM [4,5,6,7,8,9,10,11,12,13]. Therefore, radiation hardened technologies in fabrication and design require continued modification to accommodate further scaling down [3]. For the time being, radiation hardened by design (RHBD) of commercial SRAMs is a major hardening method, because it is compatible with the standard commercial CMOS process, and it does not require extra process steps to fabricate integrated circuit (IC) chips [3]. For the 40 nm technology process node, we present a certain layout technique and well engineering that have been used to reduce multiple cell upsets (MCUs) for hardening CMOS SRAMs [14,15,16]. In this paper, carriers are simultaneously collected by adjacent transistor. This mechanism may lead to an upset reversal phenomenon that reduces the particles response of SRAMs [10,17]. This work investigates the effect of layout and well engineering on the single event error rate of SRAM on a 40 nm technology node.

SERs(single event upset error rates) for SRAM are affected by the combination of structural layout, sensitive area per bit, and well engineering. By scaling down, the single event error rate of per memory cell is further reduced by the smaller sensitive area. A smaller distance between cells makes some cells vulnerable to particle strikes, resulting in multiple cell upsets (MCUs). The number of MCUs in SRAMs due to particle striking has increased. At the 40 nm technology node, to take advantage of the single event upset reversal (SEUR) caused by scaling trends, the transistors are separated by a certain distance according to the design rules to reduce multiple cell upsets. The single event responses of full 40 nm custom SRAM need to be studied to understand the factors affecting the SER of SRAMs [18,19,20,21,22]. In the work, a series of simulations and experiments are carried out for 40 nm technology process under irradiation of several particles, such as Ge, Cl, Al, O, and Li, which have different linear energy transfer (LET) values. Experimental data show that the custom SRAM has a lower multiple cell upsets rate for the 40 nm technology node. This work investigates combining the layout with well engineering, which has major effects for the soft error of SRAM. TCAD simulation for a 40 nm technology node demonstrates the change of drains potential of transistors when particles strike. By scaling down, the structural layout and well engineering determine the soft error sensitivity of SRAMs. The combined layout with well engineering plays an important role for single event cell upset [23,24].

SCUs have been researched by experiments and simulations. For single cell upsets, the diffusion of carriers and a parasitic bipolar effect transistor (NPN or PNP), which were proposed by Song and Black, have been widely researched and have been disclosed [16]. Although the features of SCUs in a custom SRAM in 40 nm CMOS technology are widely reported, the effect of the structural layout and single event upset reversal on SCUs is rarely tested [14]. In this work, a full custom SRAM combining well engineering with a vertical well isolation structural layout is fabricated at a 40 nm technology node. Features of single event error rate were widely tested by five heavy particles with different characteristics [18,19,20,21,22].

2. Device Model and I-V Curve Calibration

Sentaurus TCAD from Synopsys was used to model three devices and execute the emulations [15]. In this paper, mixed models were developed for the 40 nm SRAM. A TCAD structure was used for simulations as shown in Figure 1 [10,17]. The 3D view of the three NMOSFET is shown in Figure 1a. The cross-section view of a NMOSFET transistor is shown in Figure 1b. In the layout, a well contains 16 transistors, each of which belongs to a different storage cell [19]. The W/L ratio of the PMOSFET transistor is 0.055/0.06 μm in the SPICE lumped parameter model. The W/L ratio of NMOSFET is 0.055/0.192 μm in the TCAD distributed parameter model.

The TCAD model contained three NMOSFET transistors. These NMOSFET transistors were modeled with 3D digital models and were calibrated according to the commercial process design kits (PDKs) [10,17]. As shown in Figure 2 and Figure 3, the single NMOSFET of SRAM is calibrated according to the commercial PDKs.

The main circuit structure of a SRAM cell is shown in Figure 4. A mixed-mode model was developed using the structure shown in Figure 1. Figure 1 is not convenient to represent the striking schematic diagram, and Figure 5 is used to represent it. The main structure of a SRAM cell is composed of an interlocked inverter pair, such as INV1 and INV2. INV3 replaces another SRAM cell. The basic circuit is emulated in an initial state with MN2 and MP1 being in the OFF state and MN1 and MP2 being in the ON state. MN2 and MN3 can realize carriers sharing collection after particles strike [10,17].

The volume of silicon used for simulations is 5 μm × 5 μm × 5 μm. The incident particles are modeled using a Gaussian radial profile with 0.37 radius of 5 μm.

3. Emulation Voltage Waveform and Experimental Data

The layout, optimized for area at a 40 nm technology node, is used for SRAMs to estimate the single event response of the 40 nm technology node. SRAMs, but from one specific layout manufacturer, were exposed to heavy particles at the HI-13 Tandem Accelerator in the China Institute of Atomic Energy, Beijing. The simplified layouts of the SRAM are shown in 6a. The n- and p-wells are isolated from each other in the layout [19]. Each well is connected by one contact, and one well is placed every 16 rows. The nominal value for the 40 nm technology node is 1.1 V. The SRAM layout is simplified in Figure 6b; specific details are proprietary. Because interleaving techniques significantly increase the layout area, interleaving schemes were not used in the experimental chips.

The test was carried out with five heavy ions (Al, Cl, Ge, Li, and O) for the 40 nm technology node. Particle LET values were from 0.5 to 37.3 MeV cm²/mg. The range of particles in silicon was 30.5–249.9 μm.

Table 1. Parameter of particles.

Particle	Energy (MeV)	LET (Mev/mg/cm2)	Range (μm)	SCU (cm2/Particle)	MCU (cm2/Particle)
Ge	210	37.3	30.5	8.97617E-7	2.69265E-12
Cl	160	13.1	46.0	5.04544E-7	1.7951E-12
Al	120	8.6	50.0	1.85389E-7	0
O	100	3.1	95.2	1.39709E-7	0
Li	44	0.5	249.9	2.14582E-8	0

contains the particle beams, particle LET values, particles energy, ranges in silicon [10,17], probability of single cell upset during single particle striking, and probability of multiple cell upset during single particle striking. In this paper, the particle incident on the drain region of transistor and carriers diffusion is shown in Figure 7. Numerous ionized carriers are generated along the particle track core [16,17].

The distance between two NMOS transistors in the same well is the minimum distance of two NMOS transistors according to the design rules to take advantage of the single event upset reversal (SEUR) caused by scaling trend. As shown in Figure 8, initially, the circuit was simulated with the drain of MN2 HIGH, MN1 LOW, and MN3 HIGH, which results from transistors MN2, MN3, and MP1 being in the OFF state, as well as MP2, MP3, and MN1 being in the ON state.

As shown in Figure 8, a particle strikes the drain central region of the MN2 transistor perpendicularly. The simulation results show the voltage changes at both the drains of MN1 and MN2, as shown in Figure 9. Initially, MN2 is in the OFF state; when it collects charge, the struck transistor (MN2) of inverter INV2 is ON. A series of state changes flips the MN1 in the inverter INV1.

As shown in Figure 10 and Figure 11, the drain central region of transistor MN3 was struck by a particle. The simulation results show the voltage changes for three NMOSFET drains of MN1, MN2, and MN3. At first, the MN2 was in OFF state; when it collected enough carriers, the MN2 in the inverter INV2 was in ON state, and the MN1 in the inverter INV1 switched into the OFF state. As shown in Figure 11, MN1 tried to recover, but the lack of sufficient charge prevented MN1 from reverting back to its initial state. The gate of transistor MN3 was connected to the GND. When the particle struck the drain central region of MN3 in the inverter INV3, MN3 collected carriers, and the output of inverter INV3 changed. After the excess carriers disappeared, the state of MN3 recovered.

SERs for SRAM depend on the critical charge collected by a sensitive node. For all technology processes, the critical charge depends on the technology process and active region doping. The critical charge is inversely proportional to active region doping. To keep a moderate threshold voltage for all technology processes, the channel doping and the well doping are increased with scaling down [10,17]. Thus, the charge collected by the 40 nm process is lower than that of 65 nm and higher than that of 28 nm; meanwhile, the space between transistors is moderate in the 40 nm technology process, and the probability of the MOS transistor collecting enough carriers to mitigate cell upset is beneficial for the 40 nm technology node. The structural layout also plays an important role for single event cell upset, as scaling down, the structural layout, and well engineering determine the soft error rate of SRAMs [10,17].

On the other hand, when a particle with high LET strikes at adjacent sensitive nodes, especially when multiple particles strike at adjacent sensitive nodes at the same time for the 40 nm technology node, the amount of charge available collected by the MN transistor is sufficient to return to the initial state. The space between transistors favors the charge collection [10]. These factors lead to the dominance of the upset reversal mechanism for the 40 nm technology process. As shown in Figure 12 and Figure 13, the drain voltage of MN1 recovered to its original state after MN2 was struck.

A custom SRAM was designed using a 40 nm technology node to verify the rate of single cell upsets and multiple cell upsets, which meets access functions. The chip used for features of single event upset (SEU) was a full custom SRAM, which was made up of four 128 × 32 × 4 × 8 bit blocks, 512 Kb. The experimental chip of SRAM with a 55AA pattern was irradiated using five heavy particles: Ge, Cl, Al, O, and Li. The experiments were carried out at the HI-13 Tandem Accelerator in the China Institute of Atomic Energy, Beijing. This SRAM was accessed at a frequency of 15 MHz, from the first word wire to the last word wire. It took 34 ms to access the test SRAM until the 1 × 10⁷ particles ran out. The number of irradiation particles per accessing cycle was about 4014 ions/cm². The test area of the test SRAM chip was about 2 mm × 2.5 mm. The number of particles striking the chip per accessing cycle was about 200 particles [25]. The captured SCUs and MCUs were recorded after 1 × 10⁷ particles ran out.

When the full custom SRAM was accessed, the storage cells of the same address were accessed at the same time. When a storage cell upset was detected, the error was corrected through EDAC. After the last address was accessed, a new cycle was performed from the first address to the last address until the completion of 1 × 10⁷ particle strikes.

The field programmable gate array was responsible for the execution of the tests applied for SRAM. A computer was connected to the field programmable gate array in order to access the experimental data. The computer was located outside the radiation room. Experimental data were timely recorded and saved for subsequent processing. The total single cell upset events were 2,000,147, 1,124,269, 413,100, 311,311, and 47,815 under the irradiation of Ge, Cl, Al, O, and Li, respectively; the total multiple cell upset events were 10, 4, 0, 0, and 0 under the irradiation of Ge, Cl, Al, O, and Li, respectively [25]. The upset events decreased with LET decrease, and the multiple cell upsets events also decreased with LETs decrease. Single cell upset error rates under different particle striking are shown in Figure 14; multiple cell upsets are shown in Figure 15. The decreasing trend of the number of multiple cell upsets is attributed to the single event upset reversal, which was observed in the 40 nm technology node. To further reduce single cell upsets, the density of the well contact increased the maximum design density in the custom SRAM [20,21].

4. Conclusions

In this work, the feature of single cell upset in the full custom SRAM was carried out for a 40 nm bulk CMOS technology. The effect of structural layout and well engineering on single cell upset was researched and discussed on single event upset reversal under heavy particles exposure. The total single cell upset events were 2,000,147, 1,124,269, 413,100, 311,311, and 47,815 under the irradiation of Ge, Cl, Al, O, and Li, respectively. This indicates that single event cell upsets have become a major part of soft errors for the custom SRAM. The total multiple cell upset events were 10, 4, 0, 0, and 0 under the irradiation of Ge, Cl, Al, O, and Li, respectively. The results showed that multiple cell upsets significantly decreased. This indicates that the single event upset reversal mechanism plays a main role in SRAM and can be used for radiation hardening design. Moreover, there are a lot of single cell upsets appearing under Ge, Cl, Al, O, and Li exposure, the number may further increase with LETs increase. This shows that the well contacts still need optimization in the custom SRAM; for example, close spacing of well contacts or increasing contacts were used to drain the excess carriers quickly, and error detection and correction (EDAC) is used for SRAM technology. New radiation hardened by design techniques of SRAM need to be further proposed for single cell upset reduction, and the research on reduction techniques of SCUs continues in our group.