Single DC Source Multilevel Inverter with Changeable Gains and Levels for Low-Power Loads

Abstract

Different types of multilevel converters have been used to convert DC voltage to AC voltage for different applications. It is, however, desirable for flexible AC output voltage to be created from a single DC source at lower cost. This paper presents a new type of single DC source multilevel inverter which has the ability to create a different number of levels with low rate components. This device is also able boost the magnitude of the output voltage by means of a variable gain with one DC source. The advantages of the multilevel inverter are rapid stepping among levels, and its ability to produce different ranges of levels (seven, nine and eleven) and gains (two, four and eight). The proposed multilevel inverter includes six semiconductor switches, eight diodes, two capacitors and two inductors, making it suitable for low-power applications. A simulation in MATLAB and experimental tests on a prototype setup showed good performance for different modulations, with THD% down to 2.29%, which are meets the IEEE standard (IEEE 519).

1. Introduction

Multilevel inverters (MLIs) have been used in various applications as voltage source converters (VSC) to connect DC power systems to AC power systems. MLIs include an array of semiconductors and DC sources to generate different output voltage levels with high quality waveforms. Low harmonic contents, high resolution on the output voltage and scalability make this kind of inverter more suitable in comparison with traditional two-level inverters for energy conversion applications such as photovoltaic systems [1], HVDC [2,3], wind turbines [4], active power filers [5], drives systems [6,7], electrical vehicles [8] and power grids [9]. Multilevel inverters are classified into three well-known topologies that have been used in various industries: Neutral Point Clamped (NPC) [10], Flying Capacitor (FC) [11] and Cascade H-bridge (CHB) [12]. CHB topologies are gaining attention due to certain aspects, such as simpler control strategy, scalability, the number of levels, the number of semiconductors, etc. However, classical topologies require a large number of components to increase the number of output voltage levels. Circuit complexity, complicated voltage control strategies and higher manufacturing costs are expected when the number of components increases. Nevertheless, creating more voltage levels with fewer components and DC sources is an important objective for newer multilevel inverter topologies [13,14,15,16]. In [17], a structural review and comparative study of all categories of Multilevel Inverters are presented.

In [18], a series connection of modules consisting of one DC source and two switches was introduced. The output voltage is generated by the sum of each module’s output voltage. The module can only generate zero and positive voltage levels. An H-bridge was added at the end of the series module in [19] to create both negative and positive levels. Also, the module has a simple circuit and control strategy, and the stress on the switches is low compared with conventional CHBs. On the other hand, a large number of cascade connections to generate higher output voltage levels can increase the complexity and construction cost. A similar structure with an H-bridge at the end of the module was introduced in [20]. It is used a diode instead of a switch by [21], as the number of switches decreased in this way. The number of required electronic switches and DC sources are a key factor in designing MLIs, because the circuit size, cost, installation area and control complexity depend on them. Compared with other modules, the device described in [22] can generate more voltage levels with fewer switches. However, the cost of using several DC sources still remains high. Another type of MLI using crossing switches to oppose the polarity of DC links was introduced in [23,24] to generate more levels. The authors of [25,26] introduced modules with few semiconductors in order to achieve maximum levels from four DC sources. Recently, different storage elements such as capacitors have been mixed with DC sources to provide a sinusoidal voltage source in various multilevel inverter structures and increase the output voltage levels with the same number of DC sources. The authors of [27,28] redesigned the configuration of [11,23], replacing some DC sources with capacitors and increasing the number of voltage levels. Some configurations with mixed DC sources and capacitors were proposed in [29,30]. A new topology with only one DC source is presented in [31]. The authors of [32] redesigned the configuration of [31], removing some switches and replacing them with diodes. In some modules that use a single source to generate output levels, the number of semiconductors increased, and the charging/discharging of capacitors and switch driving become complicated [31,33]. Also, the authors of [34] replaced half of the DC sources used in [25,26] with capacitors, and rearranged the semiconductor configuration to present a new multilevel inverter with fewer DC sources.

In this paper, a flexible multilevel inverter for one DC source is proposed which can create a different number of levels and voltages at the output for low-power applications. The main core of the proposed module is a new type of DC–DC converter to change the levels very quickly by a variable duty cycle, in order to create a staircase waveform. The main converter should be rapid with a tiny transient time, and have the ability to create all voltage levels; otherwise, it can produce high harmonics and destroy the staircase waveform. The other part of the proposed inverter is a full-bridge converter (H-bridge) to evenly produce the positive and negative half-cycles of a sinusoidal waveform. The proposed multilevel inverter has the ability to create up to 11 levels and boost the output voltage up to 8 times compared to the DC source. The proposed multilevel inverter is illustrated in Section 2. The modular configuration, switching patterns, equations, and a comparative study with conventional inverters are included in this section. In Section 3, the calculations for the switching pattern and duty cycle for a different number of levels and different gains are presented. Finally, the simulation and experimental results are presented for nine different cases (number of levels = 7, 9 and 11 versus gain = 2, 4 and 8) in Section 4 and Section 5.

2. The Proposed Multilevel Inverter

Figure 1 shows the proposed multilevel inverter, which is divided into two parts: the main converter and the full-bridge converter. The main converter provides the levels, and the full-bridge converter changes the polarity of output. The main converter is very fast and comprises a high gain DC–DC converter with good dynamic reactivity to changes in the duty cycle. Each level of output can be achieved in the specified amount of the duty cycle. On the other hand, the duty cycle must be set to a certain number, which is calculated in lookup tables (

Table 1. Switching table level = 11, gain = 8.

Voltage Level		Duty Cycle S1 (%)	Duty Cycle S2 (%)	S3	S4	S5	S6
Positive Level	8 VDC	74	74	1	0	0	1
	6.66 VDC	72	72	1	0	0	1
	5.66 VDC	69	69	1	0	0	1
	4 VDC	66	66	1	0	0	1
	1.66 VDC	56	56	1	0	0	1
Zero Level	0	0	0	1	0	1	0
	0	0	0	0	1	0	1
Negative Level	−1.66 VDC	56	56	0	1	1	0
	−4 VDC	66	66	0	1	1	0
	−5.66 VDC	69	69	0	1	1	0
	−6.66 VDC	72	72	0	1	1	0
	−8 VDC	74	74	0	1	1	0
Num. of turning on per 1-cycle		20,000	20,000	1	1	2	2

,

Table 2. Switching table level = 11, gain = 4.

Voltage Level		Duty Cycle S1 (%)	Duty Cycle S2 (%)	S3	S4	S5	S6
Positive Level	4 VDC	66	66	1	0	0	1
	3.33 VDC	64	64	1	0	0	1
	2.83 VDC	62	62	1	0	0	1
	2 VDC	58	58	1	0	0	1
	0.84 VDC	47	47	1	0	0	1
Zero Level	0	0	0	1	0	1	0
	0	0	0	0	1	0	1
Negative Level	−0.84 VDC	47	47	0	1	1	0
	−2 VDC	58	58	0	1	1	0
	−2.83 VDC	63	63	0	1	1	0
	−3.33 VDC	72	72	0	1	1	0
	−4 VDC	66	66	0	1	1	0
Num. of turning on per 1-cycle		20,000	20,000	1	1	2	2

,

Table 3. Switching table level = 11, gain = 2.

Voltage Level		Duty Cycle S1 (%)	Duty Cycle S2 (%)	S3	S4	S5	S6
Positive Level	2 VDC	58	58	1	0	0	1
	1.66 VDC	56	56	1	0	0	1
	1.41 VDC	54	54	1	0	0	1
	1 VDC	50	50	1	0	0	1
	0.42 VDC	39	39	1	0	0	1
Zero Level	0	0	0	1	0	1	0
	0	0	0	0	1	0	1
Negative Level	−0.42 VDC	39	39	0	1	1	0
	−1 VDC	50	50	0	1	1	0
	−1.41 VDC	54	54	0	1	1	0
	−1.66 VDC	56	56	0	1	1	0
	−2 VDC	58	58	0	1	1	0
Num. of turning on per 1-cycle		20,000	20,000	1	1	2	2

,

Table 4. Switching table level = 9, gain = 8.

Voltage Level		Duty Cycle S1 (%)	Duty Cycle S2 (%)	S3	S4	S5	S6
Positive Level	8 VDC	74	74	1	0	0	1
	5.83 VDC	70	70	1	0	0	1
	3.33 VDC	64	64	1	0	0	1
	1.66 VDC	56	56	1	0	0	1
Zero Level	0	0	0	1	0	1	0
	0	0	0	0	1	0	1
Negative Level	−1.66 VDC	56	56	0	1	1	0
	−3.33 VDC	64	64	0	1	1	0
	−5.83 VDC	70	70	0	1	1	0
	−8 VDC	74	74	0	1	1	0
Num. of turning on per 1-cycle		20,000	20,000	1	1	2	2

,

Table 5. Switching table level = 9, gain = 4.

Voltage Level		Duty Cycle S1 (%)	Duty Cycle S2 (%)	S3	S4	S5	S6
Positive Level	4 VDC	66	66	1	0	0	1
	2.91 VDC	63	63	1	0	0	1
	1.66 VDC	56	56	1	0	0	1
	0.84 VDC	47	47	1	0	0	1
Zero Level	0	0	0	1	0	1	0
	0	0	0	0	1	0	1
Negative Level	−0.84 VDC	47	47	0	1	1	0
	−1.66 VDC	56	56	0	1	1	0
	−2.91 VDC	63	63	0	1	1	0
	−4 VDC	66	66	0	1	1	0
Num. of turning on per 1-cycle		20,000	20,000	1	1	2	2

,

Table 6. Switching table level = 9, gain = 2.

Voltage Level		Duty Cycle S1 (%)	Duty Cycle S2 (%)	S3	S4	S5	S6
Positive Level	2 VDC	58	58	1	0	0	1
	1.45 VDC	55	55	1	0	0	1
	0.84 VDC	47	47	1	0	0	1
	0.42 VDC	39	39	1	0	0	1
Zero Level	0	0	0	1	0	1	0
	0	0	0	0	1	0	1
Negative Level	−0.42 VDC	39	39	0	1	1	0
	−0.84 VDC	47	47	0	1	1	0
	−1.45 VDC	55	55	0	1	1	0
	−2 VDC	58	58	0	1	1	0
Num. of turning on per 1-cycle		20,000	20,000	1	1	2	2

,

Table 7. Switching table level = 7, gain = 8.

Voltage Level		Duty Cycle S1 (%)	Duty Cycle S2 (%)	S3	S4	S5	S6
Positive Level	8 VDC	74	74	1	0	0	1
	5.41 VDC	69	69	1	0	0	1
	2.5 VDC	61	61	1	0	0	1
Zero Level	0	0	0	1	0	1	0
	0	0	0	0	1	0	1
Negative Level	−2.5 VDC	61	61	0	1	1	0
	−5.41 VDC	69	69	0	1	1	0
	−8 VDC	74	74	0	1	1	0
Num. of turning on per 1-cycle		20,000	20,000	1	1	2	2

,

Table 8. Switching table level = 7, gain = 4.

Voltage Level		Duty Cycle S1 (%)	Duty Cycle S2 (%)	S3	S4	S5	S6
Positive Level	4 VDC	66	66	1	0	0	1
	2.70 VDC	62	62	1	0	0	1
	1.25 VDC	52	52	1	0	0	1
Zero Level	0	0	0	1	0	1	0
	0	0	0	0	1	0	1
Negative Level	−1.25 VDC	52	52	0	1	1	0
	−2.70 VDC	62	62	0	1	1	0
	−4 VDC	66	66	0	1	1	0
Num. of turning on per 1-cycle		20,000	20,000	1	1	2	2

and

Table 9. Switching table level = 7, gain = 2.

Voltage Level		Duty Cycle S1 (%)	Duty Cycle S2 (%)	S3	S4	S5	S6
Positive Level	2 VDC	58	58	1	0	0	1
	1.35 VDC	53	53	1	0	0	1
	0.62 VDC	44	44	1	0	0	1
Zero Level	0	0	0	1	0	1	0
	0	0	0	0	1	0	1
Negative Level	−0.62 VDC	44	44	0	1	1	0
	−1.35 VDC	53	53	0	1	1	0
	−2 VDC	58	58	0	1	1	0
Num. of turning on per 1-cycle		20,000	20,000	1	1	2	2

). Nevertheless, the duty cycle was changed in one cycle continuously to create different levels in the multilevel inverter. Then, the full-bridge converter changes the polarity for each half-cycle from the positive or negative half-cycles. Figure 2 illustrates this issue with an example for eleven levels on the output.

The duty cycle of each level for S1 and S2 are calculated (according to Section 3) and shown in Figure 2. The states for S3, S4, S5, and S6 to create the polarity of the output are also shown.

In order to demonstrate the detail and performance, Figure 3 depicts the two modes (on/off) for the main converter part. It is noticeable that S1 and S2 switch on and off, simultaneously.

On mode: S1 and S2 are in an on state, and D0 and D1 are in reverse bias (Figure 3a). On the other hand, switches S1 and S2 conduct the current to magnetize L1 and L2, respectively. And C0 and C1 are discharged to the output. Then:

$$V_{L1}=V_{in}$$

(1)

$$V_{L2}=V_{in}+V_{C1}$$

(2)

Off mode: S1 and S2 are turned off, and D0 and D1 are conducting in forward bias (Figure 3b). L1 and L2 demagnetize to charge C0 and C1, respectively, and supply output. Thus:

$$V_{L1}=-V_{C1}$$

(3)

$$V_{L2}=-\left(V_{C1}+V_0\right)$$

(4)

Figure 4 demonstrates the behavior of the components in the two modes.

From (1) and (3) and balancing in L1:

$$D{V}_{in}+\left(1-D\right)\left(-D{V}_{C1}\right)=V_{L1}=0$$

(5)

Then

$$V_{C1}=\frac{D}{1-D}{V}_{in}$$

(6)

Also, from (2) and (4),

$$D(V_{in}+V_{C1})+\left(1-D\right)(-(V_{C1}+V_o)=V_{L2}=0$$

(7)

Consequently,

$$\frac{V_0}{V_{in}}={\left(\frac{D}{1-D}\right)}^2$$

(8)

Equation (8) provides the formula to calculate the duty cycle which creates the levels. The duty cycles for each level and each gain according to (8) will be presented in Section 3.

A comparative study between the proposed multilevel inverter and some other configurations in cases of producing 11 levels of output voltage is shown in Figure 5. In order to make a suitable comparison, various aspects, such as the number of switches, the number of diodes, the number of DC sources and TSV, were considered.

According to Figure 5, the proposed module can get maximum levels with fewer DC sources. As a comparison only in the case of the number of DC sources, [31,32] require the same number of DC sources, but the number of switches should be considered. One of the major advantages of the proposed module is that it uses fewer switches. On the other hand, the module can be considered as being in the group with a low number of diodes. The complexity of the module is reduced by using diodes instead of switches. Since the module is intended for use in low-power applications, the range of TSV is reasonable, as can be seen in Figure 5.

3. Calculation of the Switching Pattern and Duty Cycle

The proposed multilevel inverter is divided into two parts, as mentioned above: the DC–DC converter and the full-bridge. In the DC–DC converter, the number of levels can be achieved by controlling the duty cycles. Thus, the duty cycle should be changed continuously to create each level and a staircase waveform in one cycle of a sinusoidal waveform. In the full-bridge, the switching modes should be set to alternatively change the polarity of the half-cycle. The duty cycle and switching pattern are calculated for levels 7, 9 and 11 and gains 2, 4 and 8. Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9 illustrate the calculation of the switching pattern and duty cycle according to Equation (8). S3 and S6 are for positive levels and S4 and S5 are for negative levels, which have a low frequency (up to 100 Hz); S1 and S2 are used to set a duty cycle with 20 kHz.

The nearest level control method (NLC) was also considered as a switching technique for level timing, as presented in [35]. This technique is a very simple means by which to reduce the number of calculations in the processor. The modulation scheme and the control diagram are shown in Figure 6. According to Figure 6a, the controller gets a sample from the reference voltage (Vref) and then rounds it to the nearest voltage level (VaN). Each voltage level has a switching table according to the information in Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9 to change switch modes and duty cycles (Figure 6b). The sampling is repetitive for each sample time (Ts).

4. Simulation Results

A simulation was carried out to evaluate the proposed multilevel inverter at different outputs. The specifications of the simulation are shown in

Table 10. Simulation configuration.

Switches	IGBT
Diodes	Diode
Inductors	L1 = 50 μH	L2 = 250 μH
Capacitors	C0 = 2 μF	C1 = 1 μF
DC Source	36 V
Load	500 Ω

. The aim of the simulation test was to produce a sinusoidal waveform of 50 Hz from one DC source at 36 volts.

Nine output conditions were considered for the waveforms. The output levels were set for seven, nine and eleven, along with three different gains (output voltage amount/input voltage amount), i.e., two, four and eight. Figure 7 summarizes the nine simulation setups. The simulation results showed the ability of the proposed circuit to create different waveforms with sinusoidal output voltages.

5. Experimental Results

A prototype setup was implemented in the laboratory to verify the performance of the proposed single source multilevel inverter with flexible levels and gains. Figure 8 provides a picture of the experimental setup in the laboratory. The specifications of the prototype setup are given in

Table 11. Specifications of the prototype setup configuration.

Switches	IGBT FGH60N60SFD (S1,S2) (S3,S4,S5,S6) IGBT IKW40N120H3
Diodes	RHRP15120
Inductors	L1 = 50 μH	L2 = 250 μH
Capacitors	C0 = 2 μF	C1 = 1 μF
DC Source	12 V
Optocoupler	HCPL3120
Microcontroller	ATmega32A
Buffer	7404
Load	500 Ω

. An experimental test was also carried out on nine cases (the number of levels for 7, 9 and 11 versus gains for 2, 4 and 8) to generate a sinusoidal waveform of 50 Hz from one DC source at 12 volts.

Figure 9 shows the voltages and currents of the proposed inverter with nine different outputs. It should be mentioned that the THD% of all the waveforms meets the IEEE standard (IEEE 519), in that they are under 8%. The THD% is shown in

Table 12. THD% of voltages for nine outputs.

7Levels, Gain 2	6.61
7Levels, Gain 4	6.70
7Levels, Gain 8	6.82
9Levels, Gain 2	4.88
9Levels, Gain 4	4.77
9Levels, Gain 8	5.27
11Levels, Gain 2	2.08
11Levels, Gain 4	2.28
11Levels, Gain 8	2.29

. The worst THD% was 6.82% and the best was 2.08%.

The proposed multilevel inverter (with few components and one DC source) is economical, with good output voltage for low-power applications. It can create different voltage levels for different voltages with just one DC source. Also, a low number of harmonics make it especially promising.

Figure 10 illustrates the voltages and currents of the switches and diodes in the proposed inverter.

Finally, the voltage and current of the capacitors and inductors are depicted in Figure 11.

6. Conclusions

A new kind of multilevel inverter for low-power applications, operating from one DC source, was introduced in this paper. The proposed inverter has the ability to produce different levels of output, i.e., up to 11 levels, and to increase the output voltage by up to eight times compared to the input voltage. It also has flexible levels and gains. The circuit of the proposed inverter comprises six semiconductor switches, eight diodes, two capacitors and two inductors, i.e., a low number of components for a multilevel inverter. These components are organized into two parts: the main converter and the full-bridge converter. The main converter is involved in fast DC–DC conversion, with a tiny transient time to create levels and gains by changing the duty cycle according to different strategies. Meanwhile, the full-bridge changes the polarities for the positive and negative half-cycles. Verification of the proposed inverter was carried out in a simulation and in experimental tests using nine different modulations. The device was shown to produce three level modes for 7, 9 and 11, and three gain modes for 2, 4 and 8. The simulation and experimental results showed a high level of performance for all the test cases; the THD% was shown to be between 2.08% and 6.82% (in the permitted range of the IEEE 519 standard). The illustrated features of the proposed inverter make it suitable for single DC sources in low-power applications.