FPGA Implementation of Sliding Mode Control and Proportional-Integral-Derivative Controllers for a DC–DC Buck Converter

Abstract

DC–DC buck converters have been designed by incorporating different control stages to drive the switches. Among the most commonly used controllers, the sliding mode control (SMC) and proportional-integral-derivative (PID) controller have shown advantages in accomplishing fast slew rate, reducing settling time and mitigating overshoot. The proposed work introduces the implementation of both SMC and PID controllers by using the field-programmable gate array (FPGA) device. The FPGA is chosen to exploit its main advantage for fast verification and prototyping of the controllers. In this manner, a DC–DC buck converter is emulated on an FPGA by applying an explicit multi-step numerical method. The SMC controller is synthesized into the FPGA by using a signum function, and the PID is synthesized by applying the difference quotient method to approximate the derivative action, and the second-order Adams–Bashforth method to approximate the integral action. The FPGA synthesis of the converter and controllers is performed by designing digital blocks using computer arithmetic of 32 and 64 bits, in fixed-point format. The experimental results are shown on an oscilloscope by using a digital-to-analog converter to observe the voltage regulation generated by the SMC and PID controllers on the DC–DC buck converter.

1. Introduction

Among the currently available power converters [1], DC–DC buck converters are commonly considered in the development of power applications because they provide high efficiency from a relatively simple circuitry. The most simple topology of the DC–DC buck converter consists of six elements that are described in the following section. The DC–DC converter must guarantee a desired voltage ($V_d$) that is taken as the reference to be reached by the output ($v_{out}$). This task requires the appropriate design of a controller to reduce the error ($e\left(t\right)=V_d-v_{out}$). In addition, the design of a controller for the converter must also mitigate overshoot, reduce settling time and increase slew rate. One of the controllers that are case studies in the proposed work is the well-known sliding mode control (SMC), the control law of which is taken from [2], where the authors showed the voltage regulation of a DC–DC buck converter accomplishing fast dynamic response, small steady-state output error, and practically zero overshoot.

As recently shown by the authors in [3], time simulation is a good option to enhance the response of a controller for a converter. Continuing in this direction, the proposed work applies time simulation methods to approximate the solution of the ordinary differential equations (ODEs) that are modeling the buck converter. The other reason is that the application of numerical methods to solve ODEs is also helpful to synthesize discretized equations on a field-programmable gate array (FPGA) device, as detailed in the proposed work. Interested researchers can read related works that perform the simulation of DC–DC converters by applying numerical methods, as described in [4,5,6,7].

The design of SMC controllers requires the definition of a sliding surface, which, in this case, is based on the sign() function, which is synthesized on the FPGA by approximating the error, as detailed in the following sections. Another well-known controller that is considered in the proposed work, just to show the FPGA synthesis and the response when controlling a DC–DC buck converter, is the proportional-integral-derivatve (PID) controller [8,9,10]. In a real application, a PID controller has the challenge of performing a correct tuning of the gains associated to the proportional $K_p$, integral $K_i$, and derivative $K_d$ actions [11,12,13]. In this manner, the emulation of a DC–DC buck converter along its controller, like SMC or PID, can be performed on an FPGA board. In fact, this emulation case can also be performed within the topic known as hardware-in-the-loop (HIL) [3]. Actually, HIL is a fundamental component of the power electronics control design cycle, and it includes the use of FPGAs. For instance, the authors in [14,15] provide examples on the use of HIL associating time-simulation methods. Therefore, and as one can infer, the HIL and FPGA implementations require the knowledge of numerical methods. Henceforth, this work shows the application of an explicit multi-step method to solve the model of the buck converter, which is controlled by SMC and PID blocks that are simulated by applying numerical methods to allow their synthesis into an FPGA.

The rest of the manuscript is organized as follows. Section 2 shows the DC–DC buck converter topology, the equivalent model consisting of two ODEs, and the numerical method to solve the equations. Section 3 shows the numerical methods that are applied to simulate SMC and PID controllers. Section 4 shows the FPGA emulation of the DC–DC buck converter and the FPGA synthesis of the SMC and PID controllers. Section 5 gives the hardware resource consumptions by using the FPGA Cyclone® IV EP4CGX150DF31C7N, and shows experimental results of the converter using SMC and PID controllers for output voltage regulations of 2.5, 3.3, and 4.1 volts. Finally, the conclusions are summarized in Section 6.

2. DC–DC Buck Converter

Power electronics offer a variety of converter topologies that are suitable for different applications [1]. Among the DC–DC converters that provide a regulated voltage with a lower value than that from a given input, one can find the well-known buck converter, which is a switched-mode regulator that performs DC–DC conversion with good efficiency. The design of a DC–DC buck converter is relatively simple, with an ease mode of use. It consists of simple circuit elements, and in most cases it is the cheaper solution. The DC–DC buck converter topology consists of six elements, namely: an independent DC voltage supply (E), a switch ($u\left(t\right)$), a diode (D), a capacitor (C), an inductor (L), and a resistor (R) that may also be considered as the load. These six electrical circuit elements of the buck converter are connected as shown in Figure 1, where one can see that the regulated output voltage ($v_{out}$) is taken from the parallel connection of the $RC$ elements.

The output voltage $v_{out}$ of the buck converter must be controlled to provide a desired voltage ($V_d$). In this case, $v_{out}$ can be varied by controlling the switch, which can be replaced by a power transistor that has ON–OFF control, or a more complex control stage such as pulse-wide modulation. The model of the converter shown in Figure 1 has two conduction modes: continuous conduction mode (CCM) and discontinuous conduction mode (DCM), which are better described in [8,9]. In the proposed work, the CCM mode is adopted, which can be modeled by the system of ODEs given in (1).

$$\begin{array}{cc}{\dot{i}}_L& =-{\displaystyle \frac{V_C}{L}}+{\displaystyle \frac{E}{L}}u\left(t\right),\\ {\dot{V}}_C& ={\displaystyle \frac{i_L}{C}}-{\displaystyle \frac{V_C}{RC}}.\end{array}$$

(1)

From the model given in (1), when the control signal makes the action to turn ON or to close the switch, i.e., $u\left(t\right)=1$, the diode is reverse biased and the inductor current has a positive and finite value and when the switch is turned OFF, i.e., $u\left(t\right)=0$, the diode conducts, so that the current through the inductor is uninterrupted between the switch cycles ON and OFF. As a result, in CCM, the inductor current increases and decreases during ON and OFF times of the switch, which, in the proposed work, are manipulated by the SMC [2,16,17,18,19] or PID [8,9,10,11,12,13] controllers.

The remaining sections use the ODEs given in (2), which basically make a change of variables from (1), where the current state variable is updated to $x_1=i_L$ and the voltage state variable to $x_2=V_C$. As the output $v_{out}$ is associated to $V_C$, it also belongs to $x_2$.

$$\begin{array}{cc}{\dot{x}}_1& =-{\displaystyle \frac{1}{L}}{x}_2+{\displaystyle \frac{E}{L}}u\left(t\right),\\ {\dot{x}}_2& ={\displaystyle \frac{1}{C}}{x}_1-{\displaystyle \frac{1}{RC}}{x}_2.\end{array}$$

(2)

The system of ODEs given in (2) has the form of an initial value problem $\dot{x}=f(x,t)+u\left(t\right)$, which requires initial conditions to obtain a solution. The theory on numerical methods can be found in [20,21], where one can find explicit and implicit ones. In the proposed work, the solution to (2) is performed by applying the second order Adams–Bashforth (AB2) method, which is an explicit multi-step method whose iterative equation is given as follows:

$$x_{n+1}=x_n+h\left\{{\displaystyle \frac{3}{2}}f(x_n,t_n)-{\displaystyle \frac{1}{2}}f(x_{n-1},t_{n-1})\right\},$$

(3)

where h is the time step.

3. SMC and PID Controllers

This section describes the selection of parameters of the SMC and PID controllers, and their simulation with numerical methods that will be used to perform the FPGA synthesis in the following section.

3.1. SMC Controller

The model of the DC–DC buck converter given in (2) can be described with a unified state-space formulation in the form of a bilinear system, so that it can be adapted to have the form given in (4).

$$\dot{x}=Ax+u\left(t\right)Bx.$$

(4)

As already shown in [2], the design of the SMC controller can be developed by considering a discontinuous control of the form given in (5),

$$u\left(t\right)={\displaystyle \frac{1}{2}}(1-\mathrm{sign}\left(s\right)),$$

(5)

where s is the scalar switched function defined in the sliding mode theory and the signum function of a real number w, which is a piecewise function that is defined by (6).

$$\mathrm{sign}\left(w\right)=\left\{\begin{array}{cc}-1,& w<0\\ 0,& w=0\\ 1,& w>0\end{array}\right.$$

(6)

As the target of the controller is to provide a constant voltage output $v_{out}$, equal to the desired one $V_d$, then the DC–DC buck converter must be controlled to be in steady state. This can be accomplished through the condition that $x_2=V_d$, and since the desired voltage $V_d$ is a constant value, then ${\dot{x}}_2=0$. For the sliding mode to exist in the manifold $s=0$, it needs to satisfy the sliding condition $s\dot{s}<0$.

As $x_1$ in ${\dot{x}}_2$ can be considered to be an input control, then the desired current can be denoted as $x_1^{*}$. However, $x_1$ can be expressed in terms of $x_2$ in order to control the voltage output. This means that the desired current can be expressed by (7),

$$x_1^{*}={\displaystyle \frac{V_d}{R}}.$$

(7)

The SMC requires the definition of a surface s, which can be described by ensuring that $x_1$ tracks the desired current, and therefore, it must accomplish (8),

$$s_1=x_1-x_1^{*}\to 0.$$

(8)

In this manner, when $s=0$, the current is in a stable point and the voltage loop is in equilibrium when (9) is accomplished.

$$s_2=x_2-V_d\to 0.$$

(9)

In [2], the design of the SMC includes both sliding surfaces (8) and (9), meaning that (5) can be applied to both the current and voltage surfaces to obtain (10),

$$s=\alpha s_1+\beta s_2.$$

(10)

The exponential convergence of the state variables can be achieved by driving the proposed sliding surface s, given in (10), to zero in finite time by means of the control law that is already given in (5). Afterwards, with the goal of forcing the sliding surface during the condition $s=0$, the control $u\left(t\right)$ is restricted to take values of 1 or 0. This can be accomplished by deriving a relationship between the compensation parameters $\alpha$ and $\beta$. As a result, the sliding mode locally exists on s = 0, if (11) is satisfied [2]. In the proposed work, the FPGA synthesis of the SMC is performed by considering the compensation parameters $\alpha =500$ and $\beta =1$. In fact, other values of $\beta$ generate unsuitable behaviors, as shown in Figure 2.

$$\beta <0.0051\alpha$$

(11)

3.2. PID Controller

Different to the SMC described above, this subsection shows the simulation of the PID controller to be suitable for FPGA synthesis. The design of a PID controller is quite popular due to its simplicity, affordable cost, and suitable efficiency for power converters [22]. Basically, the PID controller is defined as the weighted linear combination of tracking error, derivative of error, and integral of error in the state variables space. The PID controller acts on the error between the set point or desired value $V_d$ and the current value of the state variable $x_2=v_{out}$, which is taken as the output, and does not require internal state measurements. The PID controller executes three actions, and therefore it consists of three gain coefficients, namely: proportional $K_p$, integral $K_i$, and derivative $K_d$ ones, and its mathematical model is given in (12),

$$u\left(t\right)=K_{p}e\left(t\right)+K_i\int e\left(t\right)+K_d\dot{e}\left(t\right),$$

(12)

where $e\left(t\right)$ is the error being controlled and for the DC–DC buck converter, it is defined as,

$$e\left(t\right)=V_d-v_{out}=V_d-x_2.$$

(13)

To perform the FPGA synthesis of the PID controller, the numerical approximation of the integral action is calculated by applying the explicit second order Adams–Bashforth (AB2) method given in (3). The numerical approximation of the derivative action is calculated by applying the difference quotient, which in single-variable calculus, the method is given in (14),

$${\displaystyle \frac{f(x+h)-f\left(x\right)}{h}},$$

(14)

where h is the step-size that must be equal to the one used by the AB2 method given in (3).

4. FPGA Implementation of the SMC and PID Controllers for a DC–DC Buck Converter

Recent works, such as the ones introduced by the authors in [23,24], show the fast prototyping of SMC controllers using an FPGA. The authors in [25] show the FPGA implementation of a PID controller, and very recently, the authors in [26] introduced a review on the FPGA implementation of PID controllers. These recent works do not show the FPGA implementation of neither SMC nor PID controllers for a converter. Henceforth, this section introduces the FPGA implementation of SMC and PID controllers for the DC–DC buck converter described in Section 2. In both cases, the converter is emulated into the FPGA by using the circuit values listed in

Table 1. Circuit element values of the DC–DC buck converter shown in Figure 1.

Component	Definition	Value
E	Supply voltage	5 V
$V_d$	Desired voltage	3.3 V
R	Resistor	75 $\Omega$
L	Inductor	20 mH
C	Capacitor	100 μF

.

The parameter values of the controllers are taken from the work [2] to perform the FPGA synthesis of the SMC, while the parameters of the PID controller were tuned by the authors. In this manner, the parameter values are given in

Table 2. Parameter values of the SMC and PID controllers for the DC–DC buck converter.

Controller	Parameter	Value
PID	$K_p$	8.3413
	$K_i$	22.7361
	$K_d$	0.0086
SMC	$\alpha$	500
	$\beta$	1

.

4.1. FPGA Implementation of the SMC Controller

The emulation of the DC–DC buck converter is performed by applying the AB2 method given in (3), which requires the selection of a step-size h to guarantee convergence; in this case, it is set to $h=0.00001$.

The simulation of the SMC is based on (5), whereby combining (7), (8), and (9), then (10) can be updated to,

$$s=\alpha (x_1-(V_d/R))+\beta (x_2-V_d).$$

(15)

The scalar switched function s given in (15), and is used to evaluate the response of the SMC according to (5), so that depending on the signum function defined by (6), the controller can take the following values: $u\left(t\right)$ = 1 if, after evaluating (15), $s<0$; $u\left(t\right)$ = 0.5 if $s=0$; and $u\left(t\right)$ = 0 if $s>0$.

The digital design of the SMC and the converter are carried out by using computer arithmetic of 32 and 64 bits. Looking at the parameter values given in Table 1 and Table 2, one can see that the maximum value is for $\alpha$ = 500, so that this integer number can be represented by using 9 bits. Therefore, by using 32 bits, the fixed-point format can be expressed as 1:9:22, as distributed in

Table 3. Distribution of the fixed-point format for the FPGA synthesis of the SMC controller using 32 bits.

Sign	Integer	Decimal
1 bit	9 bits	22 bits
0	000000000	0.0000000000000000000000

. This implies that one can ensure a resolution of about $2.38418579101562\times {10}^7$. A better resolution can be accomplished by using 64 bits, where the fixed-point format can be expressed as 1:9:54.

The synthesis of the equations for the converter and SMC require some manipulations to identify the best way to perform a block description. As the synthesis is developed by using a step-size of $h=0.00001$ and the AB2 method in (3), then the discretized and reduced expressions for the state variables are given as follows.

In the discretization of the state variable ${\dot{x}}_1$ from (2), it is now called $x{1}_{n+1}$ and the variables $x_1$ and $x_2$ are updated to $x{1}_n$ and $x{2}_n$. Therefore, from the first equation in (2): ${\dot{x}}_1=-{\displaystyle \frac{1}{L}}{x}_2+{\displaystyle \frac{E}{L}}u\left(t\right)$, after applying the AB2 method given in (3), and by using the values of the parameters, the discretized state variable is updated to

$$\begin{array}{cc}\hfill x{1}_{n+1}& =x{1}_n+{\displaystyle \frac{3h}{2}}\left[-{\displaystyle \frac{1}{L}}x{2}_n+{\displaystyle \frac{E}{L}}u\left(t\right)\right]-{\displaystyle \frac{h}{2}}\left[-{\displaystyle \frac{1}{L}}x{2}_{n-1}+{\displaystyle \frac{E}{L}}u\left(t\right)\right]\hfill \\ \hfill x{1}_{n+1}& =x{1}_n-0.00075x{2}_n+0.00025x{2}_{n-1}+0.0005Eu\left(t\right)\hfill \\ \hfill x{1}_{n+1}& =x{1}_n-Ax{2}_n+Bx{2}_{n-1}+CEu\left(t\right)\hfill \end{array}$$

(16)

In (16), the parameter E is a constant value given in Table 1; however, it is considered a parameter for the FPGA synthesis, as well as the constants $A=0.00075,B=0.00025$, and $C=0.0005$. Doing the same development for the state variable ${\dot{x}}_2$ from (2), it is now called $x{2}_{n+1}$. Therefore, from the second equation in (2), ${\dot{x}}_2={\displaystyle \frac{1}{C}}{x}_1-{\displaystyle \frac{1}{RC}}{x}_2$, after applying the AB2 method given in (3), and by using the values of the parameters, the discretized state variable is updated to

$$\begin{array}{cc}\hfill x{2}_{n+1}& =x{2}_n+{\displaystyle \frac{3h}{2}}\left[{\displaystyle \frac{1}{C}}x{1}_n-{\displaystyle \frac{1}{RC}}x{2}_n\right]-{\displaystyle \frac{h}{2}}\left[{\displaystyle \frac{1}{C}}x{1}_{n-1}-{\displaystyle \frac{1}{RC}}x{2}_{n-1}\right]\hfill \\ \hfill x{2}_{n+1}& =0.998x{2}_n+0.15x{1}_n-0.05x{1}_{n-1}+{\displaystyle \frac{1}{1500}}x{2}_{n-1}\hfill \\ \hfill x{2}_{n+1}& =Dx{2}_n+Fx{1}_n-Gx{1}_{n-1}+Jx{2}_{n-1}\hfill \end{array}$$

(17)

In (17), the coefficients of the last equation are also considered parameters, namely: $D=0.998,F=0.15,G=0.05$, and $J=1/1500$. Therefore, once all the parameters are known, the high level description of the converter and the controller are labeled as AB2 and SMC blocks, as shown in Figure 3. The high-level representation shows the block description of the DC–DC buck converter that is emulated by the AB2 method, and the SMC controller. The buses are of 32 bits in fixed-point format and the state variables $x1,x2$ provided by the AB2 block, are controlled by the SMC block, which generates the signal $u\left(t\right)$.

The FPGA implementation of (16) and (17) can be improved by designing single constant multipliers (SCM), as shown in [27]. This is recommended when a constant multiplies a variable, as for the case of the parameters $A,B,C,D,E,F,G$, and J, which are labeled as SCM in the detailed block description shown in Figure 4. The remaining blocks are adders, subtractors, multipliers, and registers. The control of the iterations n is executed by the design of a finite state machine that is labeled as counter in the block description given in Figure 4.

The SMC block shown in Figure 3 is responsible for the control action given in (5). It implements the scalar switched function s given in (15), to take action according to the value provided by the signum function defined by (6), which is synthesized by a comparator. Equation (5) provides three possible output values of the control law $u\left(t\right)$, which are $[1,0.5,0]$. These blocks are shown in Figure 5, which also uses an SCM, an adder, and a comparator.

The FPGA simulation of this SMC controller for the DC–DC buck converter requires three clock cycles (CCs) to obtain a valid regulated voltage $v_{out}$. This means that iteration n for (16) and (17) changes to $n+1$ after 3 CCs.

4.2. FPGA Implementation of the PID Controller

To perform the FPGA synthesis of the PID controller, the gains of the controller $K_p,K_i$, and $K_d$, are considered as parameters that have a constant value. On the one hand, and according to the model of the PID given (12), the error $e\left(t\right)$ must be multiplied by $K_p$, integrated and multiplied by $K_i$, and derived and multiplied by $K_d$. On the other hand, the error is given in (13), having the expression $e\left(t\right)=V_d-x_2$, where according to Table 1, $V_d=3.3$.

In this case, the integral action is simulated by applying the AB2 method given in (3), and the derivative action is simulated by applying the difference quotient method given in (14). The computer arithmetic is performed by using 32 bits that are distributed in the fixed-point format 1:10:21 given in

Table 4. Distribution of the fixed-point format for the FPGA synthesis of the PID controller using 32 bits.

Sign	Integer	Decimal
1 bit	10 bits	21 bits
0	0000000000	0.000000000000000000000

. As the decimal part has 21 bits, the resolution is about $4.768371582031250\times {10}^{-7}$.

The reason to use ten bits in the integer part is to represent the value of $K_d/h=0.0086/0.00001=860$, which is the maximum value that can be generated in the data processing. In this manner, the simulation of the DC–DC buck converter is the same as described in the previous subsection, thus, the discretized equations, by applying the AB2 method, are given in (16) and (17). The block description of the converter for FPGA synthesis is shown in Figure 4. In a high-level description, Figure 6 shows the connection of the converter emulated by applying the AB2 method and the PID controller, which takes action on the error to generate the signal $u\left(t\right)$, as given in (12). Different to the SMC controller, which generates three output values of the control law $u\left(t\right)$, namely: $[1,0.5,0]$; the PID controller has a control law that generates two values, namely: $[1,0]$.

The integration action on the error at iteration $n+1$, denoted as $e_{n+1}^I$, by applying the AB2 method given in (3), leads to the discretized equations given as follows:

$$\begin{array}{cc}\hfill e_{n+1}^I& =K_i\int e_n,\hfill \\ \hfill e_{n+1}^I& =e_n+{\displaystyle \frac{3h}{2}}{K}_i{e}_n-{\displaystyle \frac{h}{2}}{K}_i{e}_{n-1},\hfill \\ \hfill e_{n+1}^I& =1.00034104e_n-0.0001136e_{n-1},\hfill \\ \hfill e_{n+1}^I& =L{e}_n-M{e}_{n-1}.\hfill \end{array}$$

(18)

In (18), the parameters $L=1.00034104$ and $M=0.0001136$ have constant values for the convenience of FPGA implementation. The derivative action is simulated by applying the difference quotient method as given in (14), thus generating the discretized equation given below.

$$\begin{array}{cc}\hfill e_{n+1}^D& =K_d{\dot{e}}_n,\hfill \\ \hfill e_{n+1}^D& ={\displaystyle \frac{K_d{e}_n-K_d{e}_{n-1}}{h}},\hfill \\ \hfill e_{n+1}^D& ={\displaystyle \frac{K_d}{h}}(e_n-e_{n-1}),\hfill \\ \hfill e_{n+1}^D& =860(e_n-e_{n-1}).\hfill \end{array}$$

(19)

In (19), there is no need to assign a parameter, as done for the previous cases; thus, the constant 860 is used as it is, and it imposes the need of using 10 bits to represent the integer part of a real number, as mentioned above. In this manner, the block description of the discretized equations of the PID given by $e_{n+1}^P=K_p{e}_n$, (18), and (19) is shown in Figure 7. This FPGA design also requires three clock cycles (CCs) to generate new data at iteration $n+1$, similar to the FPGA design for the converter using the SMC controller.

5. FPGA Hardware Resources and Experimental Results

The FPGA synthesis of the block descriptions for the emulation of the DC–DC buck converter using SMC or PID controllers requires the hardware resources given in

Table 5. Hardware resources for the synthesis of the SMC and PID controllers for the DC–DC buck converter using 32 and 64 bits, and the FPGA Cyclone® IV EP4CGX150DF31C7N.

Controller	Bits	Logic Elements	Registers	Embedded Multiplier 9 bit	Maximum Frequency (MHz)
SMC	32	1161	221	32	47.61
SMC	64	3939	317	207	24.9
PID	32	1096	220	24	40.2
PID	64	4002	316	199	21.97

, by using the FPGA Cyclone® IV EP4CGX150DF31C7N with a 50 MHz clock. The digital blocks described above were designed considering a computer arithmetic of 32 bits. The design of the digital hardware by using 64 bits is quite similar but the hardware resources are higher, as shown in Table 5.

It is worth mentioning that, to observe the experimental voltage regulation, the voltage E was emulated as a pulse with a value of $E=5$ during 7000 iterations $[n+1]$, and $E=0$ during another 7000 iterations. This emulation allows the observation of the transient response on an oscilloscope, as shown in this section.

5.1. Simulation of Variations and Experimental Results from the FPGA Implementation of the SMC Controller

Figure 8 shows the MatLab transient response and error simulation of the converter by using the SMC parameters given in Table 2.

Figure 9 shows the voltage regulation under 5% of variations in the input voltage E and load of the DC–DC buck converter by using the SMC parameters given in Table 2.

The experimental result from the emulation of the converter and the FPGA implementation of the SMC controller by using a 16-bit digital-to-analog converter, is shown in Figure 10. The figure shows the transient response of the voltage regulation for an output of 3.3 volts, and by emulating the input voltage as a pulse with a value of $E=5$.

Figure 11 shows details of the transient response by using the FPGA-based SMC controller for a voltage regulation of 3.3 and 4.1 volts.

5.2. Simulation of Variations and Experimental Results from the FPGA Implementation of the PID Controller

Figure 12 shows the MatLab transient response and error simulation of the converter by using the PID controller parameters given in Table 2.

Figure 13 shows the voltage regulation under 5 % variations in the input voltage E and load of the DC–DC buck converter by using the PID controller parameters given in Table 2.

The experimental result from the emulation of the converter and the FPGA implementation of the PID controller by using a 16-bit digital-to-analog converter, is shown in Figure 14. The figure shows the transient response of the voltage regulation for an output of 3.3 volts, and by emulating the input voltage as a pulse with a value of $E=5$.

Figure 15 shows details of the transient response by using the FPGA-based PID controller for a voltage regulation of 3.3 and 4.1 volts.

6. Conclusions

The FPGA implementation of the SMC and PID controllers for a DC–DC buck converter has been shown. The converter was emulated on the FPGA by applying the second-order Adams–Bashforth (AB2) method, and the controllers were simulated by applying their respective control laws. The model for the SMC controller used the signum function, which was synthesized by using a comparator, while the model of the PID controller was synthesized by applying the AB2 method to approximate the integration action, and the difference quotient to approximate the derivative action. In both cases, the FPGA synthesis was performed by using fixed-point format with 32 and 64 bits. The hardware resource consumption was similar for the FPGA implementation of both controllers. Finally, it can be concluded that the experimental observation of the transient response of the voltage regulation for different desired output values and the evolution of the error on an oscilloscope are in good agreement with the theory.