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Article

Robust Tracking Control of Dual-Active-Bridge DC–DC Converters with Parameter Uncertainties and Input Saturation

Department of Electrical, Electronic and Computer Engineering, University of Ulsan, Daehak-ro 93, Nam-Gu, Ulsan 680-749, Republic of Korea
*
Author to whom correspondence should be addressed.
Mathematics 2022, 10(24), 4719; https://doi.org/10.3390/math10244719
Submission received: 17 November 2022 / Revised: 5 December 2022 / Accepted: 9 December 2022 / Published: 12 December 2022
(This article belongs to the Special Issue Analysis and Control of Dynamical Systems)

Abstract

:
This paper proposes a method for robust tracking control synthesis of dual-active-bridge (DAB) DC–DC converters with parameter uncertainties and input saturation. In the proposed method, the nonlinear function of the phase shift ratio is expressed as a control input, and the phase shift ratio is determined by the one-to-one relationship with the control input. Especially, the proposed method is developed with consideration of the input saturation phenomenon that occurs physically in the phase shift ratio of DAB DC–DC converters. Furthermore, based on the proposed method, a set of exponential constrained stabilization conditions for DAB DC–DC converter systems with parameter uncertainties is provided to ensure a fast convergence rate. Finally, to verify the effectiveness of the proposed control method, various simulation results are provided and compared with the well-known improved model phase shift control (IMPSC) and load current feedforward (LCFF) control methods.

1. Introduction

Isolated bidirectional DC–DC (IBDC) converters have been widely used in energy storage systems (ESSs) for DC microgrids or smart girds [1], automotive applications [2], and solid-state transformer (SST) applications [3]. Thus, many IBDC topologies have been discussed in both academia and industry, including dual-flyback converters [4], dual-Zeta converters [5], forward-flyback converters [6], dual-push–pull converters [7], dual-half-bridge converters [8], and dual-active bridge (DAB) converters [9]. Among all these types of IBDC converters, the DAB converter has been regarded as one of the most-promising topologies due to its distinct advantages such as inherent soft switching, bidirectional power transfer capability, symmetrical structure, and high power density. When developing the DAB DC–DC converter, the main challenges arise from the input voltage fluctuation, the output load change, and the output voltage or power reference variation. Furthermore, it is worth noticing that the transient response performance of the DAB DC–DC converter can be deteriorated by the parameter uncertainty of the converter. For this reason, various control strategies have been proposed such that the DAB DC–DC converter has more improved transient response performance. As one of the most intuitive techniques, References [10] and [11] proposed a method of using a proportional–integral (PI) controller to regulate the output voltage. However, the drawback of this method is that the output voltage performance deteriorates as the load current changes.
In order to prevent the output voltage performance degradation despite the change of the load current, the linearized control method [12,13], model phase shift control (MPSC) method [14], and load current feedforward (LCFF) control method [15,16] have been proposed by taking the output the load current as the measured disturbance. Thereafter, based on the MPSC method, the work in [17] proposed an improved model phase shift control (IMPSC) to achieve a fast dynamic response on the output voltage. However, the disadvantage of the proposals in [10,11,12,13,14,15,16,17] is that the phase shift ratio is still affected by the uncertainty of the internal inductance. To solve the problem arising from this parameter uncertainty, a virtual direct power control (VDPC) for DAB DC–DC converters was proposed in [18]. The main advantage of the VDPC is that the phase shift ratio can be determined without utilizing inductance information. However, the VDPC method (as well as MPSC, LCFF control, and IMPSC) has the disadvantage that one additional current sensor must be used to measure the output load current, and the uncertainty of the load resistance and capacitance on the output side cannot be taken into account. To avoid the addition of such a current sensor, Reference [19] proposed a method of designing a nonlinear disturbance observer (NDO) that can estimate the output load current. However, it should be noted that the NDO was also designed without consideration of parameter uncertainty. Recently, in [20,21], a moving discretized control set model-predictive control (MDCS-MPC) was proposed as a potential technique applicable to DAB DC–DC converters, where the trial and error method is used to find the best phase shift value. However, MDCS-MPC requires the use of a trial and error approach to obtain the optimal phase shift value and the implementation of an artificial neural network approach to find the weighting matrix of the cost function. Furthermore, MDCS-MPC provides no way to handle the problems of the disturbance and uncertainties present in power converter systems. As an alternative, the disturbance estimation method was introduced in [22,23], but it also has the weakness of having to set too many tuning parameters therein. Recently, an adaptive model predictive control for the DAB DC–DC converter was investigated based on the MDCS-MPC method [24]. This method enables the selection of the trapezoidal and triangular modulation to reduce switching losses.
To fill the gap discussed above, this paper proposes a method for robust tracking control of DAB DC–DC converters with parameter uncertainties and input saturation. Furthermore, the proposed control method is developed so that the DAB DC–DC converter can be robust against sudden changes in the input voltage source and load resistance. To be specific, the contributions of this paper are summarized as follows:
  • Different from the the aforementioned methods, this paper provides a method to consider the phase shift nonlinearity term as a control input. Accordingly, this method opens the possibility that the phase shift ratio can be determined by designing a robust control input for DAB DC–DC converter systems with parameter uncertainties.
  • In order to achieve a fast convergence rate, this paper proposes an effective method for exponential saturated control synthesis of DAB DC–DC converter systems with parameter uncertainties. Based on several convex optimization techniques, the overall stabilization conditions are formulated in terms of the linear matrix inequality (LMI), which offers a set of optimal control gains for DAB DC–DC converter systems.
  • Indeed, the input saturation of DAB DC–DC converters has not been taken into account in the control design process until now. Thus, to overcome this lack of research, this paper proposes a method to analyze the saturation phenomenon that occurs physically in the phase shift ratio of DAB DC–DC converters and reflect its effect on the control design.
  • In order to demonstrate the effectiveness of the proposed control method, our results are compared to the aforementioned IMPSC and LCFF control methods. Furthermore, to verify the robustness of the proposed method and to show the effect of saturated input, various scenarios are produced by considering changes in the source voltage and load resistance.
The rest of the paper is organized as follows. Section 2 presents the modeling of the DAB DC–DC converter system. Section 3 proposes the feedback control design, and Section 4 provides the simulation results. Finally, the paper is concluded in Section 5.
Notations: For any matrix P , P 0 ( P > 0 ) means that P is real symmetric and positive semidefinite (definite). In symmetric block matrices, ( * ) is used as an ellipsis for terms induced by symmetry. For any square matrix Q , He { Q } = Q + Q T ; diag ( · ) stands for a block-diagonal matrix; col ( v 1 , v 2 , , v n ) = [ v 1 T v 2 T v n T ] T ; λ m i n ( . ) and λ m a x ( . ) denote the minimum and maximum eigenvalues of the corresponding matrix, respectively; and sign ( · ) returns the sign of the corresponding argument. For any matrix P > 0 , E ( P , 1 ) stands for an ellipsoid defined as E ( P , 1 ) = x R n | x T P x 1 ; for a scalar s ¯ and a matrix N R 1 × n , L ( N , s ¯ ) stands for a linear region defined as follows: L ( N , s ¯ ) = x R n | | N x | s ¯ .

2. System Description and Preliminaries

So far, various types of modeling for a DAB DC–DC converter system have been proposed such as the discrete-time model [25,26], generalized average model [27], reduced-order model [28,29], and improved reduced model [30]. Among these methods, the reduced-order model, presented in [28,29], exhibits the best choice in the aspects of complexity and accuracy [31], which will be utilized in this paper.
Figure 1 shows the topology of a two-stage single phase for a dual-active-bridge (DAB) DC–DC converter, where:
  • v 1 and v 2 ( t ) are the given constant input voltage and the measurable output voltages, respectively;
  • v p ( t ) is the output voltage on the primary bridge (Bridge 1);
  • v s ( t ) is the input voltage on the secondary bridge (Bridge 2);
  • i ( t ) , i C ( t ) , and i R ( t ) are the output current, the capacitor current, and the load current, respectively;
  • i L ( t ) is the phase shift inductor current;
  • L is the total inductance consisting of the external inductance and the transformer leakage inductor;
  • R is the equivalent load resistance satisfying R R min , R max , where R min and R max are known;
  • C 1 is the capacitance on the input side;
  • C 2 is the capacitance on the output side such that C 2 C 2 min , C 2 max , where C 2 min and C 2 max are known.
The considered DAB DC–DC converter consists of two bridges connected through an inductor L and an isolated transformer, and there are four gate drives on each bridge, where the switches S 1 to S 8 are used to control the gate drives. In general, the DAB DC–DC converter uses single-phase-shifted (SPS) square-wave modulation to control its power. Figure 2 shows the operating waveforms of this converter based on SPS square-wave modulation [9].
To be specific, a pair of switches S 1 / S 2 , S 3 / S 4 , S 5 / S 6 , and S 7 / S 8 operates complementarily, as shown in Figure 2.
Furthermore, the duty ratio of the primary and secondary bridges is fixed at 50 % , and the phase shift φ ( t ) = π d ( t ) is adjustable to control the output voltage tracking the reference.
Especially, since the current i L ( t ) is affected by ( v p ( t ) v s ( t ) ) and L, the transferred power from the primary bridge to the secondary bridge is generated by the phase shift φ ( t ) .
Thus, as in [32], the power of the considered converter is obtained as follows:
p ( t ) = n v 1 v 2 ( t ) 2 f s L d ( t ) ( 1 | d ( t ) | )
where d ( t ) [ 0.5 , 0.5 ] denotes the phase shift ratio, n denotes the transformer turns ratio, and f s denotes the switching frequency.
In addition, the transferred power is expressed as follows:
p ( t ) = v 2 ( t ) i ( t ) .
Thus, from (1) and (2), it follows that
i ( t ) = n v 1 2 f s L d ( t ) ( 1 | d ( t ) | ) .
Furthermore, by the Kirchhoff current law, it is given that
C 2 d v 2 ( t ) d t = i ( t ) i R ( t ) .
Thus, by substituting (3) and i R ( t ) = v 2 ( t ) / R into (4), it is obtained that
v ˙ 2 ( t ) = κ 1 v 2 ( t ) + κ 2 v 1 u ( t )
where
κ 1 = 1 R C 2 , κ 2 = n 2 f s L C 2 , u ( t ) = d ( t ) ( 1 | d ( t ) | ) .
Accordingly, using the first-order Euler approximation with the sampling time T s , the discrete-time model of (5) is represented as follows:
v 2 ( k + 1 ) = ρ 1 v 2 ( k ) + ρ 2 v 1 u ( k )
where
ρ 1 = 1 T s R C 2 , ρ 2 = n T s 2 f s L C 2 > 0 , u ( k ) = d ( k ) ( 1 | d ( k ) | ) .
In addition, since R R min , R max and C 2 C 2 min , C 2 max , the system coefficients are also bounded as ρ 1 ρ 1 min , ρ 1 max and ρ 2 ρ 2 min , ρ 2 max , which can be rearranged as follows:
ρ 1 = α 1 + β 1 Δ 1 , ρ 2 = α 2 + β 2 Δ 2
where
α 1 = ρ 1 max + ρ 1 min 2 , β 1 = ρ 1 max ρ 1 min 2 , | Δ 1 | 1 α 2 = ρ 2 max + ρ 2 min 2 , β 2 = ρ 2 max ρ 2 min 2 , | Δ 2 | 1 .
Remark 1.
In (6), the replacement u ( k ) = d ( k ) ( 1 | d ( k ) | ) is reasonable because the phase shift ratio d ( k ) can be reconstructed by u ( k ) according to the following one-to-one relationship:
d ( k ) = 1 2 1 4 u ( k ) , for u ( k ) [ 0 , 0.25 ] 1 2 + 1 4 + u ( k ) , for u ( k ) [ 0.25 , 0 ] .
The purpose of this paper is to design a controller that allows the output voltage v 2 ( k ) to track the reference voltage v ¯ 2 ref . To effectively address this reference tracking problem, this paper adds the following accumulator:
w ( k + 1 ) = w ( k ) + v ¯ 2 ref v 2 ( k )
with w ( 0 ) = 0 . As a result, letting x T ( k ) = v 2 T ( k ) w T ( k ) and combining (6) and (8), we can obtain
x ( k + 1 ) = A Δ x ( k ) + B Δ u ( k ) + D v ¯ 2 ref
subject to the following input saturation:
u ( k ) 0.25 , 0.25
where
A Δ = A + E Δ 1 H 1 , B Δ = B + E Δ 2 H 2 A = α 1 0 1 1 , B = α 2 v 1 0 , D = 0 1 E T = 1 0 , H 1 = β 1 0 , H 2 = β 2 v 1 .
In addition, based on (6) and (8), the steady-state values of x 1 ( k ) , x 2 ( k ) , and u ( k ) are given, respectively, as follows:
x ¯ 1 = v ¯ 2 = v ¯ 2 ref , x ¯ 2 = w ¯ , u ¯ = 2 f s L n R v 1 v ¯ 2 = 2 f s L n R v 1 v ¯ 2 ref .
However, since R is bounded, it is hard to directly obtain u ¯ from (11).
That is, based on R R min , R max , it is given that
u ¯ 2 f s L n R max v 1 v ¯ 2 , 2 f s L n R min v 1 v ¯ 2 .
Thus, u ¯ can be represented as follows:
u ¯ = u ¯ * + δ u
where u ¯ * is the central value in the steady state and δ u is the uncertain constant value, i.e.,
u ¯ * = f s L v ¯ 2 n v 1 R max + R min R min R max , | δ u | δ ¯ u = f s L v ¯ 2 n v 1 R max R min R min R max .
Accordingly, it follows from (9) that
x ¯ = A Δ x ¯ + B Δ u ¯ * + δ u + D v ¯ 2 ref , x ¯ T = x ¯ 1 T x ¯ 2 T
where x ¯ 1 T and x ¯ 2 T are the steady-state values of x 1 T and x 2 T , respectively,. By letting
e ( k ) = x ( k ) x ¯ = v 2 ( k ) v ¯ 2 ref w ( k ) w ¯ , u ˜ ( k ) = u ( k ) u ¯ *
the error system model is described as follows:
e ( k + 1 ) = A Δ e ( k ) + B Δ u ˜ ( k ) δ u .
Subsequently, let us establish u ˜ ( k ) as follows:
u ˜ ( k ) = ν ( k ) + ν ¯ i . e . , u ( k ) = ν ( k ) + ν ¯ + u ¯ *
where ν ( k ) is a feedback control input and ν ¯ [ δ ¯ u , δ ¯ u ] is a tuning control component used to eliminate δ u .
Then, based on (16), the closed-loop system is described as follows:
e ( k + 1 ) = A Δ e ( k ) + B Δ ν ( k ) + B Δ ν ¯ δ u .
In addition, (10) and (16) lead to the following constraint:
1 4 u ¯ * δ ¯ u < ν ( k ) < 1 4 u ¯ * + δ ¯ u .
As a result, since the tuning control component can be set as ν ¯ = δ u by making the steady-state error zero in real-time, this paper focuses on designing a feedback control that stabilizes the following system subject to (18):
e ( k + 1 ) = A Δ e ( k ) + B Δ sat ( ν ( k ) , s ¯ ) ,
where
sat ( ν ( k ) , s ¯ ) = sign ( ν ( k ) ) · min s ¯ , | ν ( k ) | , s ¯ = 1 4 u ¯ * + δ ¯ u .
The following lemmas will be used for our main derivation.
Lemma 1
([33]). Let X, Δ , and Y be real matrices with appropriate dimensions. Then, if Δ satisfies Δ Δ T I , then for a scalar ϵ > 0 , it holds that
He X Δ Y ϵ X X T + ϵ 1 Y T Y .
Lemma 2
([34]). For a single control input ν ( k ) , if | s ( k ) | s ¯ holds, then
sat ( ν ( k ) , s ¯ ) = i = 1 2 μ i ( k ) G i ν ( k ) + G i c s ( k )
where G i denotes an element of the set G { 0 , 1 } and G i c = 1 G i , and μ ( k ) = col μ 1 ( k ) , μ 2 ( k ) belongs to the standard simplex.
Consequently, the control law subject to the input saturation is designed by combining (16) and (22) as follows:
u ( k ) = sat ( ν ( k ) ) + ν ¯ + u ¯ * .

3. Feedback Control Design

To begin with, let us establish the feedback control input and the auxiliary control input, respectively, as follows:
ν ( k ) = F e ( k )
s ( k ) = N e ( k )
where F R 1 × 2 and N R 1 × 2 are the variables to be designed later. In addition, let us consider the following Lyapunov function:
V ( k ) = e T ( k ) P e ( k )
where 0 < P R 2 × 2 . Then, it holds that
c 1 | | e ( k ) | | 2 V ( k ) c 2 | | e ( k ) | | 2
where c 1 = λ min ( P ) and c 2 = λ max ( P ) .
The following lemma provides the exponential stabilization conditions and the corresponding invariant ellipsoid set for (19).
Lemma 3.
Suppose that it holds that
Δ V ( k ) + α V ( k ) < 0
e ( 0 ) E ( P , γ 1 ) .
Then, the saturated system (19) is robustly and exponentially stable, where the error state satisfies that e ( k ) E ( P , γ 1 ) .
Proof. 
From (28), it follows that
V ( k ) < ( 1 α ) k V ( 0 ) = e μ k V ( 0 )
where μ = ln ( 1 α ) . Furthermore, based on (27) and (30), it is obtained that
| | e ( k ) | | < c 2 c 1 e 0.5 μ k | | e ( 0 ) | | .
Thus, Condition (28) guarantees the exponential stability of (19). In what follows, by (28), it is given that
V ( k ) V ( 0 ) = ι = 0 k 1 Δ V ( ι ) < α ι = 0 k 1 V ( ι ) < 0
which leads to V ( k ) V ( 0 ) < 0 . Thus, by (29) (i.e., e T ( 0 ) P e ( 0 ) = V ( 0 ) γ 1 ), it holds that x T ( k ) P x ( k ) = V ( k ) < V ( 0 ) < γ 1 , which means x ( k ) E ( P , γ 1 ) . Therefore, E ( P , γ 1 ) becomes the invariant ellipsoid set, as well as the domain of attraction. □
The following theorem provides the robust stabilization conditions for (19), formulated in terms of linear matrix inequalities (LMIs).
Theorem 1.
For a prescribed ξ ( 0 , 1 ) and a given initial error state e ( 0 ) , suppose that there exist P ¯ > 0 , F ¯ , N ¯ , ϵ , and γ such that the following conditions hold:
0 > ξ P ¯ ( * ) ( * ) ( * ) A P ¯ + B ( G i F ¯ + G i c N ¯ ) P ¯ + 2 ϵ E E T 0 0 H 1 P ¯ 0 ϵ 0 H 2 ( G i F ¯ + G i c N ¯ ) 0 0 ϵ , i = 1 , 2
0 s ¯ 2 P ¯ ( * ) N ¯ γ , s ¯ = 1 4 u ¯ * + δ ¯ u
0 γ ( * ) γ e ( 0 ) P ¯ .
Then, the saturated system (19) is robustly and exponentially stable, and the feedback control gain and the auxiliary control gain are obtained as F = F ¯ P ¯ 1 and N = N ¯ P ¯ 1 , respectively.
Proof. 
By the Schur complement, Condition (34) is converted into 0 P ¯ ( s ¯ 2 P γ 1 N T N ) P ¯ , which ensures s ¯ 2 N T N γ P , i.e.,
E ( P , γ 1 ) L ( N , s ¯ ) .
In addition, Condition (34) is converted into γ 2 e T ( 0 ) P e ( 0 ) γ , which is equivalent to (29) because γ > 0 . Thus, based on Lemma 3, Conditions (28), (34), and (35) lead to
e ( k ) E ( P , γ 1 ) L ( N , s ¯ ) .
Accordingly, by Lemma 2, it is given that
sat ( ν ( k ) , s ¯ ) = i = 1 2 μ i ( k ) G i F + G i c N e ( k )
by substituting (38) into (19), it is obtained as follows:
e ( k + 1 ) = A Δ + i = 1 2 μ i ( k ) B Δ G i F + G i c N e ( k ) = A ( μ ( k ) ) e ( k )
where
A ( μ ( k ) ) = i = 1 2 μ i ( k ) A i , A i = A Δ + B Δ G i F + G i c N .
Now, the remaining task is to obtain an LMI-based condition from (28). For this task, based on (39), let us first represent (28) as follows:
0 > Δ V ( k ) + α V ( k ) = V ( k + 1 ) ( 1 α ) V ( k ) = e T ( k ) P P ¯ A T ( μ ( k ) ) P A ( μ ( k ) ) P ¯ ( 1 α ) P ¯ P e ( k )
where Δ V ( k ) = V ( k + 1 ) V ( k ) and P ¯ = P 1 . Then, we can see that (28) is ensured by
0 > P ¯ A T ( μ ( k ) ) P A ( μ ( k ) ) P ¯ ( 1 α ) P ¯
for which the Schur complement becomes
0 > ( 1 α ) P ¯ ( * ) A ( μ ( k ) ) P ¯ P ¯ = i = 1 2 μ i ( k ) ( 1 α ) P ¯ ( * ) A i P ¯ P ¯ .
Furthermore, due to the standard simplex of μ ( k ) , Condition (41) can be converted into
0 > ( 1 α ) P ¯ ( * ) A Δ P ¯ + B Δ G i F ¯ + G i c N ¯ P ¯
where F ¯ = F P ¯ R 1 × 2 and N ¯ = F P ¯ R 1 × 2 . Next, using A Δ = A + E Δ 1 H 1 and B Δ = B + E Δ 2 H 2 , Condition (41) is rearranged as follows:
0 > ξ P ¯ ( * ) A P ¯ + B ( G i F ¯ + G i c N ¯ ) P ¯ + He 0 0 E E Δ 1 0 0 Δ 2 H 1 P ¯ 0 H 2 ( G i F ¯ + G i c N ¯ ) 0
where ξ = ( 1 α ) ( 0 , 1 ) . Since Δ = diag ( Δ 1 , Δ 2 ) satisfies that Δ Δ T = diag ( Δ 1 2 , Δ 2 2 ) I , by Lemma 1, Condition (43) holds if
0 > ξ P ¯ ( * ) A P ¯ + B ( G i F ¯ + G i c N ¯ ) P ¯ + ϵ 0 0 E E 0 E T 0 E T + ϵ 1 H 1 P ¯ 0 H 2 ( G i F ¯ + G i c N ¯ ) 0 T H 1 P ¯ 0 H 2 ( G i F ¯ + G i c N ¯ ) 0 .
Finally, by the Schur complement, Condition (44) is converted into (33). □
Remark 2.
The smaller the value of ξ, the larger the value of α is, which accelerates the convergence speed of the error state to zero.
For a more detailed explanation, Figure 3 presents the block diagram of the proposed control scheme, where only the source voltage v 1 and the output voltage v 2 are required to be measurable.
In addition, the procedure of designing the phase shift ratio d ( k ) is summarized as follows:
Step 1.
Calculate u ¯ * , δ ¯ u , and s ¯ from (13) and (20), respectively, by considering the lower and upper bounds of C 2 and R.
Step 2.
For a given initial value e ( 0 ) , obtain F ¯ , N ¯ , and P ¯ by solving (33)–(35) in Theorem 1. After that, generate the control input u ( k ) = sat ( F ¯ P ¯ 1 e ( k ) ) + ν ¯ + u ¯ * according to (23).
Step 3.
Based on (7), obtain the phase shift ratio d ( k ) from u ( k ) , and apply d ( k ) to the single-phase-shift pulse modulator.

4. Simulation Results

For accurate verification, the performance of the controller designed for DAB DC–DC converters was analyzed using the PSIM software tool [35]. Furthermore, to demonstrate the effectiveness of the proposed method, our results were compared with the IMPSC method [17] and the LCFF control method [14]. For a specific simulation, the system parameters were set as shown in Table 1.
Based on such a setting, for ξ = 0.999 , Theorem 1 provides
F = [ 0.2389 0.0614 ] , N = [ 0.1539 0.0603 ] .
For comparison, the control gains of the IMPSC and LCFF control methods are designed based on the phase margin at 85 degree and the cutoff frequency at 4500 Hz such that its own optimized performance can be achieved.
Remark 3.
It is worth noticing that the IMPSC and LCFF methods require an additional current sensor, but the proposed method can be implemented only with input and output voltage sensors. That is, the number of measuring sensors can be reduced through the proposed control method.
In the first simulation, the reference tracking control was performed for nominal systems with R = R min = R max and C 2 = C 2 min = C 2 max , where v ¯ 2 ref = 40 V. Figure 4 shows the simulation results of the DAB DC–DC converter during the start-up process. As shown in Figure 4a, the charging time of the capacitor output was 12.5 ms for both the IMPSC and LCFF control methods. On the other hand, the proposed control method took only 8 ms to reach the capacitor output to the steady-state value, which illustrates that the proposed control method requires a shorter charging time and has an improved overshoot response compared to other methods. In addition, Figure 4b–d show the inductor current of the IMPSC, the LCFF control, and the proposed control method, respectively, during the start-up process.
Figure 5 shows the simulation results of the DAB DC–DC converter for the case where v ¯ 2 ref steps up from 40 V to 45 V at t = 0.2 s. Specifically, from Figure 5b–d, it can be found that the IMPSC and the LCFF control methods required 11.5 ms and 12.5 ms, respectively, to approach the output voltage to its the steady-state value, and the proposed control method required only 6.2 ms relatively. Furthermore, the proposed control method provided a smooth transient response without overshoot, but the IMPSC and LCFF control methods generated an overshoot response with a maximum value of 2.2 V. Conversely, Figure 6 shows the simulation results for the case where v ¯ 2 ref steps down from 45 V to 40 V at t = 0.3 s. As shown in Figure 6b–d, for the IMPSC, the LCFF control, and the proposed control methods, the settling times are given as 9.3 ms, 14.2 ms, and 7 ms, respectively. That is, from Figure 6, it can be seen that the proposed control method provides a better time response than the other methods.
In the second simulation, the load resistance was set to be changed to show the robustness of the proposed control method. Figure 7 shows the simulation results for the case where R steps up from 50 Ω to 100 Ω at t = 0.2 s. As shown in Figure 7a, the change in the load resistance decreased the load current by 0.4 A at t = 0.2 s and caused a maximum overshoot of 1.25 V on the output voltage. To be specific, for the IMPSC, the LCFF control, and the proposed control methods, the settling times are given as 22 ms, 14 ms, and 10 ms, respectively, which reveals that our method achieved a shorter settling time than the other methods. Conversely, Figure 8 shows the simulation results for the case where R steps down from 100 Ω to 50 Ω at t = 0.3 s. As shown in Figure 8, the change in the load resistance increased the load current by 0.4 A at t = 0.3 s and caused a maximum overshoot of 0.2 V on the output voltage. To be specific, for the IMPSC, the LCFF control, and the proposed control methods, the settling times are given as 81 ms, 42 ms, and 42 ms, respectively, which illustrates that the proposed method exhibited a smoother transient response and smaller oscillation than the other methods. Thus, from Figure 7 and Figure 8, it can be seen that the proposed control method provided better performance than the other methods.
In the third simulation, the source voltage was set to be changed to show the robustness of the proposed control method. Figure 9 shows the simulation results for the case where v 1 steps down from 100 V to 85 V at t = 0.2 s, where v 2 ref = 40 V. As shown in Figure 9b–d, the IMPSC method caused a maximum overshoot of 4.26 V, the LCFF control method caused a maximum overshoot of 4.7 V, and the proposed control method caused a maximum overshoot of 4.26 V. Overall, the transient response quickly disappeared as the output voltage converged to the reference voltage. Specifically, for the IMPSC, the LCFF control, and the proposed control methods, the settling times are given as 15.6 ms, 16 ms, and 9 ms, respectively, which reveals that our method required a shorter settling time than the other methods. That is, from Figure 9, it can be seen that the proposed control method is the most excellent for improving the performance among the three control methods.
Conversely, Figure 10 show the simulation results for the case where v 1 steps up from 85 V to 100 V at t = 0.3 s. As shown in Figure 10b–d, the IMPSC and the LCFF control methods required 12.5 ms and 21.5 ms, respectively, to approach the output voltage to its steady-state value, and the proposed control method required 10 ms relatively. Thus, from Figure 10, it can be seen that our method had a shorter settling time than other methods. Finally, the fourth simulation is given to verify the effect of the proposed control method on the input saturation of DAB DC–DC converters. Figure 11 shows the transient response of the output voltage for the control system with/without input saturation. As shown in Figure 11b, the input saturation occurred during the time from t = 3.9 ms to t = 5.8 ms when the control signal ν ( k ) became less than s ¯ = 0.241 . In addition, Figure 11a shows that the controller designed without input saturation considerations required a settling time of 13.5 ms, but our control method, which can cope with the saturation phenomenon, required a settling time of 8 ms. Thus, it can be seen that the proposed control method has more advantages when the input saturation occurs.
To verify whether the proposed method can work well in the case of the no-load condition, Figure 12 shows the simulation results of the output voltage when the no-load condition was applied from t = 0.15 s to t = 0.25 s. It can be seen from Figure 12 that the output voltage of the DAB DC–DC converter was not affected by the no-load condition when the no-load situation occurred from t = 0.15 s to t = 0.25 s. In addition, the result shows that the proposed method worked well when the reference changes from 40 V to 45 V at t = 0.2 s under the no-load condition.
To validate the efficacy of the proposed method in the steady state, Figure 13 shows the simulation for the error between the reference and the output voltage.
As shown in Figure 13, the steady-state error is given 0.3 V, 0.38 V, and 0.01 V for the IMPSC, LCFF control, and the proposed methods, respectively, which indicates that the proposed method exhibited the best performance compared to other methods under the steady-state condition.

5. Concluding Remarks

This work focused on developing a robust tracking control design for DAB DC–DC converters with parameter uncertainties and input saturation. From the obtained results, the following two advantages of the proposed method were verified:
(1)
The fast transient response of DAB DC–DC systems was achieved by solving an exponential stabilization problem;
(2)
The output voltage performance for the change of voltage source and load resistance was further improved through the proposed method over the IMPSC and LCFF control methods.
In the future, the proposed method will be further generalized so that it can be combined with the sampled data control scheme.

Author Contributions

Conceptualization, N.N.N.; methodology, S.H.K. and N.N.N.; software, N.N.N.; validation, S.H.K. and N.N.N.; formal analysis, S.H.K. and N.N.N.; investigation, S.H.K. and N.N.N.; resources, S.H.K.; data curation, S.H.K. and N.N.N.; writing—original draft preparation, S.H.K. and N.N.N.; writing—review and editing, S.H.K. and N.N.N.; visualization, S.H.K. and N.N.N.; supervision, S.H.K.; project administration, S.H.K.; funding acquisition, S.H.K. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the National Research Foundation of Korea Grant funded by the Korean Government (NRF-2018R1D1A1B07041456).

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. The topology of a dual-active-bridge converter.
Figure 1. The topology of a dual-active-bridge converter.
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Figure 2. Operating waveforms of the DAB converter using SPS modulation.
Figure 2. Operating waveforms of the DAB converter using SPS modulation.
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Figure 3. Block diagram of the robust control for the DAB DC–DC converter with steady-state error and input saturation.
Figure 3. Block diagram of the robust control for the DAB DC–DC converter with steady-state error and input saturation.
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Figure 4. Simulation results of the IMPSC, the LCFF control, and proposed control schemes during the startup process.
Figure 4. Simulation results of the IMPSC, the LCFF control, and proposed control schemes during the startup process.
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Figure 5. Simulation results of the output voltage when the reference steps up from 40 V to 45 V at t = 0.2 s.
Figure 5. Simulation results of the output voltage when the reference steps up from 40 V to 45 V at t = 0.2 s.
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Figure 6. Simulation results of the output voltage when the reference steps down from 45 V to 40 V at t = 0.3 s.
Figure 6. Simulation results of the output voltage when the reference steps down from 45 V to 40 V at t = 0.3 s.
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Figure 7. Simulation results of the output voltage when load steps up from 50 Ω to 100 Ω .
Figure 7. Simulation results of the output voltage when load steps up from 50 Ω to 100 Ω .
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Figure 8. Simulation results of the output voltage when load steps down from 100 Ω to 50 Ω .
Figure 8. Simulation results of the output voltage when load steps down from 100 Ω to 50 Ω .
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Figure 9. Simulation results of the output voltage when the input voltage steps down from 100 V to 85 V.
Figure 9. Simulation results of the output voltage when the input voltage steps down from 100 V to 85 V.
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Figure 10. Simulation results of the output voltage when the input voltage steps up from 85 V to 100 V.
Figure 10. Simulation results of the output voltage when the input voltage steps up from 85 V to 100 V.
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Figure 11. Simulation results of the output voltage when applying with/without input saturation.
Figure 11. Simulation results of the output voltage when applying with/without input saturation.
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Figure 12. Simulation results of output voltage when the no-load condition is applied.
Figure 12. Simulation results of output voltage when the no-load condition is applied.
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Figure 13. Simulation results for the error between the reference and the output voltage in the steady-state condition.
Figure 13. Simulation results for the error between the reference and the output voltage in the steady-state condition.
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Table 1. System parameters.
Table 1. System parameters.
ParameterSymbolValue
Input voltage v 1 100 V
Phase-shifting inductanceL50 × 10 6 H
Switching frequency f s 20 kHz
Transformer turns ration1
Input/output capacitor   C 1 / C 2   440 × 10 6 F/440 × 10 6 F
Min/Max output capacitor    C 2 min / C 2 max    420 × 10 6 F/480 × 10 6 F
Nominal load resistanceR50 Ω
Min/Max load resistance R min / R max 10 Ω/100 Ω
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Nam, N.N.; Kim, S.H. Robust Tracking Control of Dual-Active-Bridge DC–DC Converters with Parameter Uncertainties and Input Saturation. Mathematics 2022, 10, 4719. https://doi.org/10.3390/math10244719

AMA Style

Nam NN, Kim SH. Robust Tracking Control of Dual-Active-Bridge DC–DC Converters with Parameter Uncertainties and Input Saturation. Mathematics. 2022; 10(24):4719. https://doi.org/10.3390/math10244719

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Nam, Nguyen Ngoc, and Sung Hyun Kim. 2022. "Robust Tracking Control of Dual-Active-Bridge DC–DC Converters with Parameter Uncertainties and Input Saturation" Mathematics 10, no. 24: 4719. https://doi.org/10.3390/math10244719

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