Central Nervous System: Overall Considerations Based on Hardware Realization of Digital Spiking Silicon Neurons (DSSNs) and Synaptic Coupling

Abstract

The Central Nervous System (CNS) is the part of the nervous system including the brain and spinal cord. The CNS is so named because the brain integrates the received information and influences the activity of different sections of the bodies. The basic elements of this important organ are: neurons, synapses, and glias. Neuronal modeling approach and hardware realization design for the nervous system of the brain is an important issue in the case of reproducing the same biological neuronal behaviors. This work applies a quadratic-based modeling called Digital Spiking Silicon Neuron (DSSN) to propose a modified version of the neuronal model which is capable of imitating the basic behaviors of the original model. The proposed neuron is modeled based on the primary hyperbolic functions, which can be realized in high correlation state with the main model (original one). Really, if the high-cost terms of the original model, and its functions were removed, a low-error and high-performance (in case of frequency and speed-up) new model will be extracted compared to the original model. For testing and validating the new model in hardware state, Xilinx Spartan-3 FPGA board has been considered and used. Hardware results show the high-degree of similarity between the original and proposed models (in terms of neuronal behaviors) and also higher frequency and low-cost condition have been achieved. The implementation results show that the overall saving is more than other papers and also the original model. Moreover, frequency of the proposed neuronal model is about 168 MHz, which is significantly higher than the original model frequency, 63 MHz.

1. Introduction

In the past recent decades, a variety of mathematical computational approaches have been implemented in different research fields such as fluid mechanic engineering [1,2,3,4,5,6,7,8,9], chemical engineering [10,11,12,13,14,15,16,17,18], electrical engineering [19,20,21,22,23,24,25,26,27,28], telecommunication engineering [29,30,31,32,33,34], computer engineering [35,36,37,38,39], petroleum engineering [40,41,42,43,44,45,46,47], energy engineering [48,49,50], mathematics [51,52,53,54,55,56,57,58,59], environmental engineering [60,61,62], health and medical sciences [63,64,65], industrial engineering [66], etc. Among the various applied computational methods, artificial neural networks have been widely used, which demonstrates their capability. So, every effort in this field is of high importance.

Spiking Neural Networks (SNNs) are a very attractive research area based on neuronal brain cells. The time-domain field in the SNN is the main concept that is based on the different models of neural networks. In SNNs, neurons can transmit data and information via synaptic connection, and this causes different levels of learning and memory in the human brain. In coupled neurons, when the presynaptic neuron is triggered by an applied stimulus current, this can release the voltage signals, this voltage can trigger the synaptic gap, and then the additional current is injected to the postsynaptic neurons, which is illustrated as a train of spiking behaviors in the post neurons. This behavior of neurons can be described by the spiking neuron models [67,68,69,70,71,72].

The basic elements in this system are neurons, synapses, and glias [69,73,74,75]. Neuron blocks are the important organs in CNS, which have several vital roles such as receiving, processing, and transmitting information to different parts of the human brain. On the other hand, synapses connect the neurons and are responsible for transferring data between neurons. Moreover, another cell called a glia can protect neurons in the CNS. Indeed, glias regulate the synaptic coupling between neurons. Thus, in the first step, the neurons’ behaviors must be investigated in case of simulation and realization to obtain a compact and practical hardware.

Neurons have different behaviors and reactions. These behaviors can follow the basic pattern, which can be modeled by the mathematical equations in [76,77,78,79,80,81,82,83]. Two basic modeling systems have been presented. The first state is the biological model with biological parameters and reactions. Some basic models such as the Hodgkin–Huxley (HH) neuron model and the ADEX neuron model. These models have the biological aspects and may be a complex mathematical equation. On the other hand, SNN models are based on the spike timing patterns and less biological states. In this approach, some models such as the Izhikevic, FHN, and other models have been presented. Among these two modeling aspects, the SNN modeling may be better than the biological ones because of their low-cost implementations in hardware form. Indeed, when a compact neuron model (in hardware state) is required, the SNN models are better choices. As a result, a model named the Digital Spiking Silicon Neuron (DSSN) model is proposed [84]. This model was designed to simulate several classes of neurons by simple digital arithmetic circuits.

The implementation of different models have been realized in different positions. Two basic selections of the implementation are analog and digital states [67,68,70,71,85,86,87,88,89,90]. In analog implementation, CMOS elements are applied to achieve an analog architecture to follow the mathematical modeling of the neuron. This solution is fast, but it may suffer from long development timing. On the other hand, in the digital realization of neuronal models, a high amount of silicon may be required as well as high power consumption, but this solution can be very efficient in comparison to other methods. Some capabilities of the digital implementation are its high-degree of flexibility, reduced timing process, and power supply. In this approach, using programmable boards such as FPGAs can be very fast and flexible.

This paper presents a hardware implementation of the DSSN model in the case of a digital system. The basic challenge of this realization is the quadratic term of the original neuron model. In the general case, the quadratic term (because of its multiplier operation) causes the speed-down in the final system. In other words, in the CNS, the speed of the neuronal activity is a very important factor. If the final system does not have an acceptable frequency, it influences the neural system. Thus, this nonlinear term must be removed or converted to another simple term. Different approaches can be applied to obtain simple mathematical equations. Among these approaches, converting the quadratic terms to hyperbolic functions may be the best way. Indeed, by converting the nonlinear terms of the original model to a set of hyperbolic functions, we have a new model (by protecting all behaviors of the original mode) which converts all multiplier operations to a set of digital SHIFTs and ADDs (This method will be explained). Consequently, using the proposed new model, we have a low-cost, high-speed, and high-efficiency system which can trace the original neuron model with a high-degree of similarity and performances.

The overall method for implementing the neuronal networks can be explained. The efficient modeling, simulation, and implementation of biological neural networks are significant. Neuromorphic engineering is a very significant subject that takes inspiration from biology, physics, mathematics, computer science, and electronic engineering to design neural systems. In the field of biology and biomedicine, the theoretical and experimental aspects of neuroscience are evaluated to have a better understandings of the brain structure. Consequently, studying, modeling, simulation, and implementing brain-like systems to realize the brain behaviors are a vital requirement. At first step, it is necessary that the neuron model is selected. In this approach, many different neuron models have been presented for spiking neural networks to reproduce their dynamical behavior. Some neuron models have biological behaviors and other models reproduce the spiking patterns of the human brain. The DSSN neuron model is a widely accepted model that can reproduce the spiking patterns of the brain. After model selection, the time domain and dynamical behaviors of the proposed neuron model have been evaluated. Indeed, the proposed model is a modified case of the basic neuron model with low-error state and low-cost hardware attributes. Since the original models have nonlinear terms and functions with high-cost realizations, it is necessary that the model is modified to a new low-cost model for its implementation on hardware platforms. To validate the proposed model in case of following the original model, spiking patterns and dynamics must be considered. These evaluations have been performed using MATLAB software simulations. Finally, to test and validate the proposed model in hardware form, we have used the FPGA system design. In fact, the Hardware Description Language (HDL) of the proposed neuron model has been considered using the ModelSim and Xilinx ISE software. In this part, the proposed model’s overhead costs have been compared to the original model cost realization. The proposed model must be more efficient in comparison with the original model in case of overhead costs (overall saving in FPGA) and speed-up (maximum frequency).

This paper is organized as follows. In Section 2, the background of the DSSN model will be explained. In Section 3, the proposed procedure is evaluated. Section 4 presents the dynamic behaviors and time domain analysis. Synaptic coupling is described in Section 5. Overall hardware implementation is performed in Section 6 in detail. Production results are presented in Section 7. The limitations of the method and also future directions have been explained in Section 8. The paper concludes in Section 9.

2. Background

The Digital Spiking Silicon Neuron (DSSN) model is a simple practical model in terms of qualitative states. This model is capable of reproducing different classes of spiking such as Class I and Class II patterns. The DSSN model can be formulated by two coupled differential equations for voltage and recovery variables. The mathematical equations of the model are given by following statements:

$$\frac{dV}{dt}=\frac{\varphi }{\tau }(f\left(V\right)-n+I_0+I_{Stimulus})$$

(1)

$$\frac{dn}{dt}=\frac{1}{\tau }(g\left(V\right)-n)$$

(2)

where

$$f\left(V\right)=\left\{\begin{array}{c}{a}_n{(V+b_n)}^2-c_n;V<0\hfill \\ -a_p{(V-b_p)}^2+c_p;V>0\hfill \end{array}\right.$$

(3)

$$g\left(V\right)=\left\{\begin{array}{c}{k}_n{(V-p_n)}^2+q_n;V<r\hfill \\ k_p{(V-p_p)}^2+q_p;V>r\hfill \end{array}\right.$$

(4)

In these equations, V and n represents the voltage and slow variable, respectively. On the other hand, V is the membrane potential, and n is the recovery variable for producing the voltage variable. The parameter $I_0$ is a bias fixed parameter, and $I_{Stimulus}$ is the applied current for neurons. The other parameters for generating the Class I and Class II patterns are presented in

Table 1. Different Parameters for Reproducing the Class I Pattern.

Parameter	Value	Parameter	Value
$a_n$	8	$a_p$	8
$b_n$	0.25	$b_p$	0.25
$c_n$	0.5	$c_p$	0.5
$k_n$	2	$k_p$	16
$p_n$	−0.3125	$p_p$	−0.2187
$q_n$	−0.7058	$q_p$	−0.6875
$\varphi$	1	$\tau$	0.003
r	−0.2053	$I_0$	−0.205

and

Table 2. Different Parameters for Reproducing the Class II Pattern.

Parameter	Value	Parameter	Value
$a_n$	8	$a_p$	8
$b_n$	0.25	$b_p$	0.25
$c_n$	0.5	$c_p$	0.5
$k_n$	4	$k_p$	16
$p_n$	−0.5625	$p_p$	−0.2187
$q_n$	−1.3177	$q_p$	−0.6875
$\varphi$	0.5	$\tau$	0.003
r	−0.1041	$I_0$	−0.23

, respectively. These parameters are explained as follows:

• $I_0$: Bias constant;
• $I_{Stimulus}$: Applied current for neurons;
• $\varphi$ and $\tau$: Time constant;
• $r,a_x,b_x,c_x,k_x,p_x,$ and $q_x$ ($x=n$ and $x=p$): Constants that control the nullclines of the variables (Dynamics of the model).

It is emphasized that the DSSN model is a spike-based neuron model, and all the variables and constants are abstracted and do not have a physical unit. In addition, by selecting appropriate values for these parameters, both Class I and Class II neurons can be realized with parameter settings. Finally, different spiking patterns based on these two basic parameters can be simulated, as can be seen in Figure 1.

3. Proposed Procedure

As can be seen in the mathematical equations of the original DSSN model, the basic nonlinear term of this model is the quadratic term which is repeated in all parts of the model. DSSN neuron is implemented on an FPGA digital board, but the quadratic terms of the equations cause the final system to be no more efficient. In this situation, the best method is to convert the nonlinear terms to new functions which have two basic conditions: first is the high degree of similarity between the original and proposed method and second is the low-cost digital implementation in terms of FPGA resources and higher frequency (speed-up) compared with the original DSSN model. In this approach, there are different acceptable ways to approximate and modify the original models, such as piecewise linear functions, absolute functions, and hyperbolic terms. When the original models are approximated by linear functions, the error level in the proposed model can be increased, but using the hyperbolic functions reduces the error calculation, and a high-degree of similarity will also be achieved. Thus, in this paper, we used the hyperbolic-based modifications. Another advantage of this method is that by using these hyperbolic terms, all nonlinear terms and functions in the differential equations are converted to digital SHIFTs and ADDs without any multiplications. Consequently, we have a new model with all aspects of the original model that it is efficient in terms of speed and costs compared with the original main DSSN model. In the proposed model, the equations are reformulated as follows:

$$\frac{dV}{dt}=\frac{\varphi }{\tau }(F\left(V\right)-n+I_0+I_{Stimulus})$$

(5)

$$\frac{dn}{dt}=\frac{1}{\tau }(G\left(V\right)-n)$$

(6)

where

$$F\left(V\right)=\left\{\begin{array}{c}{a}_n\left(Func\left(V\right)\right)-c_n;V<0\hfill \\ -a_p(Func\left(V\right)-4V{b}_n)+c_p;V>0\hfill \end{array}\right.$$

(7)

$$G\left(V\right)=\left\{\begin{array}{c}{k}_n\left(Func\left(V\right)\right)+q_n;V<r\hfill \\ k_p\left(Func\left(V\right)\right)+q_p;V>r\hfill \end{array}\right.$$

(8)

where

$$Func\left(V\right)=0.6sinh\left(0.65V\right)+0.6cosh\left(1.5V\right)-0.5$$

(9)

In other words, based on Equations (3) and (4), when these equations are simplified, we have a new nonlinear function which is repeated in all equations. This new function can be formulated as follows:

$$NL-Func\left(V\right)=V^2+0.5V+0.0625$$

(10)

Consequently, this nonlinear function can be replaced by $Func\left(V\right)$ in all parts of the original mathematical equations. By this modification, the proposed model can be implemented in low-cost and high-speed states (This procedure is elaborated in detail in the hardware section). In this approach, as can be depicted in Figure 2, the original nonlinear function ($NL-Func\left(V\right)$) and the proposed hyperbolic term ($Func\left(V\right)$) have a high degree of similarity, and the error level between these two equations is in the low state, which is shown in the next sections. It is noticeable that based on Figure 1 and Figure 2, the permissible range of parameter value changes is given between $-0.5$ and $+0.5$. Indeed, the modifications of the nonlinear terms of the neuron model have been conducted in this variation range.

4. Dynamic Behaviors and Time Domain Analysis

Two basic factors should be considered for validating the proposed model. In this approach, at first, it is important that the proposed model is in the same state (as dynamical behaviors in equilibrium points and eigenvalues) as the original model; second, the time domain analysis for two models (original and proposed) is done with low error calculation.

4.1. Dynamics

To investigate the modified model, the behaviors of neurons in the case of dynamics are considered. In this way, to explain the transition from resting state to spiking state (bifurcation), the interactions of the two nullclines play an important role [77,91,92].

The nullclines for the original model can be given by the following statements:

$$\left\{\begin{array}{c}\frac{dV}{dt}=p(V,n)\hfill \\ \\ \frac{dn}{dt}=q(V,n)\hfill \end{array}\right.$$

(11)

$$\left\{\begin{array}{c}\frac{dV}{dt}=0;p(V,n)=0\hfill \\ \\ \frac{dn}{dt}=0;q(V,n)=0\hfill \end{array}\right.$$

(12)

$$\left\{\begin{array}{c}n=f\left(V\right)-n+I_0+I_{Stimulus}\hfill \\ \\ n=g\left(V\right)\hfill \end{array}\right.$$

(13)

On the other hand, the nullclines of the proposed model are given as:

$$\left\{\begin{array}{c}n=F\left(V\right)-n+I_0+I_{Stimulus}\hfill \\ \\ n=G\left(V\right)\hfill \end{array}\right.$$

(14)

Consequently, for analyzing the equilibrium points, the Jacobean matrix and eigenvalues are required [77,91,92], and the Jacobean matrix can be obtained as:

$$\left\{\begin{array}{c}AB\hfill \\ CD\hfill \end{array}\right.$$

(15)

where

$$\left\{\begin{array}{c}A=\frac{\partial p(V,n)}{\partial V}\hfill \\ \\ B=\frac{\partial p(V,n)}{\partial n}\hfill \\ \\ C=\frac{\partial q(V,n)}{\partial V}\hfill \\ \\ D=\frac{\partial q(V,n)}{\partial n}\hfill \end{array}\right.$$

(16)

According to $J(V,n)$, the stability of the fixed point is determined. The fixed points are stable if $A+D<0$, and they are unstable if $A+D>0$. On the other hand, the fixed point is stable if both of the eigenvalues of this matrix have a negative real part and is unstable if at least one of the eigenvalues has a positive real part. As can be seen in

Table 3. Equilibrium Points For the Original and Proposed Models.

Point (Orig.)	Value (Orig.)	Point (Prop.)	Value (Prop.)
Saddle Point	$(-0.2,-0.7)$	Saddle Point	$(-0.22,-0.68)$
Spiral Source	$(0.09,0.92)$	Spiral Source	$(0.1,0.9)$
Saddle Point	$(-0.28,-1)$	Saddle Point	$(-0.27,-0.98)$
Spiral Sink	$(0.24,1.27)$	Spiral Sink	$(0.22,1.25)$

, these calculations are applied. On the other hand, Figure 3 illustrates the similarity between spike patterns of the original and proposed DSSN neuron models. As depicted in this figure, the equilibrium points are the same.

4.2. Time Domain

To validate the proposed neuron model in case of timing accuracy and spiking patterns, the time domain must be considered. In this approach, based on different stimulus currents, the spiking patterns between original and proposed DSSN models are compared. As can be seen in Figure 4, spiking patterns of the proposed neuron model share a high degree of similarity with the original model. In addition, the error calculations are in a low state, which are computed in the next step.

As can be seen in Figure 4, in some region of the spiking patterns, there are differences (errors) between the original and proposed DSSN models. Indeed, it is attempted to reduce this error to a near-zero value. A different method is available to calculate the error values between the original and proposed models. Some of these methods are focused on the absolute differences between two signals. In addition, some methods are emphasized on the square of root mean values. In this paper, these two basic error methods are applied for validating that the proposed model is in the low-error calculation compared with the original main model. These two methods are formulated as follows:

$$RMSE(V_{Prop.},V_{Orig.})=\sqrt{\frac{{\sum }_{i=1}^n{\left(V_{Prop.}-V_{Orig.}\right)}^2}{n}}$$

(17)

$$MAE=\frac{1}{n}\sum _{i=1}^n|V_{Prop.}-V_{Orig.}|$$

(18)

Moreover, as can be seen in Figure 5, the error level is based on the differences between the original and proposed functions. Indeed, when this difference is accrued, the spiking patterns between the original and proposed models may have differences. These differences in our proposed models have been optimized, so the modified model regenerates the same behaviors of spike-based behavior of the original model to a high degree of similarity and low-error computations. As it is shown in

Table 4. Error Calculations of the Proposed Model.

${\mathit{I}}_{\mathit{Stimulus}}$	RMSE (Class I)	MAE (Class I)	RMSE (Class II)	MAE (Class II)
$0.1$	$0.05$	$0.02$	$0.067$	$0.022$
$0.2$	$0.08$	$0.01$	$0.1$	$0.018$
$0.5$	$0.09$	$0.034$	$0.095$	$0.04$
1	$0.1$	$0.028$	$0.15$	$0.039$
2	$0.075$	$0.014$	$0.035$	$0.012$
3	$0.11$	$0.08$	$0.16$	$0.06$

, the error levels are calculated.

5. Synaptic Coupling

A synapse is a connection gap that can transfer data from a presynaptic neuron to a postsynaptic neuron. Synaptic coupling is a significant issue in the case of memory and learning. For describing the coupling behavior of two connected neurons, the synaptic coupling system can be evaluated [93,94]. In this approach, a terminal can be considered that incorporates a presynaptic neuron and a postsynaptic neuron. This synapse model can be given by the following equation:

$$\left\{\begin{array}{c}\tau {}_s\frac{dZ}{dt}=[1+tanh\left(S_s(V_{presynaptic}-h_s)\right)](1-Z)-\frac{Z}{d_s}\hfill \\ \\ I_{Synapse}=k_s(Z-Z_0)\hfill \end{array}\right.$$

(19)

In the above equation, the parameter Z is the synapse factor. Moreover, the synaptic parameters are given by the following:

• ${\tau }_s$: Time delay (s);
• $S_s$: Responsible for the activation and relaxation of Z;
• $d_s$: Relaxing the parameter Z;
• $h_s$: Threshold parameter for the activation of Z;
• $k_s$: Conductivity parameter;
• $Z_0$: Reference level of Z.

When the presynaptic neuron ($V_{presynaptic}$) reaches its critical value (threshold voltage, $h_s$), the signal transmission of connected neurons is computed. Moreover, the synapse stimulus, $I_{synapse}$, triggers the postsynaptic neuron.

Table 5. Synapse Parameters.

${\tau }_s=10$

$S_s=1$

$d_s=3$

$h_s=-70$

$k_s=10$

$Z_0=0$

shows the synapse parameters.

The synchronization effects of the coupled neurons are significant for the processing of biological signals and play significant roles in the elucidation of diseases, such as Parkinson’s disease, essential tremor, and epilepsy [95]. Consequently, by the appropriate selection of input stimulus and synaptic conductance coefficient, the synchronization effects can be controlled. This coupled proposed DSSN model is specified as follows:

$$\left\{\begin{array}{c}\frac{d{V}_{pre}}{dt}=\frac{\varphi }{\tau }(F\left(V_{pre}\right)-n_{pre}+I_0+I_{Stimulus})\hfill \\ \\ \frac{d{n}_{pre}}{dt}=\frac{1}{\tau }(G\left(V_{pre}\right)-n_{pre})\hfill \\ \\ \tau {}_s\frac{dZ}{dt}=[1+tanh\left(S_s(V_{pre}-h_s)\right)](1-Z)-\frac{Z}{d_s}\hfill \\ \\ I_{synapse}=k_s(Z-Z_0)\hfill \\ \\ \frac{d{V}_{post}}{dt}=\frac{\varphi }{\tau }(F\left(V_{post}\right)-n_{post}+I_0+I_{Synapse})\hfill \\ \\ \frac{d{n}_{post}}{dt}=\frac{1}{\tau }(G\left(V_{post}\right)-n_{post})\hfill \end{array}\right.$$

(20)

Consequently, by different stimulus currents, different states of the synchronization between presynaptic and postsynaptic neurons in the proposed and original models are evaluated. These states are depicted in Figure 6.

6. Overall Hardware Implementation

This section presents a comprehensive digital architecture based on the proposed neuron model using FPGA board hardware. For implementing a mathematical neuron equation on FPGA hardware, different issues must be taken into account. In our paper, since the final goal is the realization of a compact hardware with low-cost and high-speed attributes, the first step is determining the bit-width, which must be in optimized state. On the other hand, based on the proposed equations, the scheduling diagrams are created to consider the final routes in the hardware implementation. In this state, the pipeline approach can be applied to accelerate the output signals execution. In our architecture, all of functions and terms of the model are realized without any using multiplier operations. This causes the final proposed hardware to have a high-frequency and low-resources area in comparison with the original one. After this state, we can use the Hardware Description Language (HDL) to create the proposed digital code. In this way, different approaches are used to obtain a low-cost implementation in FPGA level. Consequently, using the proposed method, we have an efficient hardware that can be used as high-speed digital equipment in spiking neural networks area.

6.1. Scheduling Diagrams

In this part, based on the proposed model (equations), the final scheduling diagrams are created. In this approach, we have two basic variables (V and n) which are scheduled as two main hardware routes. For considering the proposed model in hardware form, it is essential that the hyperbolic terms of this model is reformulated (as a discretized form) as below:

$$Func\left(V\left[i\right]\right)=0.6[\frac{2^{0.65V\left[i\right]}-2^{-0.65V\left[i\right]}}{2}]+0.6[\frac{2^{0.65V\left[i\right]}+2^{-0.65V\left[i\right]}}{2}]-0.5$$

(21)

For implementing this function, the power2-based approximation can be used [68]. Generating the exponential functions (EXP. Unit) with powers of 2, is the key idea of this approach, which is realized by a logic shift. Replacing multipliers with logic shift operations leads to a significant low-cost hardware realization. As a result, in this approach, the hyperbolic terms will be achieved. As depicted in Figure 7, this hyperbolic function can be created.

In the next step, using this $FUNC\left(V\right)$ hardware, the hardware of the internal functions ($F\left(V\right)$, $G\left(V\right)$) are realized, based on the following discretized equations:

$$F\left(V\left[i\right]\right)=\left\{\begin{array}{c}{a}_n\left(Func\left(V\left[i\right]\right)\right)-c_n;V\left[i\right]<0\hfill \\ -a_p(Func\left(V\left[i\right]\right)-4V\left[i\right]b_n)+c_p;V\left[i\right]>0\hfill \end{array}\right.$$

(22)

$$G\left(V\left[i\right]\right)=\left\{\begin{array}{c}{k}_n\left(Func\left(V\left[i\right]\right)\right)+q_n;V\left[i\right]<r\hfill \\ k_p\left(Func\left(V\left[i\right]\right)\right)+q_p;V\left[i\right]>r\hfill \end{array}\right.$$

(23)

These two internal terms are realized, as can be depicted in Figure 8.

Consequently, using the above internal functions, the scheduling diagrams of the proposed model can be designed based on the following discretized equations:

$$V[i+1]=dt\ast \frac{\varphi }{\tau }(F\left(V\left[i\right]\right)-n\left[i\right]+I_0+I_{Stimulus})+V\left[i\right]$$

(24)

$$n[i+1]=dt\ast \frac{1}{\tau }(G\left(V\left[i\right]\right)-n\left[i\right])+n\left[i\right]$$

(25)

The scheduling diagrams of the proposed equations are depicted in Figure 9.

As can be seen from the scheduling diagrams, the proposed neuron model can be implemented as a digital system in a multiplierless state. All of the proposed terms and equations of the implemented model have been realized based on the primary blocks such as ADDs, SUBs, and digital SHIFTs. In other words, using the proposed method, the final digital costs will be significantly reduced. This approach causes a speed-up (by increasing the system frequency) in the digital hardware that can be implemented on FPGA platforms. One of the important issues in the neural networks is the large-scale realization of the brain network. Indeed, if the maximum number of digitally implemented neurons is increased, we have a real neuromorphic hardware that is capable of reproducing brain behaviors. Consequently, the proposed model can be considered as a low-cost digital system that is used in the brain network.

6.2. Bit-Width Definition

In digital implementation, it is essential that the proposed model bit-width is described in detail for reducing the final hardware costs. As a first step, based on all parameters and variables of the proposed model, the number of integers and fraction parts must be calculated. In this way, for the proposed DSSN model, the maximum and minimum values are 16 and $-1.3177$, respectively. These values require the bit number of 4 and 3 for the integer and the fraction parts, respectively. Thus, in the first state, the number of 7 can be required. Moreover, based on the scheduling diagrams of the proposed DSSN neuron model (Figure 9), in the generating paths of the output signals (V and n), the signals may be shifted to the right and left. In this condition, the bit-width is significantly varied. Based on the final calculations, by shifting the signals to the right in the semi-final steps of the basic variables, the number of 8 is added to the fraction part of the bit-width. Moreover, one bit must be calculated for the sign bit of the proposed system. Consequently, the bit-width of the final system is calculated as 16. In this calculation, the number of 4 for the integer part, the number of 11 for the fraction section, and 1 bit for sign bit are required.

6.3. Architecture Design

After presenting the scheduling diagrams of the proposed model, it is required that the proposed architecture of the digital design is considered. The overall architecture of the proposed model is depicted in Figure 10.

As can be seen in this figure, the model parameters are saved in the $Memor{y}_0$ block (parameters that are presented in Table 1 and Table 2). At first step, the $FUNC\left(V\right)$ term is realized based on the proportional scheduling diagram. After creating this basic function, some $ShifterBlocks$ (based on the Equations (7) and (8)) are applied for generating the two basic functions, $F\left(V\right)$ and $G\left(V\right)$. Then, by considering some $MultiplexerBlocks$, the final terms can be realized. These final terms and also primary signals of the basic variables (V and n) are applied to the $NeuronSignalCalculator$. This core unit is responsible for reproducing the final voltage signals based on the DSSN neuron model. The neuron calculator unit is based on the scheduling diagram that is presented in Figure 9. Finally, the neuron signals are transferred to two buffers ($BufferV$ and $Buffern$). Consequently, the final signals are applied to an 8-bit DAC (Digital to Analog Converter) and can be showed on the digital oscilloscope.

7. Production Results

The basic units of the hardware implementation are: scheduling diagrams of the basic variables, the overall architecture, and the bit-width definition. Indeed, after bit-width definition, the scheduling diagrams of the basic variables (V and n) are evaluated. In this state, all aspects have been considered to achieve an HDL digital code. On the other hand, the overall architecture is presented to show the controlling sequence of the digital implementation.

To validate the proposed DSSN model and compare this model with other implementations, it is essential that a digital hardware is selected for realizing these models on digital platforms. In this paper, the original and proposed neuron models are implemented on Xilinx Spartan-3 FPGA Board (Model: XC3S50-TQ144 Package) for validating the proposed method. On the other hand, the proposed neuron model is compared by the DSSN model that is implemented in other similar papers [96]. Using the pipelining method, the number of 250 connected neurons can be implemented on this FPGA platform by resource utilization that is presented in

Table 6. FPGA Utilization Results for the Different DSSN Models.

Resources	Proposed DSSN (Spartan-3)	Original DSSN (Spartan-3)	J. Li [96] (Spartan-6)
Number of Slices	$158(21\%)$	$610(82\%)$	$\mathrm{14,198}(26\%)$
Number of Slice Flip Flops	$445(29\%)$	$1150(75\%)$	NA
Number of 4 input LUTs	$953(62\%)$	$1050(69\%)$	$\mathrm{18,556}(68\%)$
Number of bonded IOBs	$27(5\%)$	$34(6\%)$	NA
Number of GCLKs	$1(6\%)$	$1(6\%)$	NA
DSP	NA	NA	$48(82\%)$
Block RAMs	NA	NA	$73(63\%)$
Max Speed	168 MHz	63 MHz	NA

. Two basic factors must be emphasized in this issue: first is the maximum frequency of the digital design and second is the overall saving in FPGA resources (in case of maximum number of implemented neurons on a uniqe FPGA core). As can be seen from Table 6, these two parameters are in the better form in comparison to the main DSSN model and also in comparison to the model presented in [96]. As previously mentioned, since in the proposed DSSN model, all of nonlinear parts (such as multipliers and quadratic functions) are replaced by digital SHIFTs, ADDs, and SUBs, the final frequency of the digital system will be increased, significantly. Moreover, by removing the multiplier operations in the proposed model, the overhead costs will be reduced compared to other similar models. As a result, one of the basic parameters in the realization of neural networks is the large-scale implementation. In this approach, the overall saving in the FPGA resources is an essential issue. In this paper, the overall saving in FPGA resources is higher than the original and other paper model [96]. On the other hand, using an FPGA board, the maximum number of implemented proposed neurons is higher than other models because in the Spartan-3 board that we used, the number of resources are less than the Spartan-6 FPGA board that is used in [96]. Consequently, the proposed model is in the better state in the case of large numbers of implemented neurons compared to other methods. As a result, the final FPGA-based output signals can be achieved as depicted in Figure 11. As it is illustrated in this figure, the proposed signals (implemented on FPGA board) are in the high similarity state in comparison with the original output voltage signals.

8. Discussion

Digital implementation of different parts of the central nervous system is an attractive research field for achieving a real and practical system. In this area, the basic elements of this nervous system are: neurons, synapses, and glias with large number populations and a complex real network. Thus, to have a real system, it is necessary that the large number of these neuronal cells are realized and that the complexity of their connections are also considered. As a result, the basic limitation of this issue is the large-scale digital implementation of these networks and their complex connections. On the other hand, since the hardware platforms such as FPGA have limitations (in case of internal resources), to achieve a real and large-scale design, a large number of FPGA boards must be used, which can be a vital limitations in this field. Consequently, one of the topics that can be discussed, studied, and implemented in the continuation of this type of issue is the implementation of large networks of these neurons so that we can come closer to the real brain networks. With such real systems, we can study some of the underlying brain diseases and perhaps find solutions to treat them.

9. Conclusions

The simulation and implementation of neuronal networks are the attractive research area and this requires knowledge of the central nervous system and its components. Thus, modeling the neuronal behaviors must be very significant in case of using in the neuromorphic field. The realization of these models in low-cost and high-speed form is an essential issue targeting large-scale neuromorphic networks. Different approaches can be applied for implementing these neuron models, but the target approach must cover all aspects of an efficient digital design (without any nonlinear and high-cost terms implementation such as multipliers, dividers, exponential units, quadratic terms, etc.). Consequently, in this paper, a hyperbolic-based of the DSSN neuron model is presented in case of power-2 functions without any multiplications. The proposed architecture can reproduce two basic classes of spiking signals in a good similarity and efficiency. This approach causes reducing in error calculation and increasing performances of the system in case of decreasing the required resources on FPGA platform. Since the nonlinear parts of the DSSN neural modeling have been removed, we have a multiplierless digital implementation. The proposed designed system is in the high-frequency state and has an observable cost reduction in FPGA resources compared with similar implemented neuron models. For validating and confirming the proposed approach design, Spartan-3 FPGA board can be used and considered. In this way, hardware results show that this new model is cablable for mimicking the same behaviors of the original neuronal modeling. The new proposed hardware can follow the original model in case of higher frequency and also low-cost realization condition. The results of implementation show the better state in overall saving in FPGA and also higher frequency of the proposed model about 168 MHz, which is significantly higher than the original model, 63 MHz.