A Real-Number SNP Circuit for the Adder and Subtractor with Astrocyte-like Dendrite Selection Behavior Based on Colored Spikes

Abstract

In recent years, several proposals have emerged for executing arithmetic operations using different variants of Spiking Neural P (SNP) systems. However, some of these proposals rely on distinct circuits for each arithmetic operation, while others mandate preliminary configurations for result computation. Recent research suggests that the biological brain decides to activate or inhibit specific neurons based on the operations performed, without prior preparation. Building upon this understanding, the current work introduces a real-number arithmetic SNP circuit capable of dynamically adjusting its behavior without the need for prior configuration. This adaptability is achieved by selecting between addition or subtraction through the utilization of astrocyte-like control and colored spikes. To validate its performance, the circuit was implemented on an FPGA system. The results indicate that the growth in the quantity of 10th-order digits is comparable to recent proposals in terms of hardware usage, requiring fewer neurons than alternative approaches. Moreover, the computation of floating-point numbers enhances the resolution and precision in various arithmetic applications.

1. Introduction

Spiking Neural Networks (SNNs) [1,2,3] represent the third generation of neural networks, efficiently mimicking the biological behavior of the brain [4,5]. Based on the architecture of SNNs, Ionescu et al. proposed Spiking Neural P systems in 2006 [6]. SNP systems are a class of distributed parallel computing devices inspired by the original concepts of SNN circuits, utilizing spikes for communication [6].

SNP systems follow the architecture of SNNs, utilizing spikes for communication between neurons. Each neuron can follow firing rules and forgetting rules. When a certain number of spikes satisfies a regular expression, a firing rule allows the neuron to send information (coded in spikes) to other neurons. Simultaneously, the neuron has the ability to “forget” its content when a certain number of spikes are stored. The entire system evolves synchronously, following these rules at each time unit. When no rules are available for execution, the computation halts, and the result is obtained. This computational model has proven to have the same computing power as a Turing machine.

The computational power of SNP systems has expanded by integrating more biological features, such as astrocyte behavior [7,8], neural structural plasticity [9,10], and synaptic weights [11]. Additionally, various researched variants of these circuits, like SNP systems with colored spikes [12], SNP systems with rules on synapses [13], SNP systems with dendrite behavior and astrocyte-like control [6], and SNP systems with structural plasticity [14], have been proposed and incorporated.

SNP systems have been applied in various domains, including intrusion detection [15], image hiding using visual cryptography [16], image processing [17], and Arithmetic Logic Unit functions [18,19]. However, existing circuits often involve different sections or integrate multiple modules for various operations (e.g., addition, subtraction, multiplication, etc.) [19]. Alternatively, they may require a prior configuration and are limited to computing only integer numbers [20,21,22], potentially leading to scalability issues and functional limitations.

A notable feature of colored SNP systems is the capacity to store multiple colored spikes inside neurons without changing the internal behavior or requiring different firing time steps.

To address these challenges, this document proposes a self-configuring, split-function circuit capable of performing addition and subtraction. This is achieved through astrocyte-like control and dendrite inhibition. Additionally, the use of colored spikes allows the neurons to store floating numbers as decimal representations within, eliminating the need for separating every element into different sections and requiring fewer neurons. Moreover, the final representation for displaying the computation results is easy to read, using different colors that match the decimal order for every 10th-order digit. This feature enables users to compute both integer and floating numbers without changing the circuit configuration.

The next section introduces a circuit based on neural systems, wherein the addition and subtraction operations between two operands are embedded in natural neural behavior. Implementation examples are provided to demonstrate the functionality of the circuit.

2. Signed Addition/Subtraction SNP Circuit

The proposed Signed Addition/Subtraction SNP circuit exhibits characteristics related to the astrocyte control of plasticity and pruning in SNP systems, as mentioned earlier. In this case, synapses are connected to the astrocyte $as{t}_s$ in the form of $as{t}_s=(sy{n}_{plas},t)$; that is, if the threshold t is reached by a certain number of input spikes, the astrocyte prunes the exceeded synapses to establish the addition or subtraction behavior. This aligns with the SNP systems with the structural plasticity rule introduced by Carbale et al. [14], as a modification of the original plasticity rule. This new rule is defined as $E/a_n^m\to \alpha ({\sigma }_{pre},{\sigma }_{pos})$, where E is a regular expression over O (this is explained in the Formal Definition Subsection), $\alpha \in \{+,-\}$, ${\sigma }_{pre}$ is the pre-synaptic neuron, and ${\sigma }_{pos}$ is the post-synaptic neuron. If a defined number of input colored spikes reaches the astrocyte $as{t}_s$ and matches the activation condition of the regular expression E, the input colored spikes are consumed, and the astrocyte creates or prunes synapses between the pre-synaptic neuron ${\sigma }_{pre}$ and the post-synaptic neuron ${\sigma }_{pos}$, according to the $\alpha$ value (if $\alpha$ is defined as +, the astrocyte creates synapses; if −, the synapses are pruned). Also, The proposed circuit incorporates the features of astrocyte-like control and SNP systems with colored spikes. The input numbers are segmented as follows:

$$\{a_1^m,a_2^m,\dots ,a_n^m\}$$

(1)

where

• n is the assigned color for every 10th-order exponent (i.e., ${10}^{-1}$, ${10}^0$, ${10}^1$, etc.);
• m is the number of digits with the same 10th-order exponent;
• $\{a_1^m,a_2^m,a_3^m,\dots ,a_n^m\}$ is a set of colored spikes used for representing every operand 10th-order digit.

The general circuit operation, as described in Figure 1, is divided into three main modules: 9s complement module ($9^{\prime }c$), addition and carry module ($a\&c$), and signed separation module ($ss$). In case of a subtraction operation, the $9^{\prime }c$ and $a\&c$ modules, depicted in Figure 2 and Figure 3, respectively, work in parallel and direct the corresponding outputs to the $ss$ module. The $ss$ module determines whether the result is positively signed or requires passing through the $9^{\prime }c$ module again, signifying a negative sign. In the case of an addition operation, an astrocyte prunes the $9^{\prime }c$ output, and subsequent modules operate normally.

The $9^{\prime }c$ module receives operand B colored spikes and shares the output (separated into different colored spikes) with the $a\&c$ module.

Meanwhile, the $a\&c$ module receives operand A and the $9^{\prime }c$ outcome colored spikes, sharing the sum of both inputs with the $ss$ module, shown in Figure 4. The shared number is then divided into the non-carry addition operation and the carry behavior.

Finally, the $ss$ module receives the outgoing inputs from the $a\&c$ module and determines whether the result is positively or negatively signed. In the case of a positive sign, the module triggers a positive P colored spike. For a negative sign, the module shares the addition spikes with the $9^{\prime }c$ module and triggers a negative G colored spike.

The schematic view of the module connections is shown in Figure 5.

2.1. Formal Definition

The formal definition of the signed adder–subtractor SNP circuit ${\Pi }_{SAS}$ is described as follows:

$$\begin{array}{c}\hfill {\Pi }_{SAS}=\{\mathcal{C},\mathcal{O},{\sigma }_a,{\sigma }_c,{\sigma }_{c_{aux}},{\sigma }_{S_a},{\sigma }_{S_t},{\sigma }_{S_i},syn,as{t}_s,as{t}_{u_i},\\ \hfill i{n}_{en},i{n}_{sum},i{n}_{op{A}_i},i{n}_{op{B}_i},ou{t}_i,ou{t}_{si{g}_P},ou{t}_{si{g}_G},\Delta t_d\}\end{array}$$

where

• $C=\{i,m,r,G,P\}$ is a set of colors that represents the 10th order of the input operand digits, the number of digits, the flag signal, the reset signal, and the negative/positive signals, respectively, where $i\in \{1,\dots ,n\}$;
• $O=\{a_1,\dots ,a_n\}$ is the alphabet of every colored spike;
• $\{{\sigma }_a,{\sigma }_c,{\sigma }_{c_{aux}},{\sigma }_{S_i}\}=0$; every neuron within the circuit starts with any accumulation of spikes at the beginning of the computation, where $i\in \{1,\dots ,n\}$. This set of neurons contains rules of the following form:
  • $E∕a_i^j\to a_k^l$ is the firing rule, with a regular expression E of the form $a_n^m\mid \{n,m\}\in \mathbb{N}$; $a_i^j$ defines the j number of spikes and type of color i that the neuron consumed in the process; $a_k^l$ defines the l number of spikes and the type of the color k that the neuron fires to the environment. Consider $\{i,k\}\in \{1,\dots ,n\}$ and $\{j,l\}\in \{1,\dots ,m\}$;
  • $E∕a_i^j\to \lambda$ is the inhibition rule, with a regular expression E of the form $a_n^m\mid \{n,m\}\in \mathbb{N}$; $a_i^j$ defines the j number of spikes and type of color i that the neuron consumed in the process; $\lambda$ defines a process of consumption without firing spikes to the environment. Consider $\{i,k\}\in \{1,\dots ,n\}$;
• $\{i{n}_{sum},i{n}_{op{A}_i},i{n}_{op{B}_i}\}$ is a set of inputs for the addition process activation, the separated digits for the operand A, and the separated digits of the operand B, respectively, where $i\in \{1,\dots ,n\}$;
• $\{ou{t}_i,ou{t}_{si{g}_P},ou{t}_{si{g}_G}\}$ is a set of outputs for the operation result as separated digits, positive result sign, and negative result sign, respectively, where $i\in \{i,\dots ,n\}$;
• $syn=({\sigma }_a,{\sigma }_c)\cup ({\sigma }_c,{\sigma }_{S_a})\cup ({\sigma }_{S_i},{\sigma }_{S_j})\mid i\in \{1,\dots ,n\};\mid j\in \{1,\dots ,n\}\cup ({\sigma }_{S_i},{\sigma }_{S_t})\mid i\in \{1,\dots ,n\}\cup ({\sigma }_{S_a},{\sigma }_{S_t})\cup ({\sigma }_{S_t},{\sigma }_{c_{aux}})\cup ({\sigma }_{S_t},{\sigma }_c)\cup ({\sigma }_{S_t},{\sigma }_a)\cup ({\sigma }_{c_{aux}},{\sigma }_{S_t})$. This set of synapses contains rules of the following form:
  • $E∕a_i^j\to a_k^l$ is the firing rule, with a regular expression E of the form $a_n^m\mid \{n,m\}\in \mathbb{N}$; $a_i^j$ defines the j number of spikes and type of color i that the pre-synaptic neuron consumed in the process; $a_k^l$ defines the l number of spikes and the type of the color k that the pre-synaptic neuron fires to the post-synaptic neuron. Consider $\{i,k\}\in \{1,\dots ,n\}$ and $\{j,l\}\in \{1,\dots ,m\}$;
  • $E∕a_i^j\to \lambda$ is the inhibition rule, with a regular expression E of the form $a_n^m\mid \{n,m\}\in \mathbb{N}$; $a_i^j$ defines the j number of spikes and type of color i that the pre-synaptic neuron consumed in the process; $\lambda$ defines a process of consumption without firing spikes to the post-synaptic neuron. Consider $\{i,k\}\in \{1,\dots ,n\}$;
• $\Delta t_d=\left\{[({\sigma }_i,{\sigma }_j)\to n]\right\}$; is a dendritic delay of n times from a neuron ${\sigma }_i$ towards ${\sigma }_j$;
• $as{t}_{u_i}\subseteq sy{n}^{\le k}$ of the form $as{t}_{u_i}=(sy{n}_{as{t}_j},1)$, where $k\ge 2$, $i\in \{1,\dots ,n\}$, and $j\in \{1,\dots ,n\}$. The set of synapses $sy{n}_{as{t}_j}$ is controlled by the set of astrocytes $as{t}_{u_i}$, and the threshold for every astrocyte in the set is equal to a single colored spike;
• $as{t}_s$ is the pruning astrocyte, which deletes the set of synapses $sy{n}_{as{t}_s}$ connected to it. The internal pruning astrocyte rule takes the form of $a_0∕a_0,-({\sigma }_a,{\sigma }_c)$.

2.2. Circuit Behavior

A detailed description of each module is provided below:

As previously mentioned, the circuit operates in two main ways depending on the astrocyte behavior, indicating pruning based on the operation—either addition or subtraction. In the case of addition, the $a_0$ colored spike reaching the astrocyte $as{t}_s$ triggers the dendrite pruning responsible for the complement computation connected to ${\sigma }_a$. Other than this pruning, the rest of the circuit’s functionality remains unchanged.

To ensure the synchronization of firing rules among the constituent modules within the entire circuit, the $a_0$ colored spike acts as a flag for processing other colored spikes stored within each neuron. This flag is consumed and then triggered anew at the start of each new process, effectively initiating subsequent processes through the use of dendritic delays. This innovative approach enables the circuit to perform the entire process in parallel without relying on time step counting. Moreover, this feature proves highly advantageous for integrating diverse processes and modules designed to operate in both synchronous and asynchronous modes. It eliminates the need for generating distinct channel labels to differentiate between various synapses governed by different spiking rules [23,24,25]. Additionally, it provides flexibility to incorporate multiple flag-colored spikes, thanks to the properties of colored spikes, without being limited to the use of only two distinct types of spikes [26,27].

The primary change within the circuit for performing addition operations is the dendrite pruning described above. Therefore, we will now focus on describing the subtraction operation.

The process begins at the $9^{\prime }c$ module. The schematic view of this module is shown in Figure 2.

In a subtraction operation, the B operand numbers, converted into colored spikes, are delayed one time within the incoming dendrites and further fired to the ${\sigma }_c$ neuron. Also, a single flag-colored $a_0$ spike is dispatched to the input of the ${\sigma }_a$ neuron. This $a_0$ spike is absorbed, initiating the generation of distinct labeled n colored spikes along with another flag-colored $a_0$ spike: $a_1^{10}$ spikes, $a_2^9$ spikes, …, $a_n^9$ spikes. It is important to remark that this newly generated $a_0$ colored spike is delayed nine times within the dendrite, in order to synchronize the time when all the $a_1,\dots ,a_n$ spikes arrive at the ${\sigma }_c$ neuron.

Neuron ${\sigma }_c$ begins accumulating the 9s complement for every operand B digit. These complement signals are generated in the ${\sigma }_a$ neuron, based on operand B input signals, and are annihilated by astrocytes $u_n$. These astrocytes inhibit parallel signals from the ${\sigma }_a$ and B operand incoming spikes passing through dendrite paths to neuron ${\sigma }_c$. At the same time, the ${\sigma }_a$ neuron generates $a_n^9$ spikes for every n 10th-order digit generated by operand B, except for the $a_1$ spikes’ digits. As the 9s complement process requires a final addition of a single unit for creating the complement, this is compensated by generating $a_1^{10}$ spikes instead of $a_1^9$. Thus, the ${\sigma }_a$ neuron and digitwise astrocytes create the 9s complement signals that reach ${\sigma }_c$ neuron. In the case of an addition operation, dendrites from ${\sigma }_a$ to ${\sigma }_c$ are pruned, and astrocytes attached to these paths are inhibited.

After colored spikes are stored and the $a_0$ colored spike reaches the ${\sigma }_c$ neuron, firing rules on its outgoing dendrites are activated according to the number of colored spikes associated with every 10th-order digit. The rules of the form $a_0,{\left(a_n^{\ge 1}\right)}^{+}∕a_0,a_n^{\ge 1}\to a_n^{\ge 1}$ fire the corresponding $\ge 1$ colored spikes when both $a_n^{\ge 1}$ and $a_0$ exist within. There is an exception for the $a_1$ spikes’ digits; when the number of this specific spike within the neuron surpasses or is equal to ten, in order to avoid an additional further carry computation, the carry process for $a_2$ spikes’ digits occurs by the rule $a_0,{\left(a_1^{\ge 10}\right)}^{+}∕a_0,a_1^{\ge 10}\to a_2$, generating a single $a_2$ spike. However, if this condition is not reached, the rule $a_0,{\left(a_1^{<10}\right)}^{+}∕a_0,a_1^{<10}\to a_1^{<10}$ works in the same way as the last mentioned rules.

Once the $a_0$ spike reaches the ${\sigma }_c$ neuron, these spikes are consumed and sent to post-synaptic neurons ${\sigma }_{S_a}$, ${\sigma }_{S_1}$, …, ${\sigma }_{S_n}$, accompanied by a new outgoing $a_0$ spike directed to the ${\sigma }_{S_a}$ and ${\sigma }_{S_1}$ neurons. This new spike is delayed ten times in the dendrite to synchronize the further process in the $a\&c$ module.

Simultaneous to the operation of the 9′c module, the $a\&c$ module performs the non-carry addition operation and carry behavior. The schematic view of this module is shown in Figure 3.

The spikes corresponding to the operand A numbers are accumulated in neurons ${\sigma }_{S_a}$, ${\sigma }_{S_1}$, …, ${\sigma }_{S_n}$, based on their respective 10th-order digits.

Neuron ${\sigma }_{S_a}$ possesses a distinct set of rules within its soma and attached to outgoing dendrites. The inhibition rules take the form ${\left(a_1^{\ge 10}\right)}^{+}∕a_1^{\ge 10}\to \lambda ,\dots ,{\left(a_n^{\ge 10}\right)}^{+}∕a_n^{\ge 10}\to \lambda$, and the firing rules are of the form $a_0,{\left(a_1^{\le 9}\right)}^{+}∕a_0,a_1^{\le 9}\to a_1^{\le 9},\dots ,a_0,{\left(a_n^{\le 9}\right)}^{+}∕a_0,a_n^{\le 9}\to a_n^{\le 9}$. The first set of rules ensures that the incoming stored colored spikes for every 10th-order digit do not exceed nine spikes, thus performing an addition operation without carry behavior. Meanwhile, the second set fires the accumulated colored spikes to the ${\sigma }_{S_t}$ neuron when the $a_0$ spike, coming from the ${\sigma }_c$ neuron, is consumed and processed along with the other colored spikes within. It also fires a new flag-colored $a_0$ spike, which is delayed nine times within the dendrite path, to ensure adequate synchronization with the $ss$ module.

On the other hand, ${\sigma }_{S_1},\dots ,{\sigma }_{S_n}$ neurons possess four different kinds of rules: firing-to-${\sigma }_{S_t}$ rules (located along dendrite paths going to the $ss$ module), firing-to-${\sigma }_{S_n}$ rules (located along dendrite paths going to further ${\sigma }_{S_{n+1}}$ neurons), flag rules (also connected to dendrite paths going to subsequent ${\sigma }_{S_{n+1}}$ neurons), and inhibition rules (located within the neurons). The first set of rules, described as $a_0,{\left(a_n^{>9}\right)}^{+}∕a_0,a_n^{>9}\to a_{n+1}^1$, fires a single $a_{n+1}$ colored spike to the ${\sigma }_{S_t}$ neuron when accumulated $a_n$ colored spikes within ${\sigma }_{S_n}$ surpass nine spikes, being consumed and creating a carry behavior (complementary to the non-carry addition operation performed in ${\sigma }_{S_a}$). The second set of rules possesses a similar functionality and is described in the same way as the previous one, but dendrite paths connect to ${\sigma }_{S_{n+1}}$ neurons to record every carry colored spike. As the whole process occurs simultaneously, the third set of rules, described as $a_0\to a_0$, fires a flag-colored $a_0$ spike to synchronize adequate non-carry addition and carry output between the already stored operand A digits and incoming carry $a_{n+1}$ colored spikes. There is an important modification for the last stated set of rules that occurs at the final 10th-order digit assigned the ${\sigma }_{S_n}$ neuron; as there is no subsequent ${\sigma }_{S_{n+1}}$ neuron, the outgoing dendrite and firing-to-${\sigma }_{S_n}$ rule does not exist. The firing-to-${\sigma }_{S_t}$ rule changes to $a_0,{\left(a_n^{>9}\right)}^{+}∕a_0,a_n^{>9}\to a_0$, and the flag rule changes to $a_0\to a_r$. The change made in the firing-to-${\sigma }_{S_t}$ rule is needed to determine the sign of the final result in the further $ss$ module, thus requiring a dendrite delay of $9-n$ times for the outgoing flag-colored $a_0$ spike. Similarly, the modification made in the flag rule changes the original outgoing flag-colored $a_0$ spike for a reset-colored $a_r$ spike, which is delayed nine times inside the dendrite path and connected to every ${\sigma }_{S_1},\dots ,{\sigma }_{S_n}$ neuron, to avoid inhibiting stored $a_n^m$ colored spikes before the addition operation and carry behavior end. This process is performed by the inhibition rule, described as $a_r,{\left(a_n^{<10}\right)}^{+}\to \lambda$. As there will be some cases where the number of stored $a_n^m$ colored spikes within ${\sigma }_{S_1},\dots ,{\sigma }_{S_n}$ neurons will not be greater than nine spikes, it is necessary to remove them before using the ${\Pi }_{SAS}$ circuit again to avoid further miscalculation.

After performing the non-carry addition operation and carry behavior, the $ss$ module generates the sign for final computation. The schematic view of this module is shown in Figure 4.

Neuron ${\sigma }_{S_t}$ possesses five different kinds of rules: inhibiting rules, located within its soma; firing-to-$9^{\prime }c$ rules, located at dendrites connected to the $9^{\prime }c$ module; the flag rule, located at a dendrite also connected to the $9^{\prime }c$ module; firing-to-out rules, attached to outgoing dendrites, which fires the result of the computation; and the positive-label rule, located at a dendrite in charge of signalizing a positive result.

The carry behavior, occurring in the previous $a\&c$ module, requires a final non-carry addition operation to calculate the adequate result of the computation. Therefore, the ${\sigma }_{S_t}$ neuron requires inhibition rules for this purpose. Colored spikes coming from the $a\&c$ module are stored within ${\sigma }_{S_t}$, and the inhibition rules take the form ${\left(a_2^{\ge 10}\right)}^{+}∕a_2^{\ge 10}\to \lambda ,\dots ,{\left(a_n^{\ge 10}\right)}^{+}∕a_n^{\ge 10}\to \lambda$. After storing all incoming colored spikes, there are two different cases for signaling the process, according to the number of incoming $a_0$ flag-colored spikes; every time a positive-sign result is processed, the $a\&c$ module fires two $a_0$ colored spikes to the $ss$ module. On the other hand, the $a\&c$ module only fires a single $a_0$ flag-colored spike if a negative-sign result is being processed.

The first case occurs when two $a_0$ flag-colored spikes reach the ${\sigma }_{s_T}$ neuron at the same time; firing-to-out rules fire all the accumulated $a_1^m,\dots ,a_n^m$ colored spikes stored within the neuron, and the positive-labeled rule fires a positive P sign-colored spike, thus creating the final result, then computation halts, giving a positive-sign value.

The second case occurs when only one $a_0$ flag-colored spike reaches ${\sigma }_{S_t}$. This signal activates the firing-to-$9^{\prime }c$ rules, and the neuron fires all the accumulated $a_1^m,\dots ,a_n^m$ colored spikes to the ${\sigma }_c$ neuron, while the flag rule fires an $a_0$ colored spike, which is separated into two different paths: the first one going to the ${\sigma }_a$ neuron for activating the 9s complement computation again and the second one, connected to ${\sigma }_{c_{aux}}$, being delayed 25 times within the dendrite, in order to synchronize the process for negative signalization. The $a_1^m,\dots ,a_n^m$ colored spikes for this new 9s complement process are annihilated by a different set of $u_n$ astrocytes, connected in parallel with the ${\sigma }_a$ and ${\sigma }_{c_{aux}}$ neurons’ outgoing dendrites, just as occurred in the $9^{\prime }c$ module.

The negative signalizing ${\sigma }_{c_{aux}}$ neuron contains three different sets of rules, located at its outgoing dendrites’ paths: the flag rule, the positive-sign rule, and the negative-sign rule. Once the previously delayed $a_0$ flag-colored spike reaches ${\sigma }_{c_{aux}}$, three different signal-colored spikes are fired: the flag rule, defined as $a_0\to a_0$, fires a single $a_0$ colored spike to the ${\sigma }_{S_t}$ neuron, and it is delayed nine times within the dendrite path; the positive-sign rule, defined as $a_0\to a_P$, fires a positive P sign-colored spike, which is delayed 11 times within the dendrite path; finally, the negative-sign rule, defined as $a_0\to a_G$, fires a negative G sign-colored spike, which is also delayed 11 times within the dendrite path. It is important to remark that all the mentioned dendrite delays serve synchronization purposes. By the time the ${\sigma }_{c_{aux}}$ neuron fires all the signal-colored spikes, incoming spikes from the $a\&c$ module are accumulated in the ${\sigma }_{S_t}$ neuron anew. In order to avoid the activation of firing-to-$9^{\prime }c$ rules again, the incoming $a_0$ colored spike from the ${\sigma }_{c_{aux}}$ neuron (aided by the $a_0$ flag-colored spike from the $a\&c$ module) activates the firing-to-out rules. As a positive P sign-colored spike is fired at the same time as the other P sign-colored spike (coming from the ${\sigma }_{c_{aux}}$ neuron), these parallel signals are connected to the $u_s$ astrocyte, thus annihilating both to avoid an incorrect signalized result. The only sign-colored spike that reaches the final result is the negative G sign-colored spike (coming from the ${\sigma }_{c_{aux}}$ neuron), and the computation halts.

It is important to remark that, when the ${\Pi }_{SAS}$ circuit performs an addition operation, the second case for negative signalization is never reached.

Two simple examples are explained as follows: The first example, shown in

Table 1. Spike accumulation in the ${\Pi }_{SAS}$ circuit neurons, for an addition operation of $6.4+5.0=11.4$.

Time Steps	${\mathit{\sigma }}_{\mathit{a}}$	${\mathit{\sigma }}_{\mathit{c}}$	${\mathit{\sigma }}_{{\mathit{S}}_{\mathit{a}}}$	${\mathit{\sigma }}_{{\mathit{S}}_1}$	${\mathit{\sigma }}_{{\mathit{S}}_2}$	${\mathit{\sigma }}_{{\mathit{S}}_{\mathit{t}}}$
$t=0$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_2^0$, $a_3^0$	$a_1^0$, $a_2^0$, $a_3^0$
$t=12$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^5$	$a_1^4$, $a_2^6$	$a_1^4$, $a_2^0$	$a_2^6$, $a_3^0$	$a_1^0$, $a_2^0$, $a_3^0$
$t=24$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_1^4$, $a_2^1$	$a_1^0$, $a_2^0$	$a_2^0$, $a_3^1$	$a_1^0$, $a_2^0$, $a_3^0$
$t=36$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_2^0$, $a_3^0$	$a_1^4$, $a_2^1$, $a_3^1$

, represents the addition operation between $6.4$ and $5.0$. At time $t=0$, there are no colored spikes accumulated in the neurons. Then, at $t=12$, the separated digits for each operand are accumulated in the neurons ${\sigma }_c$, ${\sigma }_{S_a}$, ${\sigma }_{S_1}$, and ${\sigma }_{S_2}$. In the next step, at $t=24$, the ${\sigma }_{S_a}$ neuron accumulates the addition of both operands without considering the carry behavior. Meanwhile, the ${\sigma }_{S_1}$ and ${\sigma }_{S_2}$ neurons accumulate only the carry addition between the operands. Finally, in the step at $t=36$, all the neurons fire the accumulated colored spikes to the ${\sigma }_{S_t}$ neuron, where the operation result is stored.

The second example, shown in

Table 2. Spike accumulation in the ${\Pi }_{SAS}$ circuit neurons, for a subtraction operation of $6.4-5.0=1.4$.

Time Steps	${\mathit{\sigma }}_{\mathit{a}}$	${\mathit{\sigma }}_{\mathit{c}}$	${\mathit{\sigma }}_{{\mathit{S}}_{\mathit{a}}}$	${\mathit{\sigma }}_{{\mathit{S}}_1}$	${\mathit{\sigma }}_{{\mathit{S}}_2}$	${\mathit{\sigma }}_{{\mathit{S}}_{\mathit{t}}}$
$t=1$	$a_1^{10}$, $a_2^9$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_2^0$, $a_3^0$	$a_1^0$, $a_2^0$, $a_3^0$
$t=12$	$a_1^0$, $a_2^0$	$a_1^{10}$, $a_2^4$	$a_1^4$, $a_2^6$	$a_1^4$, $a_2^0$	$a_2^6$, $a_3^0$	$a_1^0$, $a_2^0$, $a_3^0$
$t=24$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_1^4$, $a_2^1$	$a_1^0$, $a_2^0$	$a_2^5$, $a_3^0$	$a_1^0$, $a_2^0$, $a_3^0$
$t=36$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_1^0$, $a_2^0$	$a_2^0$, $a_3^0$	$a_1^4$, $a_2^1$, $a_3^0$

, represents the subtraction operation between $6.4$ and $5.0$. The first step at $t=1$ starts with the preparation in the ${\sigma }_a$ neuron for the 9s complement of the second operand (colored spikes are not accumulated in this neuron when an addition operation is performed). After that, in step $t=12$, the ${\sigma }_{S_a}$, ${\sigma }_{S_1}$, and ${\sigma }_{S_2}$ neurons accumulate the operands’ digits, and the ${\sigma }_c$ neuron stores the addition of the first operand digits and the 9s complement conversion of the second operand digits. Similar to the previous example, at step $t=24$, the ${\sigma }_{S_a}$ neuron converts the accumulated spikes in the ${\sigma }_c$ neuron into an addition without the carry behavior. Meanwhile, the ${\sigma }_{S_1}$ and ${\sigma }_{S_2}$ neurons accumulate only the carry addition between the operands. Lastly, at step $t=36$, all the neurons fire the accumulated colored spikes to the ${\sigma }_{S_t}$ neuron, where the subtraction operation result is stored.

3. Hardware Implementation

In this section, a revision of four examples is performed to evaluate the proposed SNP signed addition and subtraction circuit ${\Pi }_{SAS}$. It has been implemented in an Altera Cyclone V FPGA, which has 29,080 adaptive logic modules (ALMs) and runs at 50 MHz.

For these examples, the implementation uses up to three 10th-order digits for every operand. The ${\Pi }_{SAS}$ circuit, with the ability to actively choose the operation it will perform, requires 1087 ALMs.

In the first example, the ${\Pi }_{SAS}$ circuit was tested using two operands of two digits each, as shown in Figure 6. The operand inputs are $op{A}_{1,2}=4,6$ and $op{B}_{1,2}=0,5$; the $a_0$ addition flag-colored spike is not fired; thus, a subtraction is performed between $6.4$ minus $5.0$. When the computation halts, the result is represented in colored spikes ($1.4$), with a positive-labeled spike, after 36 clock cycles.

For the next example, the circuit was tested using the same number of operands, but changing the number to three 10th-order digits for each, as shown in Figure 7. The operand inputs are $op{A}_{1,2,3}=7,2,3$ and $op{B}_{1,2,3}=5,1,3$. The addition flag-colored $a_0$ spike is not fired, and the subtraction is performed between $3.27$ minus $3.15$. When the computation halts, the result is represented in colored spikes ($0.12$), with a positive-labeled spike, after 36 clock cycles.

Using the same number of operands and 10th-order digits, as shown in Figure 8, the operand inputs are $op{A}_{1,2,3}=2,1,3$ and $op{B}_{1,2,3}=1,7,5$. The addition flag-colored $a_0$ spike is not fired, and the subtraction is performed between $3.12$ minus $5.71$. When the computation halts, the result is represented in colored spikes ($-2.59$), with a negative-labeled spike, after 72 clock cycles.

As mentioned before, the circuit can be set to perform addition operations. For the last example, shown in Figure 9, the operand inputs are $op{A}_{1,2,3}=3,6,2$ and $op{B}_{1,2,3}=4,2,3$; the addition flag-colored $a_0$ spike is fired, and the addition is performed between $2.63$ plus $3.24$. When the computation halts, the result is represented in colored spikes ($5.87$), with a positive-labeled spike, after 36 clock cycles.

The ${\Pi }_{SAS}$ circuit was tested by performing subtraction and addition operations between two operands. For the subtraction operation, obtaining a positive-labeled sign spike output, the circuit needs 34 clock cycles to compute the result. The same clock cycle numbers are needed to compute an addition operation, obtaining a positive-labeled sign spike output. On the other hand, a subtraction operation, obtaining a negative-labeled sign spike output, needs 72 clock cycles to compute the result because the $9^{\prime }c$ module processes the first output to obtain the correct computation.

The ${\Pi }_{SAS}$ circuit is capable of processing the subtraction and addition operations with operands of a high number of 10th-order digits, without the need for drastically increasing the clock cycle number required for the computation.

4. Conclusions and Future Work

In this paper, we presented a reliable and compact circuit designed for hardware implementation, capable of performing addition and subtraction operations between real numbers. Utilizing colored spikes and dendrite rules, a smaller number of neurons are required to compute the addition and subtraction behavior. This allows the circuit to have an active simple self-configuration switch, requiring a single spike to perform this action. It also uses a set of two colors to precisely differentiate the sign of the operation result.

The comparison of the performance for the proposed circuit’s simulation time step usage, given by the time usage functions shown in

Table 3. Time step growth for positive-signed results, where y is the time step cycles and x is the number of digits used for every operand.

Frias et al. (2018) [28]	Our Proposal
$y=28+2(x-1)$	$y=\left\{\begin{array}{cc}34,\hfill & x\le 9\hfill \\ 25+x,\hfill & x>9\hfill \end{array}\right.$

and

Table 4. Time step growth for negative-signed results, where y is the time step cycles and x is the number of digits used for every operand.

Frias et al. (2018) [28]	Our Proposal
$y=28+2(x-1)$	$y=\left\{\begin{array}{cc}72,\hfill & x\le 9\hfill \\ 63+x,\hfill & x>9\hfill \end{array}\right.$

, is depicted in Figure 10. Also, the comparison of the growth of the quantity of neurons shown by the functions in

Table 5. Neuron growth, where n is the number of neurons required for performing all the functions and x is the number of digits used for every operand.

Frias et al. (2018) [28]	Our Proposal
$n=12x$	$n=5+x$

is illustrated in Figure 11.

In the first graph, Frias et al.’s proposal [28] shows the same amount of time step usage for performing the addition and subtraction operations. The proposed circuit requires fewer time steps as the number of 10th-order digits increases for performing addition operations. Thus, for a result with a resolution of six 10th-order digits, it requires two time steps less than the Frias et al. proposal (the time gap increases with the number of 10th-order digits).

This feature is especially useful for applications that require the use of large numbers (15 or more 10th-order digits), such as prime number cryptography [29] and accuracy for positioning systems [30]. However, the time needed for performing subtraction operations is higher, and it requires at least a result of 38 10th-order digits for using fewer time steps.

On the other hand, the second graph shows the number of neurons required for performing the computation in both proposals. For the applications mentioned above, Frias et al.’s proposal uses 198 neurons for the computation of a 15-digit result, while our proposal only requires 20 neurons for computing the same result. Thus, the use of colored spikes significantly decreases the neurons required for every operation.

Working with real numbers implies the use of floating numbers. Using colored spikes facilitates digit separation and permits a single neuron to store multiple types of colored spikes within. But also, changing between performing the addition and subtraction operations only requires a single spike configuration, and the whole circuit behavior is set using plasticity with astrocyte control.

As future work, the improvement of time step usage for the subtraction operations is one of the main concerns, so the circuit will require a lower number of cycles to compute the results of at least 15 10th-order digits (according to the mentioned applications). Also, the addition of functionalities for this circuit will be evaluated, so it does not require a huge structural change, being capable of performing multiplication and division operations, increasing decimal resolution, and managing computation for numbers with a different quantity of 10th-order digits. New proposals will permit the implementation for applications in finite field arithmetic.