A New Class of Braided Block Codes Constructed by Convolutional Interleavers

Abstract

Parallel Concatenated Block (PCB) codes are conventionally represented as high-rate codes with low error correcting capability. To form a reliable and outstanding code, this paper presents a modification on the structure of PCB codes, which is accomplished by encoding some parity bits of one of their component codes. For the newly proposed code, named as the braided code, non-stuff bit-based convolutional interleavers are applied, aiming to minimize the design complexity while ensuring the proper permutations of the original message and selected parity bits. To precisely determine the error correcting capability, a tight bound for the minimum weight of braided code is presented. Additionally, further analyses are provided, which verify iterative decoding performance and the complexity of the constructed code. It is concluded that an outstanding braided code is formed by utilizing a reasonable number of iterations applied at its decoding processes, while maintaining its design complexity at a level similar to other well-known codes. The significant performance of short and long-length-based braided codes is evident in both waterfall and error floor regions.

1. Introduction

Advanced Forward Error Correcting (FEC) codes are fundamentally constructed using the combination of two or more basic codes in the serial, parallel, or hybrid form. Amongst concatenated codes, the Parallel Concatenated Block (PCB) code has less interest as it does not provide an error-correcting capability at a level similar to its counterparts. This is due to the non-recursive structure of its constituent codes as well as the lack of parity-on-parity bits, which conclude a low minimum weight for the code obtained from messages with weight one [1]. This means that conventional interleavers do not significantly impact the performance of the PCB code.

As a solution, stuff bit-based interleavers were proposed, which add some redundant bits (with the value of zero) to the permuted data aiming to mitigate the multiplicity of the minimum weight of the component code and provide the proper permuted data for the component code [2]. Although these interleavers improve the performance of PCB codes, their block (frame) error-correcting capability is not at the same level as outstanding codes.

PCB code designed using the abovementioned structure applied either Euclidean Geometry (EG) or Projective Geometry (PG) cyclic Low-Density Parity Check (LDPC) codes in its structure [3]. These codes, classified as Finite Geometry (FG) codes, do not have harmful trapping sets in their Tanner graphs [4]. This means that the performance of the PCB code constituted by FG LDPC codes is relevant to the minimum weight parameter.

As a result, to overcome the existing issue of such PCB code, it is essential to increase its minimum weight significantly. This is achievable by utilizing braided block codes, in which codewords obtained from a constituent code of the PCB code are interleaved and then encoded using the alternative constituent code [5]. Due to the encoding of parity bits of the codeword, braided block codes are considered as a class of product codes. The structure of these codes can also be modified by encoding rotated parity bits or through removing a number of them placed at a two-dimensionally formed codeword in a specific manner to construct the staircase or half braided codes [6,7], respectively. They mainly utilize Bose–Chaudhuri–Hocquenghem (BCH) codes as their component codes, which allow them to apply an efficient hard decision-based decoding technique [8,9]. Recently, a new scheme of these codes, i.e., zipper code, represented as a Spatially-Coupled (SC) product-type code, was introduced, which provides high performance and throughput for high-speed transmission systems. The combining of this code with other codes, particularly with the LDPC code, was also investigated in [10,11].

There exist several SC codes, which are fundamentally formed by turbo-like component codes [12,13,14]. These codes are represented as capacity-approaching codes for different channels when a long-length and relatively low rate (codes with a rate of 1/3 or lower) together with a pipeline decoding algorithm are applied to their structure. Similarly, serially SC codes are represented, where an inner convolutional code encodes parity bits of the outer convolutional code [15,16].

Alternatively, partial SC-LDPC code is designed using the coping fractions of a LDPC protograph in an efficient way to mitigate the gap between the proposed and original codes [17]. Partial-product LDPC block codes can also be formed by free riding codes, which transmit a few numbers of bits compared to the original code allocated for the column-wise encoding [18,19,20]. As partial columns check bits are transmitted, codes with higher rates are constructed. These codes mainly apply a soft decision decoding algorithm for one of the constituent codes, while a hard decision-based decoding algorithm is implemented for another constituent code.

Despite the above braided block coding or SC coding techniques, which apply a combination of soft and hard decision decoding techniques, some services for satellite communications, broadcasting systems, and similar ones require an outstanding code with a medium to low rate. This feature motivates us to implement a reliable soft decision-based decoding technique for the braided block code, whose performance and design complexity maintain it as the competitive code to other well-known ones.

Contributions:

• To achieve the abovementioned goal, a new scheme of the braided block code is accomplished, whose component codes (FG and EG LDPC codes) are decoded using the Min-Sum Algorithm (MSA).
• Instead of re-encoding all codeword bits, the first encoder concentrates on the most important parity bits; those contribute to the generation of low-weight codewords. This is achievable by determining the low weight distribution of the constituent code when messages with weights 1 and 2 are encoded. Then, some parity bits contributed to those weights of codewords are interleaved and encoded by the second constituent encoder.
• The paper applies a non-stuff bit-based convolutional interleaver. Similar to the messages, the permutation of the selected parity bits is conducted by the convolutional interleaver. As a convolutional interleaver is flexible to permute data with different lengths, one interleaver for the permutation of both messages and selected parity bits is applied. Despite the method proposed in [2], the convolutional interleaver used for the braided code does not add any stuff bits to the interleaved data. However, it still guarantees that only one bit of a message block is placed in an interleaved data block.
• Based on the interleaver specifications, the minimum weight of braided code is presented. It is proven that the obtained minimum weight is much greater than the minimum weight of PCB code.
• A comprehensive analysis is provided to extract the advantage of the braided code. It is shown that codes have outstanding performance, while they require similar or lower computation on their iterative decoding compared to other well-known codes.

The paper is organized as follows: Section 2 gives non-stuff bits-based convolutional interleavers for the PCB code. The structure of the braided code is explained in Section 3. Section 4 and Section 5 discuss the convergence behavior of the iterative decoding and latency of the proposed code, respectively. Section 6 compares the performance of braided codes with PCB codes through their upper bounds of probability of bit and block errors. Section 7 gives simulation results and finally Section 8 concludes the paper. To read this article better, we summarize the abbreviations in

Table A1. Description of the utilizied symbols.

Symbol	Description
L	Message length
k	Message length of cyclic codes
n	Codeword length of cyclic codes
T	Period of convolutional interleavers
$L_{int}$	Interleaver length
M	Space value of the convolutional interleavers
$d_{\min }$	Minimum weight of $(n,k)$ cyclic codes
$N_{block}$	Number of message and interleaved blocks
$N_{w_{msg}}$	Multiplicity of $d_{\min }$ from encoding of messages
$N_{w_{int}}$	Multiplicity of $d_{\min }$ from encoding of interleaved messages
$W_{msg}$	Weight of the message block
$W_{cw}$	Codeword weight of $(n,k)$ code obatined from encoding of k message blocks
$W_p$	Weight of parity bits of $(n,k)$ code obtained from encoding of k interleaved message blocks
$n_{pr}$	Number of selected parity bits
$N_{\left(W_{msg}\right)}$	Multiplicity of $W_{msg}$
${\left[{\left(W_{sp}\right)}_{blk}\right]}_{\min }$	Minimum weight of selected parity bits per block
$N_{{\left[{\left(W_{sp}\right)}_{blk}\right]}_{\min }}$	Multiplicity of ${\left[{\left(W_{sp}\right)}_{blk}\right]}_{\min }$
$[{\left[{\left(W_{par}\right]}_{sp}\right]}_{\min }$	Minimum weight of parity bits obtained from encoding of the selected parity bits
${\left(d_{\min }\right)}_{br}$	Minimum weight of the braided code
${\left(W_{msg}\right)}_{tot}$	Weight of the message
$N_{interact}$	Number of iterations applied for the interactive iterative decoding
${\left(L_e\right)}_{m_i}$	soft output extrinsic information relevant to the ith message $\left(m_i\right)$
${\left(L_e\right)}_{\pi \left(m_i\right)}$	soft output extrinsic information relevant to the ith interleaved message $\left(\pi \left(m_i\right)\right)$
$L_{SCL}$	Successive cancellation list size

.

2. Non-Stuff-Based Convolutional Interleaver for PCB Codes

Figure 1 shows the encoder structure of PCB codes, whose constituent codes (codes 1 and 2) are identical [21]. The code accepts messages with the length of $L=k\times k$ bits, where k is a positive integer. Every message with the length L is changed to k blocks with the length of k bits and considered as the input of $(n,k)$ constituent encoders. These blocks are named message blocks. A codeword with the length of n obtained from the first encoder (code 1) is added to the parity bits of the second encoder (code 2) to make a new codeword with the length of $(2n-k)$. Finally, k codewords with the length of $(2n-k)$ are multiplexed to make a codeword with the length of $k\times (2n-k)$. Hence, its code rate is ${\displaystyle \frac{L}{k\times (2n-k)}}={\displaystyle \frac{k}{2n-k}}$.

In [2], a new technique for the interleaving of messages was presented, which adds some stuff bits to the permuted data to obtain the minimum weight of the PCB code from messages with weight one and reduce the multiplicity of the minimum weight. This is accomplished by the $(T,L_{int},M)$ convolutional interleaver, which consists of T parallel lines represented as its period. Conventionally, each line has M memory units more than the previous line, which defines the space value. The interleaver accepts data with an arbitrary length of $L_{int}$, where $L_{int}\ge T(T-1)M$. Hence, depending on the data distribution to each line, the interleaved data will appear in different time slots. Figure 2 shows the general structure of $(T,L_{int},M)$ interleaver [22]. Based on $M=1$, such interleaved data with the length of ${(T-1)}^2$ together with stuff bits are represented as $\left(2\right(T-1)-1)\times T$ matrix. Two submatrices can define this matrix. The first one includes the matrix’s first $(T-1)$ rows, while the last $(T-2)$ rows form the second submatrix. The first and second submatrices have ${\displaystyle \frac{T(T-1)}{2}}$ and ${\displaystyle \frac{T(T-1)}{2}}-1$ stuff bits, respectively.

Despite the above structure, it is possible to obtain interleaved data without any stuff bits when the convolutional interleaver with the period of T and length of $T^2$ is applied. In this case, ${\displaystyle \frac{T(T-1)}{2}}$ non-stuff bits of the second submatrix are used to replace ${\displaystyle \frac{T(T-1)}{2}}$ stuff bits of the first submatrix. Indeed, non-stuff bits positioned at a column of the second submatrix are placed in the same column of the first submatrix.

Figure 3 shows the application of (4,16,1) convolutional interleaver for the construction of four blocks of the permuted data. Here, $d_i$s, $0\le i\le 15$, and “x”s represent sixteen bits of a message and twelve stuff bits, respectively. Considering this structure, for PCB codes with $L=k^2$, $(k,k^2,1)$ interleaver is used to permute the messages properly.

Lemma 1.

The minimum weight of the PCB code constructed by $(k,k^2,1)$ interleaver is $2d_{\min }-1$, where $d_{\min }$ is the minimum weight of $(n,k)$ codes.

Proof. 

To gain the minimum weight of $2d_{\min }-1$, it is required to place only one bit from each message block in a block of interleaved data [2]. At the jth row of the first submatrix, $0\le j\le (T-1)$, non-stuff bits are indexed by $Tj-(T-1)i$, where $0\le i\le j$. In one row of the first submatrix, these bits originated from $\lfloor {\displaystyle \frac{Tj-(T-1)i}{T}}\rfloor =(j-i)$th message block. It is evident that for a certain value of j, each value of i returns a unique number. This concludes that all non-stuff bits placed at a row of the first submatrix are from different message blocks.

Moreover, at the second submatrix of the interleaved data, non-stuff bits of the $j^{\prime }$th row are specified by $d_{(j^{\prime }+2)T-1+(T-1)i^{\prime }}$, where $0\le j^{\prime }\le (T-2)$ and $0\le i^{\prime }\le T-(j^{\prime }+2)$. For all $i^{\prime }$s, $\lfloor {\displaystyle \frac{i^{\prime }+1}{T}}\rfloor =0$. Hence, these bits are originated from $\lfloor {\displaystyle \frac{(j^{\prime }+2)T-1+(T-1)i^{\prime }}{T}}\rfloor =(j^{\prime }+2+i^{\prime })$th message block. Again, this means that bits of the $j^{\prime }$th row of the second submatrix originated from different message blocks.

The lowest bit index in each row of the second submatrix is $(j^{\prime }+2)T-1$. This is obtained when $i^{\prime }=0$. Non-stuff bits of the $j^{\prime }$th row of this submatrix are placed at the $j^{\prime }$th row of the first submatrix. In each of $j^{\prime }$ rows of the first submatrix, the greatest bit index of non-shifted bits is $(T-1)j^{\prime }+j^{\prime }=(j^{\prime }+1)T-j^{\prime }$. The difference between the lowest index of shifted bits from the second submatrix to the first one and the greatest index of those bits placed at the first submatrix is $(j^{\prime }+2)T+-1-[(j^{\prime }+1)T-j^{\prime }=T+j^{\prime }-1$. For all $j^{\prime }$s, the above difference will be greater than the value of T. Therefore, in one row of the updated first submatrix, bits are also originated from different message blocks. Based on the structure of bits placed at the first submatrix and those shifted from the second submatrix, it is concluded that all bits of an interleaved data block are from different message blocks. As a result, the minimum weight of the PCB code is $2d_{\min }-1$, which is obtained from messages with weight one. □

3. A New Scheme of PCB Codes

EG and PG cyclic LDPC codes are free of cyclic four and do not have any harmful trapping sets in their structure [4]. Hence, the error-correcting capability of the PCB code proposed in Section 2 and formed by the mentioned cyclic codes is limited due to its low (or relatively low) minimum weight.

It is possible to form a PCB code with a high minimum weight by encoding of the codewords of $(n,k)$ codes. Such a technique is basically represented as braided coding [5]. However, the encoding of all codeword bits will significantly reduce the overall code rate and increase the design complexity. To minimize the complexity and maintain the performance of the braided block code at a high level, only a number of parity bits of one cyclic code, which contribute to the minimum and other low weights of the constituent $(n,k)$ cyclic codes are encoded. This requires determining the suitable cyclic code, which has more influence on the performance of PCB code. For this purpose, an analysis is conducted by considering messages with weights 1 and 2 that generate the minimum weight for component codes.

Table 1. Minimum weight specifications of cyclic codes.

Cyclic Code	Input Weight	${\mathit{W}}_{\mathit{msg}}\left({\mathit{W}}_{\mathit{int}}\right)$	${\mathit{N}}_{{\mathit{W}}_{\mathit{msg}}}$	${\mathit{N}}_{\mathit{block}}$	${\mathit{N}}_{{\mathit{W}}_{\mathit{int}}}$
(21,11)		1(1)	110	110	110
(63,37)	1	1(1)	740	740	740
(73,45)		1(1)	900	900	900
(21,11)		1(2)	5500	495	253
(21,11)		2(1)	385	385	286
(63,37)	2	1(2)	26,640	7030	0
(63,37)		2(1)	888	888	0
(73,45)		1(2)	396,000	8550	1665
(73,45)		2(1)	1080	1080	0

gives the minimum weights of PCB codes from messages with weights 1 and 2. Here, $N_{block}$ is the number of messages and interleaved data blocks, which simultaneously generate the minimum weight for the first and second cyclic codes. $W_{msg}$ and $W_{int}$ are also weights of the message and interleaved data blocks applied for cyclic codes, respectively. Moreover, $N_{W_{msg}}$ and $N_{W_{int}}$ are multiplicities of $d_{\min }$ of the cyclic code obtained from the message and interleaved data blocks with weights $W_{msg}$ and $W_{int}$, respectively.

Example 1.

For (3293,1369) PCB code constructed by two (63,37) EG cyclic codes of 37 blocks with length 37 originating from a message with weight two and length 1369, it is possible to have two blocks with weight one and length 37. Considering all messages with weight two, 26,640 blocks with weight one $(W_{msg}=1)$ generate the minimum weight for the first cyclic code. These message blocks applied for the first code form 7030 blocks of the interleaved data with weight two for the second cyclic code. However, none of these 7030 blocks generate the minimum weight for the second code. On the other hand, 888 message blocks with weight two generate the minimum weight for the first code. Each of these blocks will conclude two blocks of the interleaved data with weight one. Hence, 888 cases exist to obtain two blocks of interleaved data with weight one. Again, none of these blocks generate a codeword with the minimum weight for the second code.

From the above example, it is evident that for the input data with weight two, due to the proper interleaving, the multiplicity of the minimum weight relevant to the first cyclic code is greater than that obtained from the second cyclic code. This means that parity bits of the first cyclic code have more influence on the performance of the PCB code. As a result, the encoding of the most important parity bits of the first cyclic code is followed to construct a braided block code.

3.1. Selection of Important Parity Bits of the $(n,k)$ Cyclic Code

Let $W_i=\{w_{i1},w_{i2},\dots ,w_{i{\nu }_i}\}$, $1\le i\le 2$, be a set, whose elements, i.e., $w_{ij}$s, $1\le j\le {\nu }_i$, are codewords’ weights of $(n,k)$ code obtained from messages with weight i$(1\le i\le 2)$. In this case, ${\nu }_i$ represents the number of elements of $W_i$. Obviously, each of $w_{ij}$s have different multiplicities in the construction of the weight distribution of $(n,k)$ code based on messages with weight i. Define the set $S=\{k,k+1,\dots ,n-1\}$, whose elements express indices of the parity bits of codewords for $(n,k)$ code.

For $W_1$, select some parity bits having the highest contribution to the defined codewords’ weights. Such a selection from the remaining elements of S is continued to obtain the contribution of at least two elements on all codewords. In the second step, ignore the codewords of $W_2$ if the position of one of their parity bits (or more than one parity bit) is among the elements selected from the first step. Then, select some parity bits (elements of S that are not selected at the first step), which are highly contributed to the weights of the remaining codewords of $W_2$. The contribution of at least one parity bit to the weight of each codeword of $W_2$ is required.

Example 2.

The weight distribution of (15,7) cyclic LDPC code obtained from messages with weights 1 and 2 are given in

Table 2. Some weights of (15,7) cyclic code.

$\left({\mathit{W}}_{\mathit{msg}}\right)$$\left({\mathit{W}}_{\mathit{cw}}\right)$	Positions of Bit 1
1(5)	(0,7,8,9,11), (1,8,9,10,12),
	(2,9,10,11,13), (3,10,11,12,14),
	(6,7,8,10,14)
1(6)	(4,7,8,9,12,13), (5,8,9,10,13,14)
2(5)	(0,4,11,12,13), (1,4,7,10,13),
	(1,5,12,13,14), (2,5,8,11,14),
	(5,6,7,9,13)
2(6)	(0,1,7,10,11,12), (0,2,7,8,10,13),
	(0,6,9,10,11,14), (1,2,8,11,12,13),
	(1,3,8,9,11,14), (1,6,7,9,12,14)
	(2,3,9,12,13,14), (3,6,7,8,11,12),
	(4,5,7,10,12,14)
2(7)	(0,5,7,10,11,13,14), (4,6,9,10,12,13,14)
	(2,4,7,8,10,11,12), (3,5,8,9,11,12,13)
2(8)	(0,3,7,8,9,10,12,14), (2,6,7,8,9,11,13,14)
2(9)	(3,4,7,8,9,10,11,13,14)

, where $W_{msg}$ and $W_{cw}$ are weights of messages and codewords, respectively. Based on messages with weight 1, $W_1=\{5,6\}$, where $w_{11}=5$ and $w_{12}=6$ having 5 and 2 multiplicites, respectively. In this case, bits 10, 8, and 9 have the highest contributions on weights of $W_1$. The selection of these bits together with the 12th bit of the codewords guarantees that at least two of the selected bits are contributed on all weights of $W_1$. At least one of these selected bits is also in weights of $W_2$, $(W_2=\{5,6,7,8,9\})$.

3.2. Structure of the Braided Code

Figure 4 shows the encoding process of the selected parity bits of the first constituent code of the PCB code, which is highlighted by four grey blocks. Encoding of these bits and conventional PCB encoding will form the encoder of the braided code. Let $n_{pr}$, $n_{pr}<k$, be the number of parity bits selected for the encoding. Based on k message blocks applied for the first $(n,k)$ code, $k\times n_{pr}$ parity bits are considered for the encoding. These bits are interleaved by the ($n_{pr}$,$k\times n_{pr}$,1) interleaver proposed in Section 2. The interleaved data can be viewed as two-dimensional data having k rows and $n_{pr}$ columns. In this case, column-wise reading of such data provides $n_{pr}$ blocks of data with the length of k, which can be encoded by the second $(n,k)$ code.

Lemma 2.

Every block of interleaved data formed by the above interleaving has one parity bit of a codeword.

Proof. 

There exist $i^{″}$ blocks of interleaved data, $0\le i^{″}\le n_{pr}-1$, with k bits. Bits are given by $d_{j^{″}\times n_{pr}+A}$, where $0\le j^{″}\le k-1$ and $\mathrm{rem}\left({\displaystyle \frac{i^{″}}{n_{pr}}}\right)$ is the remainder of ${\displaystyle \frac{i^{″}}{n_{pr}}}$. For all $i^{″}$s, $A<n_{pr}$. Hence, $\lfloor {\displaystyle \frac{A}{n_{pr}}}\rfloor =0$ and $j^{″}$th bit of the $i^{″}$th block of interleaved data is from $\lfloor {\displaystyle \frac{j^{″}\times n_{pr}+A}{n_{pr}}}\rfloor =j^{″}$th codeword block. Thus, a block of the permuted data has one parity bit of a codeword. □

Figure 5 shows data obtained from (4,24,1) convolutional interleaver. The interleaver accepts data in the shape of six blocks with a length of four. In each of the four blocks of interleaved data, only one bit from the originally constructed six blocks exists. Such a property is guaranteed by the column-wise reading of two-dimensional interleaved data.

Theorem 1.

The minimum weight of the constructed braided block code $\left({\left(d_{\min }\right)}_{br}\right)$ is at least $4d_{\min }-3$, where $d_{\min }>3$.

Proof. 

The weight of the braided code can be expressed as the sum of the weight of the PCB code and the parity weight of the second constituted code obtained from the encoding of selected parity bits of the first codeword. In the proposed algorithm, at least two parity bits are selected from the encoding of the messages with weight one. As parity bits of a codeword block are placed in different blocks of interleaved data, the minimum parity weight obtained from the encoding of these bits is ${\left(w_p\right)}_{\min }=2(d_{\min }-1)$. The minimum weight of conventional PCB code based on messages with weight one is $2d_{\min }-1$. Therefore, the minimum weight of the braided code from messages with weight one will be $2d_{\min }-1+2(d_{\min }-1)=4d_{\min }-3$.

Similarly, the minimum weight of selected parity bits obtained from the encoding of messages with weight two is 1. This means encoding of these selected bits will form a codeword whose parity weight is at least $d_{\min }-1$. On the other hand, the minimum weight of PCB code formed from messages with weight two is $d_{\min }+2(d_{\min }-1)=3d_{\min }-2$ [2]. As a result, the minimum weight of the braided code obtained from messages with weight two will be $3d_{\min }-2+d_{\min }-1=4d_{\min }-3$.

Figure 6 shows all possibilities of the message and interleaved data blocks with weight three, which generate the minimum weight for both component codes. In case (a), only one non-zero-weight message block exists. As the weight of this message block is three, the lowest possible parity weight obtained from the encoding of the selected parity bits is zero. The minimum weight of codewords from the first encoder is $d_{\min }$. As each of bits 1 of a message block are placed in different interleaved blocks, the minimum parity weight obtained from encoding of three interleaved blocks with weight one will be $3(d_{\min }-1)$. Hence, the minimum weight of the braided code is $d_{\min }+3(d_{\min }-1)=4d_{\min }-3$. In cases (b) and (c), message blocks applied for the first encoder have weights of one or two. Considering this and the interleaving process of the selected parity bits, the lowest possible parity weights obtained from the encoding of these interleaved blocks are $2(d_{\min }-3)$ and $2d_{\min }-3$, respectively. Therefore, the minimum weights of the braided code obtained from these two cases will be $6d_{\min }-8$ and $6d_{\min }-6$. The minimum weights of utilized EG and PG codes are greater than three $(d_{\min }>3)$ [3]. Based on this and the minimum weights of the three cases, $4d_{\min }-3$ is represented as the minimum weight of the braided code.

Table 3. Possible minimum weights of braided code obtained from messages with weight 4.

$\left({\mathit{W}}_{\mathit{msg}}\right)$$\left({\mathit{N}}_{\left({\mathit{W}}_{\mathit{msg}}\right)}\right)$	${\left({\mathit{W}}_{\mathit{cw}}\right)}_{\mathbf{min}}$ +${\left({\mathit{W}}_{\mathit{p}}\right)}_{\mathbf{min}}$	${\left[{\left({\mathit{W}}_{\mathit{sp}}\right)}_{\mathit{blk}}\right]}_{\mathbf{min}}$ (${\mathit{N}}_{{\left[{\left({\mathit{W}}_{\mathit{sp}}\right)}_{\mathit{blk}}\right]}_{\mathbf{min}}}$)	${\left[{\left[{\mathit{W}}_{\mathit{par}}\right]}_{\mathit{sp}}\right]}_{\mathbf{min}}$	${\left({\mathit{d}}_{\mathbf{min}}\right)}_{\mathit{br}}$
2(2)	4$d_{\min }-$4	2(1)	$d_{\min }-2$	5$d_{\min }-$6
1(4)	5$d_{\min }-$4	4(2)	$2(d_{\min }-4)$	7$d_{\min }-$12
1(2)		2(1)
2(1)	5$d_{\min }-$4	3(1)	$2d_{\min }-5$	7$d_{\min }-$9
1(1)		1(2)
3(1)	5$d_{\min }-$4	0(0)	$2(d_{\min }-1)$	7$d_{\min }-$6
4(1)	5$d_{\min }-$4	0(0)	0	$5d_{\min }-4$

gives minimum weights of the braided code relevant to the encoding of messages with weight four, where $N_{\left(W_{msg}\right)}$ represents the multiplicity of $W_{msg}$. In this table, ${\left[{\left(W_{sp}\right)}_{blk}\right]}_{\min }$ and $N_{{\left[{\left(W_{sp}\right)}_{blk}\right]}_{\min }}$ are the minimum weight of interleaved parity bits per block and its multiplicity, respectively. Moreover, ${\left[{\left[W_{par}\right]}_{sp}\right]}_{\min }$ represents the minimum parity weight generated by the encoding of the interleaved parity bits.

Again, the effect of the parity bits encoding is observed for messages whose weights are placed in more than one message block. As shown, without the encoding of the parity bits, the minimum weight of the PCB code ${\left(W_{PCB}\right)}_{\min }$ will be $4d_{\min }-4$. This is possible when each of the two message blocks and two interleaved blocks with weight two generate the minimum weight for both $(n,k)$ codes. However, the weight of the selected parity bits of each codeword will be one since each non-zero weight message block has weight of two. As these two 1s are placed at two blocks of selected parity bits (they originate from two separate codewords), the interleaving of parity bits can form one non-zero-weight block with the weight of two. Hence, the parity weight obtained from encoding of the interleaved parity bits will be $d_{\min }-2$, which consequently concludes the minimum weight of $5d_{\min }-6$ for the braided code. The above analysis can be followed for other cases given in table. From the last column, the minimum weight of $5d_{\min }-6$ is achieved for the braided code. This means the given minimum weight of the braided code is greater than $4d_{\min }-3$ obtained from encoding of messages with weights 1, 2 and 3. Similar analysis can be applied for messages with weight of five and above. The lowest possible minimum weight is from messages with even weights when 1s are equally placed at two messaged blocks. Let ${\left(W_{msg}\right)}_{tot}$ be the message weight, which is equal to the sum of weights of the message blocks $\left(W_{msg}s\right)$. For a message with even weights, the minimum weight of PCB code is ${\displaystyle \frac{{\left(W_{msg}\right)}_{tot}}{2}}(d_{\min }-2)+2d_{\min }$ (For messages with odd weights, $d_{\min }-1$ is added to the mentioned weight). If none of the selected parity bits are involved in the encoding process, ${\left[{\left(W_{par}\right)}_{sp}\right]}_{\min }=0$ and ${\left(d_{\min }\right)}_{br}$ will remain as ${\displaystyle \frac{{\left(W_{msg}\right)}_{tot}}{2}}(d_{\min }-2)+2d_{\min }$. For $d_{\min }>3$, this weight and that obtained from messages with odd weigths are greater than $4d\min -3$. Hence, ${\left(d_{\min }\right)}_{br}\ge 4d_{\min }-3$. □

As the $d_{\min }$ of cyclic LDPC codes is increased by their lengths [3], the given bound grows with the length of cyclic codes.

4. Convergence Behavior of the Iterative Decoding of the Braided Code

Figure 7 shows the structure of iterative decoding applied for the braided code. The fundamental operation is the conventional interactive decoding applied for the PCB code. Furthermore, the decoder for decoding the first cyclic code accepts two pieces of a-priori information from another decoder. This information is obtained from the deinterleaving of the interleaved messages and selected parity bits. (in Figure, two (n,k) cyclic codes that accept $(k\times n)$ and $n_{pr}\times n$ blocks of information can be represented as one decoder for decoding of $(k+n_{pr})\times n$ blocks of information).

Let ${\left(L_e\right)}_{m_i}$, ${\left(L_e\right)}_{\pi \left(m_i\right)}$, and $0\le i\le k\times n$ be the soft output extrinsic information relevant to the ith original and interleaved messages, respectively. At $N_{\left(interact\right)}$th iteration, $1\le N_{interact}\le {\left(N_{interact}\right)}_{\max }$, the interactive decoding applied between two MSA-based decoders of cyclic codes is terminated if the polarities of soft-output extrinsic information obtained from both decoders are not changed at two consecutive iterations and the difference between magnitudes of the information of a decoder input and output is small [23]. Figure 8 shows the average number of iterations applied for the iterative decoding of braided codes constructed using (73,45) and (21,11) PG cyclic LDPC codes. Codes are modulated using Binary Phase Shift Keying (BPSK) and verified for Additive White Gaussian Noise (AWGN) channel. Maximum 10 iterations are applied for the MSA-based decoder and $N_{{\left(interact\right)}_{\max }}=10$. It is evident that increasing the ${\displaystyle \frac{E_b}{N_0}}$ decreases the number of iterations. This concludes the proper error-correcting capability of the braided code at the waterfall region, which is confirmed by simulations presented in Section 7.

5. Latency of the Designed Braided Code

The latency of encoding and the interleaving of data is proportional to the number of utilized registers. For the $(n,k)$ cyclic code, $n-k$ registers are applied. For the PCB code, as k message blocks are encoded, overall, $k(n-k)$ registers are involved in the encoding of one code. On the other hand, the interleaving delay for $(T,L_{int},1)$ interleaver is ${\displaystyle \frac{T(T-1)}{2}}$[22]. This latency is added to the latency required for transferring ${\displaystyle \frac{T(T-1)}{2}}$ non-stuff bits of the second submatrix to the first one. Hence, the overall latency of the interleaving will be $T(T-1)$. For the braided code, the period of the interleaver applied for the permutation of messages is equal to the value of k. Hence, the overall interleaving latency will be $k(k-1)$.

For cyclic codes applied in the PCB code, $(n-k)\le (k-1)\le 2(n-k)$. This means that the latency generated by the interleaver is greater than that obtained from one encoder. As the message interleaving and first cyclic encoding are processed in parallel with each other after the completion of the message interleaving, the latency of the PCB encoding is only related to the second encoder. On the other hand, the latency required for the convolutional interleaving of parity bits will be $2n_{pr}(n_{pr}-1)$. The factor of 2 appeared because of the column-wise reading of the interleaved data. As $n_{pr}\le k$ and $2(n_{pr}-1)\le (n-k)$, the abovementioned latency is less than the latency of the second cyclic encoding. Therefore, during the second encoding, the interleaver constructed for the message interleaving also has enough time to permute selected parity bits of the first cyclic code. This is achievable due to the flexibility of the convolutional interleaver in permuting data with an arbitrary length. Hence, the complexities of the braided and original PCB encodings remain at the same level.

6. Upper Bound of Probability of Error for Braided Codes Constructed by the Proposed Interleaver

For a $(n,k)$ linear block code, the input-redundancy weight enumerating function (IRWEF) is defined as follows [21]:

$$A^C(W,Z)\triangleq \sum _{\omega ,j}{A}_{\omega ,j}{W}^{\omega }{Z}^j.$$

(1)

In this equation, $A_{\omega ,j}$ is the number of codewords with weight $\omega +j$, whose message and parity weights are $\omega$ and j, respectively. Based on this definition, the conditional weight enumerating function (CWEF) of the parity check bits is given by

$$A_{\omega }^C\left(Z\right)=\sum _j{A}_{\omega ,j}{Z}^j={\displaystyle \frac{1}{\omega !}}{\displaystyle \frac{{\partial }^{\omega }\left[A^C(W,Z)\right]}{\partial W^{\omega }}}{|}_{W=0}.$$

(2)

For codes implemented by a maximum likelihood soft decision decoding algorithm, the probability of error under AWGN is upper bounded by

$$P_b\left(e\right)\le \sum _{\omega =1}^k{\displaystyle \frac{\omega }{k}}{W}^{\omega }{A}_{\omega }^C{\left(Z\right)|}_{W=Z=e^{-R_C{E}_b/N_0}},$$

(3)

where $R_C$ and ${\displaystyle \frac{E_b}{N_0}}$ are the code rate and energy per bit per noise ratio, respectively.

Based on the finite number of terms, the above bound is approximated by

$$P_b\left(e\right)\le {\displaystyle \frac{1}{2}}\sum _m{D}_{m}erfc\left(\sqrt{{\displaystyle \frac{m{R}_c{E}_b}{N_0}}}\right),$$

(4)

where $D_m\triangleq {\sum }_{j+\omega =m}{\displaystyle \frac{\omega }{k}}{A}_{\omega ,j}$. Simarly, the probability of block error, represented as blcok error rate $\left(BLER\right)$, is bounded by

$$P_{blk}\left(e\right)\le k{\displaystyle \frac{1}{2}}\sum _m{D}_{m}erfc\left(\sqrt{{\displaystyle \frac{m{R}_c{E}_b}{N_0}}}\right),$$

(5)

Table 4. Partial IRWEF of braided codes.

Code	Applied EG/PG Code	$\mathit{A}(\mathit{W},\mathit{Z})$
(4797,2025)	(73,45)	$W(24Z^{36}+16Z^{38}+27Z^{40})+$
		$W^2(80Z^{36}+92Z^{37}+112Z^{39})$
		$+W^3(45Z^{34}+45Z^{36}+90Z^{38})$
(3579,1369)	(63,37)	$W(35Z^{32}+24Z^{33}+34Z^{34})+$$37W^3{Z}^{32}$
(401,121)	(21,11)	$W(9Z^{20}+2Z^{22}+48Z^{25})$
		$W^2(50Z^{19}+5Z^{21}+117Z^{24})+$
		$W^3(22Z^{18}+11Z^{20}+110Z^{23})$
(193,49)	(15,7)	$W(15Z^{14}+10Z^{17}+3Z^{18})$
		$W^2(25Z^{16}+10Z^{17})+$
		$W^3(14Z^{14}+7Z^{16})$

gives partial IRWEF of braided codes constructed by different EG and PG cyclic codes. Weights are obtained from messages whose weights are not greater than three and placed in one block.

It is concluded that (4797,2025) and (401,121) codes have the minimum weight from messages with weights 1, 2, and 3. By contrast, the minimum weight of (193,49) is obtained from messages with weights 1 and 3, while for (3579,1369) code, it is only generated from messages with weight 1.

Figure 9 shows the upper bounds of the probability of bit and block errors for (193,49) and (401,121) braided codes and their performance obtained from simulations. It also shows bounds for (161,49) and (341,121) PCB codes. For braided codes, the three lowest weights are applied, while for PCB code, only the minimum weight is considered (minimum weight of (161,49) is 9 with 35 multiplicities, while (341,121) PCB code has a minimum weight of 11 with 110 multiplicities). Constituent (21,11) and (15,7) cyclic codes implemented for the encoding of messages with lengths 49 and 121 are decoded by the MSA with no more than ten iterations, respectively. Moreover, twenty iterations are used for the iterative decoding of MSA-based decoders. It is confirmed that at the medium to high signal-to-noise ratios, BER and BLER performances of braided codes modulated by BPSK are compatible with their relevant upper bounds. For (193,49) code, this is evident at ${\displaystyle \frac{E_b}{N_0}}\ge 4.0$ dB, while for $(401,121)$ code, it occurs at ${\displaystyle \frac{E_b}{N_0}}\ge 3.5$ dB. As expected, the given bounds demonstrate that braided codes have better error-correcting capability compared to their PCB codes.

To verify the effectiveness of the correct selection of parity bits, Figure 10 shows the performance of the (193,49) braided code formed by three different sets of parity bits. The braided code constructed by the 8th, 9th, 10th, and 12 parity bits $(Se{l}_{b}its=8,9,10,12)$ outperforms two other codes. This is an expected result because, in two other codes, two parity bits of all codewords obtained from messages with weight one are not encoded. In the iterative decoding of codes, 20 iterations are applied. In this case, for the decoding of cyclic codes, maximum 10 iterations are considered.

7. Simulation Results

Table 5. Codes applied in simulations.

Description	Code
	(391,121) ($C_{a1}$, with convolutional interleaver)
	(391,121) ($C_{a5}$, with row-column interleaver)
Braided codes	(3579,1369) ($C_{b1}$ with $N_{interact=6}$)
	(3579,1369) ($C_{b3}$ with $N_{interact=8}$)
	(4797,2025) ($C_{c1}$)
	(361,121) ($C_{a2}$)
PCB codes	(3345,1369) ($C_{b2}$)
	(4601,2025) ($C_{c2}$)
	(401,121) ($C_{a3}$ with $L_{SCL}=8$)
	(391,121) ($C_{a6}$ with $L_{SCL}=16$)
Polar codes	(3579,1369) ($C_{b4}$with $L_{SCL}=16$)
	(3579,1369) ($C_{b5}$with $L_{SCL}=32$)
	(4601,2025) ($C_{c3}$)
LDPC codes	(500,125) ($C_{a4}$)
	(4608,2304) ($C_{c4})$

represents codes applied in simulations. In simulations, the codewords of the braided block codes are also modulated by BPSK and verified for the AWGN channel. Constituent EG and PG cyclic LDPC codes are decoded by the MSA with no more than ten iterations $({\left(N_{MSA}\right)}_{\max }=10)$. Maximum ten iterations are also applied for the interactive decoding of MSA-based decoders $({\left(N_{interact}\right)}_{\max }=10)$. The performance of braided codes is compared with the punctured polar codes, which are decoded by the Successive Cancellation List (SCL) algorithm (polar codes are constructed by the Gaussian approximation method). These codes are also assisted by the Cyclic Redundancy Check (CRC) codes. Puncturing on their lengths is accomplished based on the Worst Quality Puncturing (WQP) algorithm [24].

Figure 11 shows the Bit Error Rate (BER) and Block Error Rate (BLER) performances of (391,121) braided code $\left(C_{a1}\right)$ constructed by the two (21,11) PG cyclic LDPC codes with $d_{\min }=6$. The result is based on $N_{interact}=8$. With a $9\%$ reduction in the coding rate and without a visible error floor, for $BLER\le {10}^{-2}$, the braided code outperforms (361,121) PCB code $\left(C_{a2}\right)$ by $1.5$ dB. In addition, for $BER\le {10}^{-5}$ dBs, it outperforms (401,121) polar code $\left(C_{a3}\right)$ constructed by the 4-bit CRC code and the list size of $L_{SCL}=8$, while their BLER performances are the same. Such results are also observed between the braided code and (391,121) polar code constructed by the list size $L_{SCL}=16$ and 4-bit CRC. Indeed, by utilizing a greater list size and shorter length, the $BLER$ performance of polar code and braided become similar. The (401,121) braided code has a better BLER performance than the girth-8-based (500,125) QC-LDPC code $\left(C_{a4}\right)$ proposed in [25], where the reference code can provide coding gain over the 5G NR LDPC codes. Moreover, it slightly shows a better performance than the same braided code implemented by two row-column interleavers formed by $k\times k$ and $k\times n_{pr}$ matrices, which are applied in permuting messages and selected parity bits, respectively $\left(C_{a5}\right)$. (In row-column interleavers, data are written in rows of the matrix and then read column-by-column). Figure 12 shows the performances of (3579,1369) braided code $\left(C_{b1}\right)$, which is constructed by two (63,37) EG cyclic LDPC codes with $d_{\min }=9$. With the similar rate and $N_{interact}=6$, the code provides a better block error correcting capability compared to the (3345,1369) PCB code $\left(C_{b2}\right)$ presented in [1]. The error floor of the braided code decoded based on $N_{interact}=8$$\left(C_{b3}\right)$ expects at $BLER\le {10}^{-5}$ and $BER\le {10}^{-9}$, which are lower than those obtained from (3579,1369) polar codes $(C_{b4}$ and $C_{b5})$ concatenated by 4-bit CRC code and decoded by $L_{SCL}=16$ and $L_{SCL}=32$, respectively. Figure 13 shows the results of (4797,2025) braided code $\left(C_{c1}\right)$ formed by two (73,45) PG cyclic LDPC codes with $d_{\min }=10$. Based on $N_{interact}=10$, this code outperforms $(4601,2025)$ PCB $\left(C_{c2}\right)$ [2] and (4608,2304) QC-LDPC codes $\left(C_{c4}\right)$ with the girth of 8 given in [26]. The result is obtained when the braided code utilizes a lower rate than the QC-LDPC code. This code also outperforms (4601,2025) polar code $\left(C_{c3}\right)$ implemented by the 8-bit CRC and $L_{SCL}=32$. At $BER={10}^{-8}$, it is 1.83 dB away from the Shannon limit.

Decoding Complexity of Braided Codes

The overall number of sums (or products) required for the braided decoding is $(d_{\min }$$-1)\times n\times N_{interact}\times N_{MSA}\times (2k+n_{pr})$, which is proportional to the density of the utilized $(n,k)$ cyclic codes [27]. For SCL-based decoding of polar codes, this is given by $N_{polar}\times {\log }_2\left(N_{polar}\right)\times L_{SCL}$, where $N_{polar}$ is the original length of the polar code. For ${\displaystyle \frac{E_b}{N_0}}\ge 3.5$ dB, where the MSA decoding of (21,11) PG cyclic codes is conducted by few iterations, the decoding complexity of (391,121) PCB code is higher than that of formed by the (401,121) polar code. However, the maximum number of operations required for decoding $k+n_{pr}$ blocks with length n (maximum number of operations applied for the decoding unit) will be similar to the one used for the SCL decoding of the polar code. Based on $N_{interact}=10$ and $N_{MSA}\le 5$, which occurs for ${\displaystyle \frac{E_b}{N_0}}\ge 1.75$ dB, the number of operations required for the decoding of (3579,1369) braided code is slightly lower than that used for the decoding of (3579,1369) polar code with $L_{SCL}=32$. With the maximum of 50 iterations, the MSA-based decoding of (3,6) regular (4608,2304) QC-LDPC code demands $2\times 6\times 50\times 4608$ sums, which is a bit lower than the number of operations required for (4797,2025) braided code based on the average of 4 iterations for the MSA algorithm. However, the encoder of the QC code is more complex than the cyclic PG code. Hence, the overall complexity of codes is at the same level.

It is also worth mentioning that increasing the length of constituent $(n,k)$ cyclic code increases the complexity of selecting parity bits. However, most selected parity bits are from codewords formed by messages with weight 1. By choosing two parity bits from those codewords, the number of codewords obtained from messages with weight 2, which are not amongst those selected parity bits, will be significantly reduced.

8. Conclusions and Future Work

A scheme of an outstanding braided block codes constructed by the encoding of some parity bits of the PCB codeword was presented. To achieve this goal and minimize the design complexity, a non-stuff-based convolutional interleaver was applied for permuting the original message and selected parity bits. Conducted analysis proved braided codes with high minimum weights, while a reasonable number of iterations is applied in its iterative decoding process. Moreover, simulations confirmed that the code has an outstanding error-correcting capability. This is achievable for both short and long-length codes. In future work, the algorithm applied for selecting parity bits will be presented to minimize the number of parity bits involved in the encoding. This will consequently optimize the rate and complexity of the designed code.