Investigation on Performance of Single Precision Floating Point Multiplier (SPFPM) Using CSA Multiplier and Different Types of Adders ^†

Abstract

Nowadays, floating point multiplier (FPM) plays an essential role in computers. The IEEE 754 norm for floating point numbers is the most widely recognized portrayal for real numbers on today’s PCs. Addition, multiplication, subtraction, and division are the four important functions of single precision floating arithmetic, amongst which multiplication has the most extensive use in every algorithm. Fast multipliers are of critical need in modern high-performance applications, especially in digital signal processing, because DSP involves many important multiplication-based operations, e.g., fast Fourier transform (FFT) and convolution. These speedy computations can be implemented on field programmable gate arrays (FPGAs), because they can provide a high speed and a large number of on-board digital resources. FPGAs are involved in many modern applications such as cryptography and communication computations, arithmetic and scientific computation, digital image and signal processing, etc. There are many forms of FPM available. This paper describes an efficient way to implement single precision FPM in IEEE 754 standard format, where Verilog hardware description language (VHDL) is used to implement the design for Xilinx Spartan 6 FPGA. Here, the 32-bit number will be divided into three parts: sign bit, exponent, and mantissa. This paper is implemented by using different types of adders, which includes carry increment adder (CIA), carry select adder (CSA), ripple carry adder (RCA), and carry look-ahead adder (CLA). Carry save array (CSA) multiplication is used for performing the mantissa multiplication.

1. Introduction

There are many different methods to express real numbers in binary format on computers. Floating point representation is the most effective way to represent real numbers in binary form, e.g., 9876543.21 could be represented as 9.87654321 × 10⁶ [1]. Decimal interchange and binary interchange are the two distinct customary formats available in IEEE 754 for floating point (FP). Booth’s multiplier algorithm uses standard add shift operations, ultimately reducing the number of partial products, therefore achieving a speed advantage [2]. Wallace’s tree algorithm, using a tree of carry save adders, implemented a new way to add the partial component bits in parallel [3]. Vedic multiplier is based on Sutra of Vedic multiplication and reduces the hardware requirement. Sutra of Urdhava–Triyakbhayam multiplier is used for high-speed performance [4].

The proposed paper focuses on single precision multiplication only. This paper presents comparative investigation on SPFPM, and it is undertaken using carry save array multiplier and different adders such as carry skip, carry save, CLA, CIA, carry select, and RCA for calculating the addition of mantissa and for adding partial products.

2. Representation and Calculation of Floating Point in IEEE-754 Standard

According to this format, a floating point number N is represented as follows.

For 32-bit SPFP-numbers, the IEEE-754 norm has following three parts [5] and representation is shown in

Table 1. Representation of SPFP number [1].

Sign Bit	Exponent		Mantissa
b31	b31	b23	b22	b0

:

i.

The sign of the FP number is represented by the most significant bit (MSB): 0 for a positive number and 1 for a negative number. By taking the XOR of sign bit of multiplier and multiplicand, the sign-bit is consequently determined.

S = S1 ⊕ S2

(1)

ii.

Bit (30-23) is used to express a biased exponent (E). E = e + 127, where e is the actual exponent, and 127 is the bias value for single precision. We add the exponents of two numbers using a different type of 8-bit full adder. After adding the exponents of two inputs, the bias is subtracted from this using a 9-bit subtractor (to cater the carry of addition) to obtain the final output.

E = (E1 + E2) − bias

(2)

iii.

The mantissa/significand for a binary number is represented by 0 to 22 bits as shown in Table 1. Here, we are using array multiplier for this purpose as shown in Figure 1. This involves the multiplication of 24-bit (23 fraction bits and one hidden bit) mantissas of two input numbers and results a 48-bit mantissa, which is then truncated to 24 bits.

M = M1 ∗ M2

(3)

iv.

As mentioned earlier, IEEE-754 standard floating point numbers always have one ‘1’ to the left of the binary point. We ignored the binary point while multiplying the mantissa. Therefore, the lower 46 bits are placed to the left of the binary point in the result. In this case, we have two possibilities, i.e., the binary point could be in 47th or 46th place.

• In the first case, no normalization is required if the leading ‘1’ bit is in 46th place (i.e., there is just one bit ‘1’ on the left), because the result is already normalized.
• In the second case, normalization is needed if the leading ‘1’ bit is at 47th place (i.e., it occurs one bit away from the binary point). So, mantissa needs to be shifted one unit left, and consequently, the exponent also requires normalization, which is done by adding one to it.

In the final product, the output should be of 23 bits only, so we round off over the result. So, in the first case, we select [45:23], and in the second case, [46:24].

3. Adders for Comparison

3.1. Carry Look Ahead Adder (CLA)

This is just another kind of adder that contains carry propagation that, depending on the input signal, can calculate the carry in advance. This adder can perform faster addition than ripple carry adder, and it can also reduce the time delay [6].

3.2. Carry Skip Adder (CSA/CBA)

This adder is also known as carry bypass adder. It improves the ripple carry adder by reducing the delay. In this method for the propagation of carry, skip logic is used. The basic logic to propagate carry is that bit position remains unchanged for different values of A1, B1 [7].

3.3. Carry Increment Adder (CIA)

Incremental circuit and ripple carry adders (RCA) are used in the layout of carry increment adder (CIA). Half adders (HA) are used in making the design of incremental circuit of CIA. Firstly, the total number of bits is split up into groups of 4 bits, and afterwards, addition is accomplished by respective RCA [8].

4. Results

For simulation purposes, data flow and gate level modeling is selected in the Xilinx, and the design is a composite, using Xilinx ISIM tool, Family Spartan6, device XC6SLX45, and package CSG324. Two 32-bit numbers were multiplied using FPM, and the desired result was obtained.

4.1. Comparison with the Literature

The proposed technique using different adders was compared with different research papers, in which different adders and multipliers are used as shown in

Table 2. Comparison with literature.

Description	Proposed	[9]	[10]
Year	2021	2020	2020
FPGA	Spartan 6	Cadence EDA Tool	Altera Cyclone II
Multiplication Algorithm	Carry Save Array Multiplier	Vedic multiplier	Array Multiplier
Adder Algorithm	CIA, CSA, CLA, RCA	Kogge stone	Modified CLA

. The given literature is compared with time delay, number of LUTs, and number of occupied slices of below-mentioned techniques.

4.2. Device Utilization Summary

Carry select adder (CSA) and carry increment adder (CIA) use minimum time delay, 81.716 ns, to perform the floating point multiplication. Moreover, CIA occupies minimum number of slices, and CSA uses minimum number of slice LUTs as shown in

Table 3. Device utilization summary.

Description	Ripple Carry Adder- (Used/Available)	Carry Skip Adder (Used/Available)	Carry Select Adder (Used/Available)	Carry Look Ahead Adder (Used/Available)	Carry Increment (Used/Available)
Number of Slice LUTs	821/27,288	821/27,288	822/27,288	823/27,288	823/27,288
Occupied Slices	341/6822	352/6822	353/6822	347/6822	325/6822
Bonded IOBs	144/218	144/218	144/218	144/218	144/218
Average Fan-out	4.58	4.58	4.58	4.57	4.57
Total Delay	82.292 ns	81.783 ns	81.716 ns	82.138 ns	81.716 ns

.

5. Conclusions and Future Work

The major focus of this paper is to perform a 32-bit floating point multiplier that supports IEEE 754 format; the multiplier performs significands multiplication, thus normalizing the mantissa to obtain a 32-bit accurate output. The design may be implemented on intel’s Stratix10NX, Heterogeneous FPGA in the future to obtain fastest multiplication for higher bit numbers [11].