High Output Third-Order Intercept Point Low-Noise Amplifier Design Based on 0.13 μm CMOS Process for High-Precision Sensors ^†

This paper proposes a highly linear low-noise amplifier (LNA) using a cascode configuration. In the proposed topology, the linearity of the circuit is enhanced through the application of derivative superposition technology. The technology combines an auxiliary transistor operating in the moderate inversion region with a main transistor operating in the strong inversion region, and two degenerative inductors are connected in series at the source nodes of both transistors. The primary objective of this design is to mitigate the negative impacts of second-order and third-order nonlinearities on the third-order input intercept point (IIP3) through their interactions, thereby enhancing the linear performance of the circuit. An on-chip active bias circuit is designed to effectively address fluctuations in the IIP3 during process and temperature variations by stabilizing the transconductance of the common-source transistor, enabling the LNA to operate reliably in complex environments. During post-layout simulation in DongBu High-Tech’s 0.13 μm CMOS process, the circuit’s output third-order intercept point (OIP3) exhibits minimal fluctuations across different process corners and temperature variations. At the typical nmos and typical pmos (TT) process corner and a temperature of 30 °C, it achieves an OIP3 of 33.9 dBm with a power consumption of 42 mW sourced from a 2.8 V power supply. Furthermore, it realizes a relatively flat gain of 16 dB, a noise figure (NF) of 0.91 dB, input return loss less than −8 dB, and output return loss less than −10 dB.