High-Accuracy Bandgap Reference of <20 ppm/°C: A Review

Abstract

This review discusses the principle of typical bandgap reference circuits and analyzes their sources of errors. In order to provide readers with a clear perspective, we categorize the error sources into four types: (a) amplifier offset; (b) high-order nonlinearity of $V_{BE}$; (c) current mirror mismatch; and (d) other error sources. For these error sources, the most commonly used methods to reduce or minimize them to achieve high accuracy are summarized. Furthermore, this review explores sub-1V bandgap reference design techniques, addressing the increasing demand for low-power and low-voltage applications. Finally, we provide some suggestions for a future high-accuracy reference design.

1. Introduction

The bandgap reference (BGR) is a critical component used in analog and mixed-signal circuits, such as A/D data converters, phase-locked loops, DRAMs, and supply voltage regulators [1,2,3,4,5,6,7,8,9,10,11]. It can generate a stable reference voltage or current for maintaining the performance of circuits across varying operating conditions because of its temperature independence. The accuracy of the bandgap reference limits the accuracy of the circuits mentioned above. Therefore, a high-accuracy bandgap reference is necessary.

The principle of a bandgap reference is summing the proportional-to-absolute temperature (PTAT) signal and a complementary-to-absolute temperature (CTAT) signal in a certain proportion to obtain a temperature-independent voltage or current. However, the output voltage or current of the bandgap reference is not strictly temperature-independent. Quite a few factors contribute to the temperature drift of the output such as the process variation [1,12]; the nonlinearity of $V_{BE}$ [1,4,6,12], which is the base-emitter voltage of BJTs and used as the CTAT term; the variation in the common emitter current gain ($\beta$) of the BJT [12,13,14]; and the offset and noise of the error amplifier [1,12,13,14,15].

In this paper, we summarize the factors that influence the accuracy of the bandgap reference as well as the corresponding solutions proposed by former researchers. The reminder of the paper is organized as follows. The principle of the bandgap reference is introduced in Section 2. The sources of errors are discussed in Section 3, and the techniques to reduce or minimize them are presented in Section 4. The sub-1V references are presented in Section 5. Finally, the conclusion is drawn in Section 6.

2. Principle of Bandgap Reference

The main idea of a bandgap reference is to sum a PTAT signal and a CTAT signal in a certain proportion to reduce the temperature coefficient (TC) of the reference voltage, as shown in Figure 1. BJT-based bandgap references are the most widely used as they are insensitive to PVT variations [3,16,17]. The base-emitter voltage ($V_{BE}$) of a BJT has a negative TC, while the difference in $V_{BE}(\mathsf{\Delta }{V}_{BE}={\displaystyle \frac{kT}{q}}lnN)$ between two BJTs biased at different current densities has a positive TC. We could obtain a theoretically zero-TC reference voltage by designing a circuit which combines $V_{BE}$ and $\mathsf{\Delta }{V}_{BE}$ in a proper proportion. Also, there has been a lot of research on $V_{TH}$-based CMOS voltage references for low supply voltage and low power consumption. However, $V_{TH}$-based references always suffer from poor accuracy, as $V_{TH}$ is sensitive to process variations [16,17,18,19]. Therefore, $V_{TH}$-based references are not suitable for high-accuracy applications.

BJT-based bandgap references developed to date can be divided into two categories, i.e., voltage-mode BGRs, proposed by Kuijk [20]; and current-mode BGRs, proposed by Banba [9]. The main difference between them is that the PTAT signal and the CTAT signal are summed in either the voltage mode or the current mode, as shown in Figure 2a,b. A voltage-mode BGR has a reference voltage of about 1.25 V [8], and it usually works with a relatively high supply voltage. A current-mode BGR allows for operation under a low supply voltage, thus possibly resulting in less power consumption. Since its reference voltage is not limited to around 1.25 V, it can be used in sub-1V designs. In addition, voltage-mode BGRs have only two operating points, while current-mode BGRs have more operating points due to their symmetry. Therefore, the start-up circuit of a voltage-mode BGR is easier than for a current-mode BGR [5,8]. Some researchers also proposed a mixed-mode BGR to obtain a sub-1V voltage reference as well as to decrease the number of operating points [8].

The output voltage $V_{ref}$ in Figure 2a can be expressed as

$$V_{ref}=V_{EB1}+(V_{T}lnn)(1+{\displaystyle \frac{R_2}{R_3}})$$

(1)

where $V_T$ is the thermal voltage.

Apart from that, the output voltage $V_{ref}$ in Figure 2b can be expressed as

$$V_{ref}={\displaystyle \frac{R_4}{R_1}}(V_{EB1}+{\displaystyle \frac{R_1}{R_3}}{V}_{T}lnn)$$

(2)

3. Sources of Errors

There are many factors that affect the output accuracy of BGRs. Among them, the most significant factors are the operational amplifier offset, nonlinearity of $V_{BE}$, and current mirror mismatch in most cases.

3.1. Amplifier Offset

An amplifier is usually indispensable in the design of a BGR. We use the “virtual short” characteristic of the input terminals of the operational amplifier (opamp) to force the voltages between two nodes to be equal. However, the opamp has input offset [1,4,5,6,8,12,13,14,15,17,21], that is, the input voltage difference is unexpectedly not zero, which contributes to the output of the BGR. When the offset of the amplifier is considered, the output voltage in Figure 2a can be expressed as

$$V_{ref}=V_{EB1}+(1+{\displaystyle \frac{R_2}{R_3}})\mathsf{\Delta }{V}_{EB}+V_{OS}(1+{\displaystyle \frac{R_2}{R_3}})$$

(3)

and the output voltage in Figure 2b can be expressed as

$$V_{ref}={\displaystyle \frac{R_4}{R_1}}{V}_{EB1}+{\displaystyle \frac{R_4}{R_3}}\mathsf{\Delta }{V}_{EB}-({\displaystyle \frac{1}{R_3}}+{\displaystyle \frac{1}{R_1}})R_4{V}_{OS}$$

(4)

From Equations (3) and (4), we can see that the offset is amplified by the closed-loop gain times towards the reference voltage output [8,12,16,21]. Therefore, it is desirable to have a small amplifier offset in a high-accuracy BGR.

3.2. High-Order Nonlinearity of $V_{BE}$

The I-V characteristic of a diode-connected BJT can be expressed as [6,22,23]

$$I_C\left(T\right)=I_S\left(T\right)exp\left({\displaystyle \frac{q{V}_{BE}}{kT}}\right)=A{J}_{SX}{T}^{\eta }exp\left({\displaystyle \frac{q(V_{BE}-V_G\left(T\right))}{kT}}\right)$$

(5)

where A is the emitter area, $J_{SX}$ and $\eta$ are both process-dependent constants, T is the absolute temperature, and $V_G\left(T\right)$ is the bandgap voltage at T and can be modeled as [6,22,23]

$$V_G\left(T\right)=V_{G0}-{\displaystyle \frac{\alpha T^2}{\beta +T}}$$

(6)

where $V_{G0}$ is the bandgap voltage at 0 K, and $\alpha$ and $\beta$ are temperature-independent parameters. Equation (5) can be equivalently rewritten in logarithmic form as follows [22,24]:

$$V_{BE}=V_G\left(T\right)-[V_G\left(T_r\right)-V_{BE}\left(T_r\right)]{\displaystyle \frac{T}{T_r}}-\eta {\displaystyle \frac{kT}{q}}+{\displaystyle \frac{kT}{q}}\left[{\displaystyle \frac{I_C\left(T\right)}{I_C\left(T_r\right)}}\right]$$

(7)

Usually, we use a linear approximation to estimate $V_G\left(T\right)$:

$$V_G\left(T\right)=V_{G0}\left(T_r\right)+aT$$

(8)

where $V_{G0}\left(T_r\right)$ is an extrapolated bandgap voltage at 0 K, and a is a constant.

Combining Equations (7) and (8), if $I_C\left(T\right)$ is proportional to $T^{\xi }$, the base-emitter voltage $V_{BE}$ can be expressed as [1,4,6,12,13,22,24]

$$V_{BE}\left(T\right)=V_{G0}\left(T_r\right)-[V_{G0}\left(T_r\right)-V_{BE}\left(T_r\right)]{\displaystyle \frac{T}{T_r}}-(\eta -\xi )V_{T}ln\left({\displaystyle \frac{T}{T_r}}\right)$$

(9)

where $V_{BE}\left(T_r\right)$ is the base-emitter voltage at the reference temperature, and $\xi$ is the order of temperature dependency of the collector current. In this equation, $[V_{G0}\left(T_r\right)-V_{BE}\left(T_r\right)]{\displaystyle \frac{T}{T_r}}$ is the first-order temperature-dependent term, which can be compensated by a PTAT source, and $(\eta -\xi )V_{T}ln({\displaystyle \frac{T}{T_r}})$ is the high-order nonlinearity, which contributes to the systematic output variation and thus must be canceled or at least reduced in order to obtain a high-accuracy reference [25]. If we express $V_{BE}$ in the form of the tangent at the temperature $T_r$ plus a nonlinear term, then $V_{BE}$ can be expressed as

$$V_{BE}\left(T\right)=V_{BE0}-\lambda T+c\left(T\right)$$

(10)

where $\lambda$ is the slope of the tangent at the temperature $T_r$, and $c\left(T\right)$ is a nonlinear term that can be expressed as

$$c\left(T\right)={\displaystyle \frac{k}{q}}(\eta -\xi )[T-T_r-Tln\left({\displaystyle \frac{T}{T_r}}\right)]$$

(11)

Figure 3a shows a $V_{BE}$ and its tangent at $T_r$ [26]; and Figure 3b shows the $c\left(T\right)$ at a reference temperature $T_r=25 °$C and a temperature range $-40 °$C to $125 °$C [26]. It can be seen that the larger $\xi$ is, the smaller $c\left(T\right)$ will be. Due to this reason, it is desirable to have a larger $\xi$. Nevertheless, this means that we need to generate a current that changes with temperature with a higher-order relationship. And this is usually not easy to realize. Therefore, a more practical way is to use a PTAT current to bias the BJT ($\xi =1$).

Although the above discussion is useful, Equation (8) may not be accurate enough in some cases. For example, in the design of some ultra-high-accuracy ${\mathrm{sub-ppm/}}^{\circ }$C BGRs, the $V_G\left(T\right)$ is expanded by two basis functions, T and $TlnT$, instead of Equation (8). This method of expansion is more accurate and is called the natural basis expansion [6,22,23]. In this circumstance, $V_G\left(T\right)$ can be approximated in the following way [22]:

$$V_G\left(T\right)=V_{G0}\left(T_r\right)+a{\displaystyle \frac{T}{T_r}}+bTln\left({\displaystyle \frac{T}{T_r}}\right)$$

(12)

where a and b are temperature-independent coefficients.

For easy understanding, the fitting curves of Equations (8) and (12) are shown in Figure 4a, and the fitting error is shown in Figure 4b [22].

It is clear that Equation (12) has less error in the temperature range of 233 K to 400 K compared to Equation (8). Based on this point, Equation (9) can be changed to be more accurate as follows [6,22,23]:

$$V_{BE}\left(T\right)=V_{G0}\left(T_r\right)-[V_{G0}\left(T_r\right)-V_{BE}\left(T_r\right)]{\displaystyle \frac{T}{T_r}}-(\eta -\xi -b)V_{T}ln\left({\displaystyle \frac{T}{T_r}}\right)$$

(13)

3.3. Current Mirror Mismatch

The mismatch of CMOS current mirrors is mainly caused by variations in the threshold voltage $V_{TH}$ and current gain $\beta$ ($=\mu C_{OX}{\displaystyle \frac{W}{L}}$), both of which are influenced by the temperature and process [3]. Specifically, the current mirror mismatch can be expressed as follows [3,27]:

$$\sigma \left({\displaystyle \frac{\mathsf{\Delta }{I}_{DS}}{I_{DS}}}\right)={\displaystyle \frac{g_m{A}_{V_{TH}}}{I_{DS}\sqrt{W·L}}}+{\displaystyle \frac{A_{\beta }}{\sqrt{W·L}}}$$

(14)

where $A_{V_{TH}}$ is the mismatch coefficient of the threshold voltage; $A_{\beta }$ is the mismatch coefficient of the current gain $\beta$; W and L are the channel width and length of transistor, respectively; and ${\displaystyle \frac{g_m}{I_{DS}}}$ is the transistor current efficiency in the strong inversion region. Because $g_m=\beta (V_{GS}-V_{TH})$ in the strong inversion region, the current mirror mismatch can be re-written as [3]

$$\sigma \left({\displaystyle \frac{\mathsf{\Delta }{I}_{DS}}{I_{DS}}}\right)={\displaystyle \frac{A_{V_{TH}}\sqrt{\mu ·C_{OX}}}{\sqrt{I_{DS}}}}+{\displaystyle \frac{A_{\beta }}{\sqrt{W·L}}}$$

(15)

It can be seen in Equation (15) that to reduce the current mirror mismatch, we can increase the transistor size or increase the drain current. Nevertheless, an increased size means a larger chip area, and an increased drain current means a larger power consumption and a higher supply voltage. Therefore, there is a trade-off in the circuit design, since it is desirable to have a smaller area, a lower power consumption, and a lower supply voltage. On the other hand, if the drain current is so small that the transistor enters the sub-threshold region, then the current mirror mismatch will increase significantly. This is because there is an exponential relationship between the drain current and the gate-source voltage at this moment, and any small changes in the threshold voltage $V_{TH}$ can be exponentially amplified, which leads to significant changes in the current. This should be avoided in a high-accuracy design.

Usually, a current mirror mismatch is undesirable. For example, it can result in variations in the current ratio, leading to a non-PTAT error in the generated PTAT current as well as the final reference voltage [12].

3.4. Other Error Sources

3.4.1. Variation in Saturation Current

The base-emitter voltage $V_{BE}$ of a BJT is closely related to its saturation current $I_S$ and its collector current $I_C$. Due to this reason, if $I_S$ deviates from its nominal value under process variations, then the $V_{BE}$ can be influenced as well. The following equation shows this phenomenon [12]:

$$V_{BE}=V_{T}ln{\displaystyle \frac{I_C}{I_S+\mathsf{\Delta }{I}_S}}\approx V_{BE}{|}_{\mathsf{\Delta }{I}_S=0}-V_T{\displaystyle \frac{\mathsf{\Delta }{I}_S}{I_S}}$$

(16)

It can be assumed that $\mathsf{\Delta }{I}_S/I_S$ is process-dependent but temperature-independent. And therefore, the saturation current spread results in a PTAT error in $V_{BE}$, which can be reduced by a PTAT trim [12].

3.4.2. Resistor Mismatch

The mismatch of $R_1$ and $R_2$ in Figure 2a can influence the $V_{BE}$ by changing the $I_C$. If we define the mismatch as a fractional deviation ${\delta }_R$, then the $V_{BE}$ can be written as [12]

$$V_{BE}=V_{T}ln{\displaystyle \frac{I_C/(1+{\delta }_R)}{I_S}}\approx V_{BE}{|}_{{\delta }_R=0}-{\delta }_R{V}_T$$

(17)

As can be seen, since ${\delta }_R$ is mainly temperature-independent, it only results in a PTAT error in $V_{BE}$ as well, which can also be reduced by a PTAT trim [12].

3.4.3. Finite Current Gain $\beta$

The limited BJT current gain $\beta$ also affects the accuracy of the BGR. Especially, $\beta$ is usually small in standard CMOS technology [28] and it can easily vary with temperature and process. Under this circumstance, the $V_{BE}$ can be expressed in the following way [12]:

$$V_{BE}=V_{T}ln\left({\displaystyle \frac{I_E}{I_S}}·{\displaystyle \frac{\beta +\mathsf{\Delta }\beta }{1+\beta +\mathsf{\Delta }\beta }}\right)\approx V_{BE}{|}_{\mathsf{\Delta }\beta =0}+V_T·{\displaystyle \frac{1}{1+\beta }}·{\displaystyle \frac{\mathsf{\Delta }\beta }{\beta }}$$

(18)

where $I_E$ is the emitter current of the BJT. It can be seen in the above equation that the $\beta$ variation results in a non-PTAT error which cannot be canceled by a PTAT trim. This non-PTAT error is also one of the factors that limits the accuracy of a single-trim BGR.

3.4.4. Parasitic Base Resistance

The parasitic base resistance also affects the output of a BGR. If both the parasitic base resistance and $\beta$ are taken into account, then the $V_{BE}$ can be rewritten as follows [14]:

$$\begin{array}{c}\hfill V_{BE}=V_{T}ln{\displaystyle \frac{I_E}{I_S}}+V_{T}ln{\displaystyle \frac{\beta }{\beta +1}}+{\displaystyle \frac{I_E{r}_b}{\beta }}\end{array}$$

(19)

where $r_b$ is the parasitic base resistor of the BJT. Similar to $\beta$ variations, this error is also non-PTAT and it is also a factor that limits the accuracy of a single-trim BGR.

4. Methods for Eliminating the Error Sources

In order to improve the accuracy of the BGR, the following summarizes the commonly used solutions to cancel out the error sources.

4.1. Techniques to Reduce the Amplifier Offset

4.1.1. Self-Biasing Technique

The self-biasing technique [5,8,13,29,30,31,32] is a circuit design method that allows key components in a circuit, such as operational amplifiers or other active components, to automatically adjust their operating points without an extra biasing circuit. This technique is sometimes suitable for analog circuits that require high accuracy and robustness, such as bandgap reference circuits, as they can maintain a consistent performance under different operating conditions and under PVT variations.

In bandgap reference circuits, the self-biasing technique can reduce system errors caused by device mismatches through ensuring current density matching within the circuit. Specifically, the self-biasing technique can reduce the system offset of operational amplifiers.

In operational amplifiers, the input stage is typically composed of a pair of differential transistors that require precise matching in order to ensure the circuit performance, such as a low input-referred offset and a good common-mode rejection ratio (CMRR). Nevertheless, in an actual manufacturing process, even transistors on the same chip may have slight differences in their physical parameters, which leads to mismatched current density of input-stage transistors, and thus affects the performance of the circuit. In the design of operational amplifiers, for example, in Figure 5, the self-biasing technique [5] helps control the biasing point of the amplifier by using the output of the circuit to guarantee that the circuit operates in the optimal linear region. This typically involves using a negative feedback loop that detects the current at the output or detects the internal nodes of the amplifier, and thus adjusts the bias circuit to maintain the desired current density or operating point [5,33].

4.1.2. Chopping Technique

The chopping technique is often used to reduce the random offset or low-frequency noise of error opamp [5,12,34,35,36,37]. The principle of the chopping technique is to perform a square-wave modulation on the input signal before inputting it into the operational amplifier, and then to perform a square-wave modulation on the output of the operational amplifier. During the entire process, the input signal is modulated twice, but the offset signal or low-frequency noise is modulated only once. This helps demodulate the input signal and modulate the offset and low-frequency noise to a high frequency [34,38]. Finally, after filtering, an amplified input signal can be obtained, which realizes the elimination of offset and low-frequency noise. The principle of the chopping technique [12] is shown in Figure 6, where $f_{CH}$ is the clock frequency, A is the gain of the opamp, and LPF is a low-pass filter.

4.1.3. Auto-Zeroing Technique

The basic principle of the auto-zeroing technique [1,14,35,37,38,39] is to sample the unwanted offset voltage and subtract it from the input signal or output signal [38]. A typical continuous-output auto-zeroing amplifier [1,38] is shown in Figure 7. It includes two amplifiers, one of which is the main amplifier and the other is the nulling amplifier, also known as the auxiliary amplifier or zeroing amplifier. The auto-zeroing process consists of at least two successive phases. In the first phase, $\varphi 0$, the nulling amplifier is disconnected from the main amplifier and its input ports are shorted to perform its own auto-zeroing operation. As a result, its auto-zeroing correction signal $V_n$ is generated and held on the capacitor $C_n$ for its nulling amplifier correction. In the second phase, $\varphi 1$, the nulling amplifier is connected in parallel with the main amplifier to obtain its input offset and to generate another correction signal $V_m$. This correction signal is held on the capacitor $C_m$ for the main amplifier correction [39]. Finally, an output without offset is realized.

Overall, the core idea of the auto-zeroing technique is to store the offset voltage on a capacitor and use it to eliminate the offset voltage later. Therefore, it is also known as the offset storage technique.

As mentioned above, the auto-zeroing technique is useful, but it needs a nulling amplifier, which consumes energy. Especially, if there are many main amplifiers, then each main amplifier will need a nulling amplifier, wasting a lot of energy. To solve this issue, ref. [1] proposed a shared offset cancellation method to share the same nulling amplifier among different main amplifiers, so that energy, as well as die area, could be saved.

4.1.4. Switched-Capacitor Bandgap Reference

Another idea to cancel out the amplifier offset is to use a switched-capacitor bandgap reference. For example, if the amplifier offset is difficult to eliminate for some reason, then a bandgap reference without an amplifier can be used. In this situation, a switched-capacitor bandgap reference (SCBGR) [31,35,40,41] is a possible solution. Usually, SCBGRs are based on sampling. This means that, in the first phase, we can first sample the voltages through capacitors, and then, in the second phase, the operation of summation or subtraction can be performed on the sampled voltages by using the charge redistribution of capacitors. Since, in this operation, it is not necessary to use an amplifier, the amplifier offset is no longer a problem either. Here, for easy understanding, this technique is illustrated with the circuit of [31], as shown in Figure 8.

This technique can be understood easily by looking at the expression of reference voltage. Usually, the reference voltage is expressed in the following way:

$$V_{ref}=V_{EB1}+\alpha (V_{BE1}-V_{EB2})$$

(20)

For easy understanding, this expression can be rewritten as follows:

$$V_{ref}=(1+\alpha )(V_{EB1}-{\displaystyle \frac{\alpha }{1+\alpha }}{V}_{EB2})$$

(21)

As can be seen, the reference voltage is a scaled subtraction of two base-emitter voltages of BJTs with different current densities [31]. To realize this scaled subtraction, Figure 8 shows the switched-capacitor bandgap reference in [31]. It is controlled by clock signals. In the first phase, ${\varphi }_0$, the voltage $V_{EB1}-V_{EB2}$ is sampled onto the capacitor $C_1$, while the voltage $V_{EB1}$ is sampled onto the capacitor $C_2$. After that, in the second phase, ${\varphi }_1$, the capacitors $C_1$, $C_2$, and $C_L$ are connected together, so that there is a charge redistribution among these capacitors. As a result, a $V_{ref}$ is generated that can be expressed in the following way [31]:

$$V_{ref}=V_{EB1}-{\displaystyle \frac{C_1}{C_1+C_2}}{V}_{EB2}$$

(22)

As can be seen, this realizes the desired scaled subtraction of two base-emitter voltages. And if the ratio between $C_1$ and $C_2$ is designed as $\alpha :1$, then it can be demonstrated that the generated $V_{ref}$ is a temperature-independent reference voltage.

Here, the problem is that, in Figure 8, there is also an amplifier in the bandgap reference circuit. This seems to contradict the above statement that this technique does not need an amplifier. Nevertheless, this is not a real problem. This is because this amplifier is only used for generating a biasing current. If it is necessary, we can also use other methods without an amplifier to generate the biasing current. From this perspective, it is true that the technique in Figure 8 does not need an amplifier.

Apart from that, since the amplifier is only used for generating the biasing current, its amplifier offset has almost no influence on the accuracy of the reference voltage. And therefore, we do not need to care about the amplifier offset here. For easy understanding, we calculate the influence of the amplifier offset on the generated reference voltage $V_{ref}$ as follows [31]:

$$V_{OS,ref}={\displaystyle \frac{V_{OS}}{R_2}}{\displaystyle \frac{1}{g_{mQ1}}}{\displaystyle \frac{C_2}{C_1+C_2}}$$

(23)

where $g_{mQ1}$ is the transconductance of the BJT $Q_1$, and $V_{OS}$ is the amplifier offset mentioned above. As can be seen, the amplifier offset is greatly attenuated, by $g_{mQ1}{R}_2$ times, when generating the reference voltage $V_{ref}$. This demonstrates that the amplifier offset indeed does not influence the reference voltage accuracy in the structure of Figure 8.

Overall, the amplifier offset can be significantly reduced by using the auto-zeroing technique, the chopping technique, and the switched-capacitor bandgap reference. Their disadvantages are that all of them are clock-controlled circuits. This kind of circuit has the issue of charge injection and clock feedthrough, which should be treated carefully in high-accuracy bandgap references. Apart from that, they also require extra clock generators to generate the clock signals. This also wastes some energy and chip area.

4.1.5. Feedback Coefficient Enhancement Technique

In the previous sections, we have introduced some techniques to eliminate the amplifier offset error. Here, as an alternative, we also introduce a technique to reduce, but not eliminate, the amplifier offset error. It is called the feedback coefficient enhancement technique; it uses a better feedback coefficient in the feedback loop to help reduce the amplifier offset error.

For example, in order to calculate the feedback coefficient, Figure 9 shows the equivalent small-signal model of both a voltage-mode BGR and current-mode BGR. Since both of them have a feedback loop, their feedback coefficients can be calculated. Here, $V_{OS}$ and $V_n$ represent the input-referred offset and noise of the amplifier, respectively. And the feedback network in the yellow rectangle can be simplified as shown in Figure 10.

In Figure 10, F is the feedback coefficient. And its value can be calculated in the following way:

$$F={\displaystyle \frac{(\mathsf{\Delta }{V}_X-\mathsf{\Delta }{V}_Y)}{\mathsf{\Delta }{V}_O}}$$

(24)

By using this concept of feedback coefficient F, the amplifier input-referred offset that is transferred to the reference voltage output can be calculated as follows:

$$V_{OS,O}={\displaystyle \frac{V_{OS,EA}}{F}}$$

(25)

Take Figure 9a as an example, its feedback coefficient F can be expressed as

$$F={\displaystyle \frac{\mathsf{\Delta }{V}_X-\mathsf{\Delta }{V}_Y}{\mathsf{\Delta }{V}_{ref}}}$$

(26)

From its equivalent small-signal circuit, it is easy to know that the voltage change at node X is as follows:

$$\mathsf{\Delta }{V}_X={\displaystyle \frac{1/g_{mQ2}}{R_1+1/g_{mQ2}}}\mathsf{\Delta }{V}_{ref}$$

(27)

And the voltage change at node Y is as follows:

$$\mathsf{\Delta }{V}_Y={\displaystyle \frac{R_3+1/g_{mQ1}}{R_2+R_3+1/g_{mQ1}}}\mathsf{\Delta }{V}_{ref}$$

(28)

And therefore, with Equations (26)–(28), the feedback coefficient F can be calculated as follows:

$$F={\displaystyle \frac{\mathsf{\Delta }{V}_X-\mathsf{\Delta }{V}_Y}{\mathsf{\Delta }{V}_{ref}}}=-{\displaystyle \frac{g_{mQ1}{g}_{mQ2}{R}_1{R}_3}{(1+g_{mQ2R_1})(1+g_{mQ1}{R}_2+g_{mQ1}{R}_3)}}\approx -{\displaystyle \frac{R_3}{R_2+R_3}}$$

(29)

According to Equation (25), we can calculate the reference voltage change $V_{OS,ref}$ that is caused by the amplifier input-referred offset $V_{OS,EA}$:

$$V_{OS,ref}={\displaystyle \frac{V_{OS,EA}}{F}}\approx -V_{OS,EA}(1+{\displaystyle \frac{R_2}{R_3}})$$

(30)

As can be seen in Equation (30), the amplifier input-referred offset is amplified by a factor of ($1+R_2/R_3$) towards the reference voltage. This satisfies the previously mentioned Equation (3). In general, this factor of ($1+R_2/R_3$) is approximately equal to 10 [21]. And as long as this factor is greatly reduced, the error in the reference voltage will also be greatly reduced as well.

Similarly, for the current-mode BGR in Figure 9b, we can also calculate the reference voltage change $V_{OS,ref}$ that is caused by the amplifier input-referred offset $V_{OS,EA}$ as follows [42]:

$$V_{OS,ref}=-{\displaystyle \frac{R_4}{R_3}}{V}_{OS,EA}$$

(31)

As can be seen in Equation (31), the amplifier input-referred offset is amplified by a factor of $R_4/R_3$ towards the reference voltage. This approximately satisfies the previously mentioned Equation (4). Typically, this factor of $R_4/R_3$ is also a large value. And it is desirable if this factor can be greatly reduced as much as possible.

From the above analysis, we can see that increasing the feedback coefficient F is helpful for reducing the impact of amplifier offset. This is the basic idea of the feedback coefficient enhancement technique, which is also called the offset suppression technique [16,21,42,43]. Based on this technique, refs. [21,43] proposed improved versions of voltage-mode and current-mode BGRs, which are shown in Figure 11a and Figure 11b, respectively.

Here, still using the improved voltage-mode BGR in Figure 11a as an example, we can calculate its feedback coefficient F in a similar way. The only difference is that an intermediate node Z is added here for easy calculation. As a result, we have

$$F={\displaystyle \frac{\mathsf{\Delta }{V}_X-\mathsf{\Delta }{V}_Y}{\mathsf{\Delta }{V}_{ref}}}={\displaystyle \frac{\mathsf{\Delta }{V}_X-\mathsf{\Delta }{V}_Y}{\mathsf{\Delta }{V}_Z}}{\displaystyle \frac{\mathsf{\Delta }{V}_Z}{\mathsf{\Delta }{V}_{ref}}}$$

(32)

Based on this way of calculation, we first calculate the equivalent resistor looking from node Z, which is given by [21]

$$R_{EQ}={\displaystyle \frac{R_3}{(2-lnN)lnN}}$$

(33)

Then, we can obtain the relation between $\mathsf{\Delta }{V}_{ref}$ and $\mathsf{\Delta }{V}_Z$ as follows:

$$\mathsf{\Delta }{V}_Z={\displaystyle \frac{R_{EQ}}{R_{EQ}+R_1}}\mathsf{\Delta }{V}_{ref}$$

(34)

In addition, $\mathsf{\Delta }{V}_X$ and $\mathsf{\Delta }{V}_Y$ can be calculated easily with the help of $\mathsf{\Delta }{V}_Z$ in the following way:

$$\begin{array}{cc}\hfill \mathsf{\Delta }{V}_X=& \mathsf{\Delta }{V}_Z-{\displaystyle \frac{\mathsf{\Delta }{V}_Z}{1/g_{mQ2}}}{R}_3\hfill \end{array}$$

(35)

$$\begin{array}{cc}\hfill \mathsf{\Delta }{V}_Y=& \mathsf{\Delta }{V}_Z-\mathsf{\Delta }{V}_X{g}_{mQ1}{R}_2\hfill \end{array}$$

(36)

Finally, according to Equations (32)–(36), the feedback coefficient F can be calculated as follows [21]:

$$F=-{\displaystyle \frac{1}{[1+(2-lnN)·lnN·\frac{R_1}{R_2}]·{\left(\frac{1}{lnN}\right)}^2}}$$

(37)

As can be seen in the above equation, the feedback coefficient F becomes a large value. This helps to greatly reduce the error in the reference voltage that is caused by the amplifier offset. Specifically, N is chosen to be 6 in [21] as an example. This leads to an F of 1/1.02, which is much larger than the previous F of 1/10. This improvement is desirable in high-accuracy applications.

Similarly, we can also calculate the feedback coefficient F in the improved current-mode BGR in Figure 11b, as follows [43]:

$$F={\displaystyle \frac{g_{mp}{R}_{3}lnN}{lnN-2}}$$

(38)

where $g_{mp}$ is the transconductance of $M_1$. As can be seen, the feedback coefficient F is greatly increased, since $g_{mp}{R}_3$ is a large value. This is helpful for suppressing the amplifier offset effectively. As a result, the accuracy of BGR is greatly improved.

4.2. Curvature Compensation to Reduce $V_{BE}$ Nonlinearity

4.2.1. Piecewise Compensation Technique

In a typical BGR circuit, the output reference voltage usually has a convex curvature due to the nonlinear term in $V_{BE}$. The piecewise compensation technique [1,6,10,11,21,43,44] is usually used to reduce this nonlinearity by dividing the entire temperature range into several intervals and using different compensation currents in each interval.

The most commonly used compensation technique is piecewise linear compensation, which typically uses a CTAT current for compensation in the lower-temperature range and a PTAT current in the higher-temperature range, with no compensation applied in the intermediate temperature range. The principle of piecewise linear compensation is shown in Figure 12. As can be seen, it uses three-piece linear compensation. Similarly, ref. [21] even uses five-piece linear compensation.

Apart from the linear compensation current mentioned above, piecewise compensation can also be realized by using a variety of nonlinear currents in different temperature ranges [7,37,42,45]. For example, ref. [45] realized compensation with an exponential current in the low-temperature range and a logarithmic current in the high-temperature range. Ref. [42] used two exponential currents in the low- and high-temperature ranges, respectively, in order to form a bowl-shaped curvature compensation current, as shown in Figure 13. As can be seen, nonlinear compensation currents have a better compensation effect. And generally, the selection of the compensation current within different temperature ranges depends on the specific application.

In order to cater to different applications, ref. [7] designed an adjustable-temperature curvature compensation circuit that generates different compensation currents based on the curvature type of the reference voltage. This allows it to compensate for the reference voltage with an arbitrary curvature type.

Up to now, the above-mentioned piecewise compensations are limited in the number of temperature segments. To break this limitation, ref. [1] proposed an interesting idea of using multiple piecewise linear compensations, with each compensation current having a different threshold voltage. This approach of increasing the number of segments is called multi-section curvature compensation, which provides more flexibility during the design of compensation and over a wider temperature range. The principle of multi-section curvature compensation is illustrated in Figure 14.

Similarly, ref. [46] proposed a method called segmented curvature compensation. It also divides the reference voltage into many pieces as well. This makes it similar to the multi-section curvature compensation that is mentioned above. Nevertheless, they are actually very different. This difference can be observed in Figure 15. As can be seen, segmented curvature compensation has a different reference voltage after compensation. Its shape is very different. Specifically, its shape is like dividing the $V_{ref}$ into $2S+1$ segments. And if the total change in reference voltage before compensation is $V_{DF}$, then the total change in reference voltage after compensation can be calculated in the following way [46]:

$$V_{DF,SEG}={\displaystyle \frac{V_{DF}}{S+1}}$$

(39)

where S is the number of segments in the lower-temperature range $T_L$ or higher-temperature range $T_H$. And its temperature coefficient can be expressed in the following way [46]:

$$T{C}_{SEG}={\displaystyle \frac{V_{DF,SEG}}{V_{ref1}\times (T_{MAX}-T_{MIN})}}\times {10}^6$$

(40)

where $T_{MAX}$ is the maximum operating temperature and $T_{MIN}$ is the minimum operating temperature. From Equations (39) and (40), it can be found that, in an ideal situation, the greater the number of segments, the lower the temperature coefficient will be. However, there is a trade-off. This is because a large number of segments means a large number of comparators as well. This consumes much energy and area.

4.2.2. Second-Order Curvature Compensation

Another type of compensation is called second-order curvature compensation. This compensation can be understood easily by looking at the curvature in $V_{BE}$. If we perform a Taylor expansion on $V_{BE}$ in Equation (9), then we can obtain the following expression:

$$V_{BE}=a_0+a_{1}T+a_2{T}^2+a_3{T}^3+\dots$$

(41)

where $a_2$ ranges from $-3.05\times {10}^{-7}$ to $0 \mathrm{V}/{\mathrm{K}}^2$ when the temperature is in the range of −123 °C to 127 °C [4]. Due to this negative $a_2$, the $V_{BE}$ usually has a curvature-down characteristic. Apart from that, other terms in the above equation, such as the third-order term, fourth-order term, and so on, only have a negligible impact on the BGR accuracy. And the first-order term can also be canceled out by a PTAT voltage. Therefore, the most important thing here is the second-order term. To eliminate this term, second-order curvature compensation is usually used, which introduces a $PTA{T}^2$ component into the reference voltage.

There are several methods to generate the second-order compensation current or voltage in the BGR circuit. For example, refs. [47,48] use the temperature coefficient difference between the poly resistor and diffusion resistor to generate a ${PTAT}^2$ term for the second-order curvature compensation.

Similarly, ref. [14] generates a second-order term in $\mathsf{\Delta }{V}_{BE}$ by adding a PTAT current into the bias current of one BJT and subtracting a PTAT current from another BJT. As a result, its $\mathsf{\Delta }{V}_{BE}$ can be expressed in the following way [14]:

$$\begin{array}{cc}\hfill \mathsf{\Delta }{V}_{BE}& =V_{T}ln\left(N{\displaystyle \frac{I_0+I_T}{I_0-I_T}}\right)\hfill \\ \hfill & =V_{T}ln\left(N\right)+2V_T\left({\displaystyle \frac{I_T}{I_0}}\right)+{\displaystyle \frac{2}{3}}{V}_T{\left({\displaystyle \frac{I_T}{I_0}}\right)}^3+\dots \hfill \end{array}$$

(42)

where $I_T$ is a PTAT current, $I_0$ is a temperature-independent current, and N is the ratio between the two BJTs. As can be seen in the above equation, the second term is a desirable ${PTAT}^2$ term.

As another example, ref. [49] realizes the second-order compensation by combining an MOS-based compensation circuit and a BJT-based reference circuit with correct weights, and using their outputs with opposite curvatures for the second-order and partial third-order compensation. By using the parameter n in Equation (46) (to be discussed later) that is a function of temperature, it generates a positive second-order term in the expression of $\mathsf{\Delta }{V}_{GS}$ as follows [49]:

$$\begin{array}{c}\hfill \mathsf{\Delta }{V}_{GS}={\displaystyle \frac{kT}{q}}Elnw+{\displaystyle \frac{k{T}^2}{q}}Flnw+{\displaystyle \frac{k{T}^3}{q}}Glnw\end{array}$$

(43)

where E, F, and G are positive constants, w is equal to $(I_1/I_2)·{(W/L)}_1/{(W/L)}_2$, $I_1$ and $I_2$ are the currents flowing through two MOSFETs, and ${(W/L)}_1$ and ${(W/L)}_2$ are the width–length ratios of the two MOSFETs. As can be seen, this voltage difference $\mathsf{\Delta }{V}_{GS}$ includes a desirable second-order term, which can be used to perform the curvature compensation.

In sum, although second-order compensation cannot completely eliminate the curvature in the reference voltage, it cancels out the most significant term among the high-order terms. As a result, the BGR accuracy is greatly improved.

4.2.3. $TlnT$ Compensation

Another commonly used technique is $TlnT$ compensation. From Equation (9), it can be seen that the nonlinearity in $V_{BE}$ is totally caused by the $TlnT$ term. Therefore, as long as the $TlnT$ term is eliminated, we can completely remove the curvature in $V_{BE}$.

There are several methods to generate the $TlnT$ term for curvature compensation. The first method is called the $V_{G0}$ extraction technique [11,12,22,23,24,35,50,51], which is based on the fact that the $\mathsf{\Delta }{V}_{BE}$ of two BJTs biased at a ZTAT current and a PTAT current has exactly the same $TlnT$ term that we need in the curvature compensation. Specifically, according to Equation (9), if we have a BJT (Q3 as an example) with a ZTAT current and a BJT (Q2) with a PTAT current, then the $\mathsf{\Delta }{V}_{BE}$ between them can be calculated as follows:

$$\mathsf{\Delta }{V}_{BE3,2}\left(T\right)=[V_{BE3}\left(T_r\right)-V_{BE2}\left(T_r\right)]{\displaystyle \frac{T}{T_r}}-{\displaystyle \frac{kT}{q}}ln{\displaystyle \frac{T}{T_r}}$$

(44)

By carefully combining $V_{BE}$, $\mathsf{\Delta }{V}_{BE}$, and $\mathsf{\Delta }{V}_{BE3,2}$, we can extract $V_{G0}$ from $V_{BE}$ and use this extracted $V_{G0}$ as the reference voltage. For easy understanding, this combination can be expressed in the following way:

$$V_{ref}=V_{BE}+A_1·\mathsf{\Delta }{V}_{BE}+A_2·\mathsf{\Delta }{V}_{BE3,2}=V_{G0}$$

(45)

where $A_1$ and $A_2$ are the scaling factors, which can be determined by solving both ${\displaystyle \frac{\mathrm{d}{V}_{ref}}{\mathrm{d}T}}=0$ and ${\displaystyle \frac{\mathrm{d}{V}_{ref}}{\mathrm{d}(TlnT)}}=0$ simultaneously.

The second method also generates the $TlnT$ term for the curvature compensation. The only difference is that it uses the gate-source voltage of the MOSFET in the sub-threshold region to generate this $TlnT$ term [6,25,52,53]. Specifically, it is based on the drain current of the MOSFET in the sub-threshold region as follows [54]:

$$I_{DS}=\mu C_{OX}{V_T}^2\left({\displaystyle \frac{W}{L}}\right)(n-1)e^{({\displaystyle \frac{V_{GS}-V_{TH}}{n{V}_T}})}(1-e^{-{\displaystyle \frac{V_{DS}}{V_T}}})$$

(46)

where $C_{OX}$ is the gate oxide capacitance, n is the sub-threshold slope factor, $\mu$ is the mobility, $V_{GS}$ is the gate-source voltage, $V_{DS}$ is the drain-source voltage, and $V_{TH}$ is the threshold voltage. For $V_{DS}>4V_T$, the $V_{DS}$ term can be neglected, so that we can obtain the expression of $V_{GS}$ as follows [6]:

$$V_{GS}=n{V}_{T}ln{\displaystyle \frac{I_{DS}L}{\mu C_{OX}{V_T}^{2}W(n-1)}}+V_{TH}$$

(47)

Here, the relationship between the mobility $\mu$ and the temperature T is usually modeled in the following way [55]:

$$\mu ={\mu }_0{\left({\displaystyle \frac{T}{T_0}}\right)}^{{\beta }_{\mu }}$$

(48)

where ${\mu }_0$ is the mobility at temperature $T_0$, and ${\beta }_{\mu }$ is the mobility temperature exponent.

Apart from that, the threshold voltage $V_{TH}$ is usually modeled in the following way [55]:

$$V_{TH}\left(T\right)=V_{TH0}-{\alpha }_{V_{TH}}T$$

(49)

where $V_{TH0}$ is the threshold voltage at 0 K and ${\alpha }_{V_{TH}}$ is the temperature coefficient of $V_{TH}$.

Combining Equation (47), Equation (48), and Equation (49), the $V_{GS}$ can be expressed in the following way, if we set $I_{DS}$ to be equal to $GT$ (where G is a coefficient) [6]:

$$V_{GS}=V_{TH0}+\left(n{\displaystyle \frac{k}{q}}ln\left({\displaystyle \frac{q^{2}GL{T_0}^{{\beta }_{\mu }}}{{\mu }_0{C}_{OX}{k}^{2}W(n-1)}}\right)-{\alpha }_{V_{TH}}\right)T-n{\displaystyle \frac{k}{q}}(1+{\beta }_{\mu })TlnT$$

(50)

As can be seen in this equation, the last term is the desirable $TlnT$ term. By summing $V_{BE}$, $\mathsf{\Delta }{V}_{BE}$, and $V_{GS}$ in an appropriate proportion, we can finally obtain a reference voltage which no longer has the nonlinear term $TlnT$. For easy understanding, this summation is also expressed below:

$$V_{ref}=K_1{V}_{BE}+K_2\mathsf{\Delta }{V}_{BE}+K_3{V}_{GS}=K_1{V}_{G0}\left(T_r\right)+K_3{V}_{TH0}$$

(51)

Apart from the methods discussed above, there are also other methods. For example, ref. [56] realizes an approximate value of $TlnT$. Although not accurately equal to $TlnT$, it is approximately equal to $TlnT$. It generates an approximate value, because the accurate value of $TlnT$ is hard to generate, since complicated circuits are usually required. Due to this reason, a compensation term that is equal to $T{e}^{f\left(T\right)}$ is generated instead. Although it seems to be very different from $TlnT$, their values are very close to each other as long as the circuit is properly designed.

4.2.4. Indirect Curvature Compensation

Up to now, in all of the previously discussed compensation methods, the compensation signal is added directly onto the reference voltage or current. From this perspective, all of these methods are called direct curvature compensation. Different from this direct curvature compensation, ref. [40] proposed an indirect curvature compensation. This does not add the compensation signal directly onto the reference voltage or current. Instead, it performs the compensation by setting the biasing current of the BJT. Specifically, when a well-designed biasing current flows into the BJT, the curvature in the emitter-base voltage $V_{EB}$ can be canceled out. This realizes the compensation operation. For easy understanding, Figure 16 shows this conception of indirect curvature compensation. As can be seen in Figure 16, the $I_{NL}$ is the source-drain current of an MOS transistor operating in the sub-threshold region, which can be expressed as Equation (46).

Here, to understand indirect curvature compensation, we express the collector current of the BJT in the following way [40]:

$$I_C={\displaystyle \frac{\beta \left(T\right)}{\beta \left(T\right)+1}}{I}_E\left(T\right)={\displaystyle \frac{{\beta }_0}{{\beta }_0+1}}{\left({\displaystyle \frac{T}{T_r}}\right)}^{X_{TB}}{I}_{E0}{\left({\displaystyle \frac{T}{T_r}}\right)}^{X_{TE}}={\displaystyle \frac{{\beta }_0}{{\beta }_0+1}}{I}_{E0}{\left({\displaystyle \frac{T}{T_r}}\right)}^{X_{TB}+X_{TE}}$$

(52)

where ${\beta }_0$ is the current gain of the BJT at the reference temperature $T_r$, $I_{E0}$ is the emitter current at the reference temperature $T_r$, and $X_{TB}$ and $X_{TE}$ are the temperature exponents of $\beta$ and $I_E$, respectively. After that, by combining Equation (52) and Equation (11), the nonlinear term $c\left(T\right)$ in the emitter-base voltage $V_{EB}$ can be expressed in the following way [40]:

$$c\left(T\right)={\displaystyle \frac{k}{q}}(\eta -X_{TB}-X_{TE})[T-T_r-Tln\left({\displaystyle \frac{T}{T_r}}\right)]$$

(53)

Since the emitter current is $I_E\left(T\right)=I_{PTAT}+I_{NL}$, as shown in Figure 16, the temperature exponent $X_{TE}$ of the emitter current can be controlled by adjusting the ratio between $I_{PTAT}$ and $I_{NL}$. As a result, a desirable value of $X_{TE}=\eta -X_{TB}$ can be realized by designing $I_{PTAT}$ and $I_{NL}$ in a proper proportion. This eliminates the curvature $c\left(T\right)$ in the emitter-base voltage $V_{EB}$.

4.2.5. Other Compensation Techniques

Apart from the previously mentioned methods, there are also many other compensation techniques. For example, refs. [4,28] propose two compensation methods, which are shown in Figure 17. Here, the first method [28] is to use a BGR circuit with NPN transistors and a BGR circuit with PNP transistors to generate two reference currents that have the same type of curvature but different reference currents. And then, these reference currents are subtracted from each other to cancel out the curvature in them [28].

The second method [4] uses a special current mirror to generate a curvature for the curvature compensation. Specifically, it causes the original reference current to flow through the current mirror, so that an opposite curvature is generated in the output current. After that, it adds this output current back to the original reference current, so that the curvature in them can be canceled out [4].

Overall, any signal, that can adjust the curvature in the reference voltage may be used as a curvature compensation signal.

4.3. Techniques to Reduce the Current Mirror Mismatch

4.3.1. Automatic Current-Controlled Feedback Loop

Current mirror mismatch can significantly affect the BGR accuracy. To solve this issue, an automatic current-controlled feedback loop can be used to reduce the current mirror mismatch. As mentioned in Equations (14) and (15), in order to reduce the current mirror mismatch, one possible solution is to increase the current in the current mirror. Nevertheless, this method goes against our need for low power consumption and a low power supply voltage, since a large current also means a large base-emitter voltage of the BJT that is used in the BGR circuit. By contrast, in order to realize both low power consumption and a low power supply voltage, ref. [18] proposed an automatic current-controlled feedback loop which reduces the current mirror mismatch without increasing the power consumption or power supply voltage. Figure 18a shows a schematic diagram of it.

As can be seen in Figure 18a, the circuit ensures that the current flowing through the BJT is effectively limited to a small value for a low power supply voltage, and it ensures that the current in the current mirror is large enough for a good matching, and this does not require increasing the transistor size in the current mirror. Regardless of its effectiveness, this method also has a disadvantage. It is sensitive to the amplifier offset. Specifically, although the input-referred offset of amplifier OP2 in the feedback loop contributes little to the reference voltage, the reference voltage is quite sensitive to the amplifier OP1 offset. Therefore, to solve this issue, an improved version of the automatic current-controlled feedback loop is developed in [16], which makes the reference voltage insensitive to the amplifier OP1 offset. Figure 18b shows this improved version of the automatic current-controlled feedback loop.

4.3.2. Resistor Feedback Technique

Another way to reduce the current mirror mismatch is to use the resistor feedback technique in [21,42,43], as shown in Figure 19. This technique can effectively reduce the error and low-frequency noise in the current mirror. Its principle is easy to understand. The feedback resistor adjusts the current distribution in the current mirror, making the current more uniform and thus reducing the errors caused by inconsistent transistor parameters. This kind of feedback resistor is added at the source of the current mirror (see Figure 19). Let us take the low-frequency noise of transistors $M1$ and $M2$ as an example. If there are no feedback resistors $R_1$ and $R_2$, then the low-frequency noise $V_{n,M1,2}$ is amplified by the current mirror in the following way, when the noise is transferred to $R_3$:

$$V_{n,R_3}=g_{m2}{R}_3{V}_{n,M1,2}$$

(54)

where $V_{n,R_3}$ is the low-frequency noise at $R_3$ that is caused by $V_{n,M1,2}$. In addition, the transfer of the current mirror offset $V_{OS,M1,2}$ is similar to this low-frequency noise as well.

After the feedback resistors $R_1$ and $R_2$ are added into the circuit, the noise transferred to $R_3$ becomes the following:

$$V_{n,R_3}=g_{m2}{R}_3{V}_{n,M1,2}/(1+g_{m2}{R}_2)$$

(55)

From Equations (54) and (55), it can be clearly seen that the influence of low-frequency noise is significantly reduced thanks to the resistor feedback technique. Nevertheless, regardless of its effectiveness, its disadvantage is that it sacrifices the voltage margin.

4.3.3. Stacked Multiple Transistors

According to Equation (15), another possible way to reduce the current mirror mismatch is to increase the size (W and L) of the MOSFET. Nevertheless, in advanced technology nodes, the chemical mechanical polishing (CMP) process may affect the uniformity of the metal gate, especially for long-channel transistors. This may influence the performance of the transistor unexpectedly. Fortunately, this problem can be avoided by stacking multiple short-channel transistors together, as in [3,17]. This is because when the gate length of each small transistor is short enough, it is much easier to control the process variability and its defects, and thus the overall quality and performance of transistor can be improved. Apart from that, the design of stacked small transistors can also help alleviate the impact of temperature and process variations on the circuit performance. This is because, by spreading the small transistors across the entire chip, the effects of local temperature and process variations can be averaged out, thereby improving the stability and reliability of the circuit. In addition, by putting the small transistors into idle areas of the layout, the limited chip area can be effectively used to achieve a more compact layout, thus reducing the overall chip size [3]. As an example, Figure 20 shows the idea of stacked multiple transistors [57].

4.3.4. Matched Resistor Topology

Refs. [12,21] used a matched resistor topology to avoid the problem of current mirror mismatch, as shown in Figure 21. In this topology, two resistors $R_1$ and $R_2$ are used to ensure the current matching between the two branches and therefore the MOSFET-based current mirror is no longer needed. Here, since $R_1$ and $R_2$ are equal, the reference voltage can be calculated in the following way:

$$V_{ref}=V_{EB2}+{\displaystyle \frac{R_2}{R_3}}{V}_{T}lnN$$

(56)

This topology is advantageous compared to the MOSFET-based current mirror as its mismatch error is much smaller and can be easily removed. It only results in a PTAT error, which can be removed by a single trim [12]. This is different from the current mirror mismatch. The current mirror mismatch always results in non-PTAT errors, that are often more difficult to eliminate.

4.3.5. Regulated Cascode Current Mirror

The inaccuracy of the current mirror is not only caused by the device mismatch, but also caused by channel-length modulation. Specifically, in a current mirror, the drain-source voltage variations of the MOS transistor can seriously affect the accuracy of its drain current. To solve this issue, the regulated cascode current mirror was proposed in [58], which is much more accurate than the classic cascode current mirror and Wilson current mirror.

Here, to understand the regulated cascode current mirror, let us look at channel-length modulation first. Channel-length modulation can be seen in the drain-source current of the MOS transistor as follows:

$$I_{DS}={\displaystyle \frac{\beta }{2}}{(V_{GS}-V_T)}^2(1+\lambda V_{DS})$$

(57)

where $\beta =\mu C_{OX}{\displaystyle \frac{W}{L}}$ is the current gain of the MOS transistor. As can be seen, when the drain-source voltage $V_{DS}$ changes, the drain-source current $I_{DS}$ changes as well. Specifically, if the drain-source voltage variation is $\mathsf{\Delta }{V}_{DS}$, then the output current variation will be $\mathsf{\Delta }{I}_{DS}$ ($={\displaystyle \frac{\beta }{2}}{(V_{GS}-V_T)}^2\lambda \mathsf{\Delta }{V}_{DS}$) due to the channel-length modulation effect. This means that the output resistance of the MOS transistor is $r_o\approx {\displaystyle \frac{1}{\lambda I_{DS}}}$. In order to increase the output resistance of the current mirror, the classic techniques include the cascode current mirror and the Wilson current mirror, whose output resistances are both $g_m{r}_o^2$. Nevertheless, the problem is that in a high-accuracy bandgap reference, especially a ${\mathrm{sub-ppm/}}^{\circ }$C bandgap reference, this kind of output resistance is still not large enough. To solve this issue, refs. [16,18,46,59] used a regulated cascode current mirror, which was first proposed by [58].

Figure 22 shows this regulated cascode current mirror. As can be seen, it uses an amplifier to accurately control the drain voltage of the MOS transistor, so that current matching between $M_1$ and $M_2$ is guaranteed. For easy understanding, the following equation shows the output resistance of the regulated cascode current mirror:

$$R_{out}=A·g_{m3}{r}_{o2}{r}_{o3}$$

(58)

As can be seen, its output resistance is greatly increased, since the amplifier’s open-loop gain A can be designed to be very large. This helps guarantee accurate matching in the current mirror. Apart from that, this regulated cascode current mirror also has the advantage of a large output voltage swing. This is because the voltage drop across the output transistors $M_2$ and $M_3$ is as small as 2$V_{Dsat}$. This small voltage drop also makes it suitable for low-voltage applications. Apart from that, its disadvantage is that it uses an extra amplifier, wasting a lot of energy and area.

4.4. Summary

To gain an overall understanding of the above-mentioned techniques, we performed a statistical analysis of these techniques, summarized from 51 papers. This analysis is illustrated in Figure 23 and Figure 24, where Figure 23 shows the techniques for realizing the specific accuracy of the bandgap reference, and Figure 24 shows the important error sources that should be considered when realizing the specific accuracy of bandgap reference. Here, we focus on different accuracy ranges of the bandgap reference, including sub-1 ppm/°C, 1∼$10 {\mathrm{ppm/}}^{\circ }$C, 10∼$15 {\mathrm{ppm/}}^{\circ }$C, and 15∼$20 {\mathrm{ppm/}}^{\circ }$C. This summary is important, since it provides us with clear guidance before we start to design the bandgap reference with a specific accuracy. In particular, for different accuracy ranges we have the following conclusions.

For the 15∼$20 {\mathrm{ppm/}}^{\circ }$C range, the most important error sources that should be considered include the opamp offset and the $V_{BE}$ nonlinearity. In this situation, the most commonly used techniques to reduce the opamp offset include the chopping technique and the self-biasing technique. In addition, the techniques to reduce the $V_{BE}$ nonlinearity include simple piecewise compensation. Since 15∼$20 {\mathrm{ppm/}}^{\circ }$C accuracy is easy to realize, it is sufficient to use only a simple piecewise compensation.

For the 10∼$15 {\mathrm{ppm/}}^{\circ }$C range, the $V_{BE}$ nonlinearity starts to become a dominant error source. Under this circumstance, it is necessary to use more complicated curvature compensation techniques, such as piecewise compensation, second-order curvature compensation, and TlnT compensation. Apart from that, the chopping technique is also usually used in order to cancel out the opamp offset error.

For the 1∼$10 {\mathrm{ppm/}}^{\circ }$C range, the $V_{BE}$ nonlinearity is still a dominant error source. And therefore, it is necessary to use more effective curvature compensation techniques, such as piecewise compensation, TlnT compensation, and other high-order curvature compensation techniques. Apart from that, the chopping techniqe is still needed to cancel out the opamp offset error.

For the ${\mathrm{sub-1ppm/}}^{\circ }$C range, the $V_{BE}$ nonlinearity is not only a dominant error source, but also an error source that must be completely canceled out. Under this circumstance, the extremely accurate compensation techniques are required, which requires using several compensation techniques simultaneously, including multi-section piecewise compensation, TlnT compensation, and other high-order curvature compensation techniques. Apart from that, it is often necessary to design highly accurate current mirrors. And therefore, the resistor feedback technique is usually required as well.

Overall, across the entire accuracy range, we can see that the $V_{BE}$ nonlinearity is always the most important error source in the bandgap reference. And for this reason, in recent decades, curvature compensation techniques have been a hot topic of research. And it can be anticipated that, in the near future, more accurate and low-cost compensation techniques are going to be invented.

5. Sub-1V Reference

The previous section mainly discusses how to improve the accuracy of the bandgap reference, but it does not investigate the way to reduce the supply voltage and the power consumption. Especially, with the development of portable battery-powered devices and the Internet of Things (IoT), there is an increasing demand to operate under a low supply voltage and with a low power consumption. Also, with the continual scaling down of modern CMOS processes, the supply voltage is going to decrease as well. For these reasons, sub-1V reference circuits have become more and more popular in recent years. In the following, this section focuses on the recent techniques to realize sub-1V reference circuits.

5.1. Current-Mode BGR

As mentioned before, there are two types of BGR circuits, which are voltage-mode BGRs and current-mode BGRs. Among them, voltage-mode BGRs have a relatively fixed reference voltage of approximately 1.25 V. And therefore, the supply voltage must be larger than this value [60] (for example, a 1.8 V supply voltage can be used). By contrast, current-mode BGRs are suitable for realizing a sub-1V design. The earliest sub-1V BGR was proposed by Banba in 1999 [9]. In this Banba structure, the supply voltage is greatly reduced to approximately $V_{EB}+V_{DS}$ [9], which was around 0.7 V in [61]. Overall, current-mode BGRs have been widely used in recent years in order to realize supply voltages of 0.7∼1 V.

5.2. BGR with Charge Pump

If we want to further reduce the supply voltage, it is a good choice to use a switched-capacitor reference with a charge pump. Specifically, the charge pump helps reduce the supply voltage by half, usually to around 0.5 V [62,63,64,65,66] or even below.

Figure 25 shows a typical BGR with charge pump. Its minimum supply voltage $V_{in}$ is equal to $V_{EB}/2$, which is as small as approximately 375 mV [65]. It uses a 2× charge pump to double the supply voltage. This doubled supply voltage drives the BJTs to generate $V_{EB1}$ and $V_{EB2}$, which are stored onto $C_{L1}$ and $C_{L2}$, respectively. Meanwhile, the difference between $V_{EB1}$ and $V_{EB2}$ is stored onto $C_{\mathsf{\Delta }}$. And finally, the switched-capacitor network sums these PTAT and CTAT voltages together with appropriate weights in order to generate a reference voltage $V_{ref}$.

Nevertheless, the limitation of such a BGR structure is that, since the driving capability is an important consideration, it cannot unconditionally reduce the supply voltage. As a result, it is not easy to design this structure [40].

5.3. MOSFET-Based Voltage Reference

In a classic BGR circuit, the PTAT voltage is usually generated by the base-emitter voltage difference between two BJTs. Nevertheless, the disadvantage is that this requires a relatively high supply voltage. By contrast, an MOSFET-based PTAT generator is more suitable for low-voltage applications. It uses the gate-source voltage difference between two MOS transistors in the sub-threshold region in order to generate the PTAT voltage [61,64,67,68].

Figure 26a shows an MOSFET-based PTAT generator with a differential pair structure [61,64,67], while Figure 26b shows a PTAT generator with a series-connected structure [69]. Both of these PTAT generators consist of two MOS transistors, $M1$ and $M2$, operating in the sub-threshold region. And the gate-source voltage difference of these MOS transistors can be calculated as follows [61]:

$$\mathsf{\Delta }{V}_{GS}=V_{GS,M2}-V_{GS,M1}=n{V}_{T}ln\left({\displaystyle \frac{W_1/L_1}{W_2/L_2}}\right)$$

(59)

where $W/L$ is the width-to-length ratio of the MOS transistor. As can be seen, it generates a PTAT voltage, which is desirable.

Apart from that, the CTAT voltage can be generated by using the gate-source voltage of a single MOS transistor operating in the sub-threshold region [70], since the threshold voltage $V_{th}$ is CTAT. And therefore, by combining these PTAT and CTAT voltages together in a proper proportion, a reference voltage can be generated. This kind of voltage reference circuit has the advantage of low-voltage operation. It only uses MOS transistors, and an MOS transistor usually has a much lower gate-source voltage than the base-emitter voltage of a BJT. And therefore, it can operate under a much lower supply voltage and with a much lower power consumption when compared to a BJT-based bandgap reference circuit. Nevertheless, its disadvantage is that the threshold voltage $V_{th}$ is sensitive to process variations. This causes its reference voltage to have a worse temperature coefficient when compared to the BJT-based bandgap reference circuit.

Overall, the MOSFET-based voltage reference uses only MOS transistors, and its generated reference voltage is no longer equal to the bandgap voltage [61,64,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81]. Therefore, this kind of circuit is called a voltage reference circuit, rather than a bandgap reference circuit. For this reason, we do not discuss this kind of circuit in more detail, as it is not the topic of this paper.

6. Conclusions

This review provides a comprehensive analysis of the operating principles and error sources in bandgap reference circuits, highlighting the key challenges in achieving high accuracy. By examining various error sources, including the amplifier offset, the $V_{BE}$ nonlinearity, and the current mirror mismatch, this review summarizes different kinds of techniques to improve the accuracy. When discussing these techniques, this review focuses on different accuracy ranges of the bandgap reference, including ${\mathrm{sub-1ppm/}}^{\circ }$C, 1∼$10 {\mathrm{ppm/}}^{\circ }$C, 10∼$15 {\mathrm{ppm/}}^{\circ }$C, and 15∼$20 {\mathrm{ppm/}}^{\circ }$C. This classification is useful, since it helps us easily choose an appropriate technique in order to realize the target accuracy of the bandgap reference. Finally, apart from the discussion of accuracy, this review also summarizes low-voltage designs. Especially, it summarizes the advancements in recent sub-1V bandgap reference circuits.

Overall, in a high-accuracy bandgap reference design, the most important technique is the curvature compensation technique. And therefore, in the future, we believe that bandgap reference circuits will have the following two directions of development. The first direction is to propose a novel curvature compensation technique, in order to achieve an ultra-high accuracy, for example, <$0.5 {\mathrm{ppm/}}^{\circ }$C. The second direction is to not only realize a high accuracy but also greatly reduce the cost, for example, reduce the circuit complexity, reduce the supply voltage, and reduce the power consumption.