Chips

Main memory carries data outside the processor’s trust boundary, so commodity systems-on-chip (SoCs) increasingly encrypt it; yet, in-line memory encryption engine itself becomes a differential power analysis (DPA) target whose key, if recovered, unlocks all of dynamic random-access memory (DRAM). We present PACE, a page-adaptive, cache-anchored memory encryption engine for RISC-V that makes nth-order DPA resistance practical and keeps cryptographic latency off the cache eviction critical path. PACE inserts a TileLink adapter between the last-level cache and the memory port and applies, per physical page, one of four policies (plaintext/confidentiality/confidentiality+integrity/+masking-order-d) selected from RISC-V page table bits through a memory-mapped control plane. Confidentiality uses counter mode whose per-line keystream is precomputed during cache residency; integrity is tree-free at the embedded operating point via on-chip counters and tags, with a live split counter block-MAC Bonsai Merkle tree for scale-out. DPA resistance is layered: ISAP-style fresh re-keying caps the data complexity per key at $q\approx 1$, and domain-oriented masking (DOM, d + 1 shares) protects the sole key processing block to order d. We implement PACE in Chisel on a Rocket SoC (Chipyard) and evaluate it with open-source tooling. A deterministic TileLink-level harness proves ciphertext-in-memory and detects tamper/replay/splice, and the live Tier-B engine (DRAM counters and per-line message authentication codes (MACs) plus an on-chip-rooted block-MAC tree) is validated from end to end on full Rocket and BOOM SoCs and on the FPGA; the masked Ascon-p S-box is proven order-d secure (d = 1, 2) under a glitch- and transition-aware model by three independent formal tools (COCO, PROLEAD, and SILVER, the last also deciding the full composability lattice and confirming exact glitch-robust order-2 probing security), with COCO extending the exact verdict to the highest synthesized order d = 3 (secure at probing orders 1–3); a simulated trace correlation power analysis (CPA) recovers the full key from an unprotected core and is defeated by masking, with a mutual information analysis confirming the $N\propto {\sigma }^{2(d+1)}$ trace amplification law. We further realize PACE on field-programmable gate array (FPGA) silicon: the engine plus an on-chip ring oscillator power sensor is placed, routed, timing-closed at 100 MHz, and programmed on a Xilinx XC7Z020, and we drive a fixed-vs-random Test Vector Leakage Assessment (TVLA) campaign read back entirely over a JTAG (Joint Test Action Group). A multi-core configuration and a Linux control-plane driver are likewise validated. Across synthetic access patterns and named application kernels (AES, SHA-256, matrix multiplication, pointer chasing) on both in-order Rocket and out-of-order BOOM, application-level overhead is within measurement noise of plaintext for cache resident workloads (masking, in particular, is cycle-identical to plain confidentiality), and we characterize the cost of each policy, masking order, and re-keying interval, demonstrating side-channel-hardened memory encryption on open RISC-V hardware. Full article

Modern embedded systems are vulnerable to complex data-oriented attacks that subvert not only existing control-flow integrity protections but also have dire implications on safety-critical applications. To overcome this challenge, this work proposes a secure RISC-based architecture that incorporates hardware-assisted Data-Flow Integrity (DFI) enforcement into the processor pipeline. The architecture uses tag-based metadata propagation, a Security Monitor Unit, and compiler support for static analysis in order to ensure the validity of dynamic data flows without affecting execution. A complete RTL prototype was designed and tested with MiBench and CoreMark. Results show an average performance overhead of 11.3% and a logic utilization increase of <9.2% on FPGAs, while achieving 100% detection of all attempted pointer corruption and data tampering attacks. These results indicate the efficacy of the lightweight security-aware RISC architecture as a feasible compromise between security, performance, and hardware expense in today’s embedded systems. Full article

The interfacial adhesion strength of fine lines for flip-chip ball grid array (FCBGA) substrates is highly dependent on the surface desmear process during substrate manufacturing. However, the extremely narrow window for optimal desmear processes limits the improvement of the adhesion strength of fine lines. Herein, a polydopamine-modified epoxy build-up film substrate was fabricated to increase chemical bonding action and broaden the process window. The chemical structure, surface roughness, morphology, surface chemical state, and adhesion strength of the modified substrate were characterized. The results showed that the adhesion strength of the substrates increased from 2.2 N/cm to 4.1 N/cm under suboptimal process conditions. Meanwhile, the effect of the polydopamine deposition time on the adhesion strength of the copper-deposited epoxy resin composite films at the interfaces was systematically investigated; furthermore, the mechanisms and reasons for the increased adhesion strength and interfacial adhesion failure for the copper-deposited epoxy resin composite build-up film substrates were revealed. This work will provide guidance in both theory and experiment to enhance the interfacial adhesion force for advanced substrates in the future. Full article

Low-Density Parity-Check (LDPC) codes have traditionally performed better at longer code lengths. This research develops and rigorously evaluates a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G and subsequent technologies. The paper investigates LDPC codes in short-length contexts through architectural optimization based on a layered decoding approach, which provides improved convergence speed and reduced latency compared with traditional flooding techniques. The short block-length QC-LDPC code ($280,176$) addresses the dual challenge of achieving ultra-low latency while maintaining high performance relative to existing work. For a target BLER of ${10}^{-2}$, the decoder outperforms the shorter reference codes ($60,40$) and ($96,64$), with an $E_b/N_0$ gain of up to $0.9$ dB, part of which is attributable to the longer block length rather than to the decoder alone. The FPGA implementation results demonstrate that the design is hardware-efficient: it operates at a maximum frequency of $218.62$ MHz, resulting in a throughput of $155.77$ Mbps, while maintaining a decoding latency of only $1.129$ µs and a power consumption of $0.201$ W. Full article

The transition from electrical to optical interconnects, enabled by the adoption of co-packaged optics (CPO) in advanced processors, is accelerating the scale-up to high volumes and redefining wafer-level test requirements. As optical interfaces migrate closer to the compute die, an increasing share of functional characterization must occur at the probe, where stringent sub-micron alignment, the mechanical stability necessary to preserve optical coupling against dynamic disturbances, and opto-electrical co-validation introduce new technical challenges. Ensuring repeatable and precise fiber-array-unit (FAU) engagement at the wafer level is therefore essential to enable scalable manufacturing of photonic-enabled processors. This paper introduces the EclipsePhotonic probe card, which embeds the Eclipse Dynamic piezoelectric positioning mechanism into a standard vertical-needle probe head as a route toward six-degree-of-freedom FAU manipulation with nanometric positioning accuracy. This architecture is designed to support repeatable coupling to on-wafer photonic structures without requiring specialized probe-head designs, thereby reducing integration complexity and addressing alignment-related yield risks. The platform is also intended to support multi-site electrical and optical probing, providing a path toward parallel test execution once the corresponding layout, optical-routing, and validation constraints are satisfied. A core innovation of the platform is its embedded sensor network, which integrates low- and higher-frequency displacement sensors, relative displacement sensors, and temperature sensors around a microcontroller-based supervisor. The vibration sensor fulfills a dual operational role: it detects environmental and test-cell disturbances that may have influenced optical coupling, providing essential context for binning decisions or targeted retest, and it contributes to probe card lifecycle monitoring by ensuring that the mechanical signature of the probe card remains within a validated operational “swim lane” throughout its service life. Recently published characterization of the underlying Eclipse Dynamic alignment engine shows that, in the production-optimized high-speed regime with effective hysteresis compensation, the Fixed Gradient routine provides the best normalized trade-off among the evaluated routines, with a normalized alignment cost of 1.44 a.u., 95.8% convergence reliability, and 99.4% of the global maximum optical coupling. These values should be interpreted as inherited algorithmic benchmarking results rather than as absolute wall-clock performance of the fully integrated sensor-augmented platform. Full article

This work presents a power-friendly framework for efficient manufacturing test of dynamic voltage and frequency scaling (DVFS)-based 3D Systems-on-Chip (SoCs). The proposed approach employs a through-silicon via (TSV)-based inter-layer test architecture to enable compact and high-speed delivery of test data across stacked dies, while a bus-based space- and time-division multiplexing (SDM/TDM) mechanism distributes test data within each layer. Based on this architecture, a test access mechanism (TAM) optimization method is introduced to reduce TSV usage, improve bandwidth utilization, and minimize test application time. The optimization process uses effective pruning criteria to limit the exploration of inefficient TAM configurations while preserving promising design alternatives. In addition, advanced test-scheduling methods are developed to exploit TDM-based parallelism and flexibility, while explicitly enforcing power constraints at the SoC, layer, and voltage-island levels. These scheduling methods combine fast heuristic construction with metaheuristic optimization techniques to improve solution quality without excessive computational cost. Experimental evaluation on artificial DVFS-based 3D SoC instances demonstrates that the proposed framework achieves reductions in TSV count and effectively limits the overall test time compared with baseline approaches. The results confirm that jointly considering TAM design, DVFS-aware scheduling, and power constraints provides an effective and scalable solution for testing complex DVFS-based 3D SoCs. Full article

The growing deployment of Internet of Things (IoT) monitoring systems has resulted in demands for low-latency, secure, and energy-efficient intelligence on embedded chips. But most cloud-based and edge-assisted solutions are prone to high communication latency, lack adaptability, consume more energy, and lack decision security under resource-limited conditions. This paper introduces an Edge-Intelligent IoT Framework for Real-Time Adaptive Monitoring and Trust-Aware Secure Decision Validation with Resource-Aware Artificial Intelligence and Machine Learning (AI/ML) on embedded chips. Unlike conventional TinyML or Edge AI deployments that use a fixed inference model, the proposed framework introduces a validation-calibrated adaptive inference mechanism that jointly considers chip resources, input complexity, and sensor trust before accepting an embedded decision. The main scientific contribution is the unified coupling of resource-aware model selection with trust-aware decision validation for low-power embedded IoT inference. The framework dynamically selects the inference path and validates sensor trust before decision acceptance. Through experimentation, the proposed framework is demonstrated with 97.2% accuracy, 96.4% F1-score, and 98.1% AUROC, and 40.4% lower inference latency (31.2 ms to 18.6 ms) and 39.6% lower energy (9.6 mJ to 5.8 mJ) compared with traditional TinyML deployment. These results were obtained using the MHEALTH wearable IoT dataset with a leakage-safe 70:15:15 split and were statistically validated across five independent runs. The findings demonstrate a promising resource-aware TinyML-style embedded inference pipeline for wearable IoT monitoring, with improved latency-energy efficiency and trust-aware decision validation under the evaluated settings. Full article

The rapid adoption of Wide Band Gap (WBG) semiconductor technologies, particularly Silicon Carbide (SiC) and Gallium Nitride (GaN), together with emerging Ultra-Wide Band Gap (UWBG) materials such as AlGaN, Aluminum Nitride (AlN), Diamond, β-gallium oxide (β-Ga₂O₃), and Hexagonal Boron Nitride (h-BN), is reshaping wafer-level electrical testing beyond the capabilities of conventional silicon-based probing infrastructures. The increasingly demanding electrical, thermal, and mechanical operating conditions of these devices require probe cards to evolve from passive interconnects into integrated multiphysics systems capable of supporting high voltages, high current densities, and fast switching transients. This review analyzes the fundamental design constraints governing advanced probe card technologies, including probe-to-wafer contact physics, electrothermal behavior, insulation requirements, parasitic effects, and high-frequency performance. Particular attention is devoted to Vertical MEMS probe card architectures, which enable high contact density, low parasitic inductance, and improved current-carrying capability, making them particularly suitable for modern WBG applications. Emerging solutions, including ceramic insulation structures, controlled-atmosphere testing environments, integrated sensing, and advanced thermal management techniques, are also discussed. Furthermore, the paper examines the evolution of wafer-level testing strategies, from conventional parametric screening to reliability-oriented methodologies inspired by burn-in procedures, highlighting the growing importance of body-diode characterization for early defect detection in SiC devices. Beyond reviewing the current state of the art, this work proposes a structured taxonomy of probe card technologies and outlines a technology roadmap linking future WBG and UWBG device requirements with the evolution of wafer-level testing infrastructures. Full article

The growing demand for reliable wearable devices that can continuously monitor vital signs and track health under various conditions imposes challenging constraints on battery life. Wearable devices typically include a Photoplethysmogram (PPG) sensor, which is used for various applications such as monitoring heart rate (HR) and blood oxygenation (${\mathrm{SpO}}_2$). The efficiency of these applications depends on the quality of the PPG sensor, which acquires raw data through the analog front-end and transmits it externally. This paper presents a digital block that evaluates the quality of the PPG signal directly within the ASIC. The proposed Signal Quality Assessment (SQA) module is derived from post-processing algorithms and translated into a real-time, single-sample evaluation approach, providing significant benefits at both the sensor and system levels. The proposed solution achieves performance comparable to state-of-the-art methods, with a sensitivity of 95.2%, a specificity of 88.1%, and an accuracy of 89.52%, while introducing an extremely low energy overhead equal to $5.38$ μ$\mathrm{J}$. Full article

This paper presents an open-source miniaturised readout device designed for the wireless interrogation of passive LC sensors and wireless power transmission. The system is based on a Sparkfun RedBoard Artemis microcontroller with a custom-printed circuit board as an extension, providing a compact, low-cost alternative to expensive laboratory-grade equipment. The reader coil is excited by a signal that can be tuned digitally in both frequency and amplitude. The resonance frequency of a wirelessly coupled LC tank is detected by monitoring the voltage minimum of a rectified signal envelope, which corresponds to the impedance change of the reader inductance at resonance. Experimental validation demonstrates that the device accurately tracks resonance frequency shifts resulting from variations of the LC tank’s capacitance, performing comparably to laboratory-grade impedance analysers. Testing the influence of axial separation between the two coils up to 25 $\mathrm{m}$$\mathrm{m}$ showed stable and identifiable voltage dips. The programmable excitation signal peak-to-peak voltage ranges from $0.81$ V to $5.35$ V. The device enables fully stand-alone operation with a display and navigation switch, making it suitable for untethered LC wireless sensing and actuation applications. Full article

DIGOTA architectures have attracted growing interest as a means of addressing the problems that arose with the extreme miniaturization of the MOS transistor in analog design. Despite the increasing number of proposed architectures, the literature remains fragmented, with differences in design goals, structural choices, and evaluation criteria that make direct comparison difficult. This paper presents a comprehensive survey of DIGOTA architectures reported in the literature so far. This review study is organized according to key architectural characteristics, including biomedical applications, flexible electronics, and low-power amplifiers. Based on this analysis, the paper discusses major trends, common trade-offs, strengths, and limitations across current approaches. The survey also identifies open issues and promising directions for future research. By providing a structured overview of the field, this work serves as a useful reference for researchers seeking to understand, compare, and develop DIGOTA architectures. Full article

This work presents a comprehensive analytical and simulation-based comparison between bulk-driven (BD) and gate-driven (GD) operational transconductance amplifiers (OTAs) operating in the deep-subthreshold ultra-low-voltage regime. While BD techniques are traditionally considered unsuitable for high-performance analog design due to their lower transconductance efficiency, this study demonstrates that, when combined with self-cascode structures, BD architectures achieve competitive intrinsic gain, enhanced input common-mode range, and improved slew rate efficiency under nanoampere bias conditions. To support these claims, closed-form analytical derivations, dynamic analysis, and comprehensive Monte Carlo and PVT simulations are provided to quantify robustness and mismatch sensitivity. The results establish a systematic framework for evaluating BD versus GD architectures under identical technology and power constraints, offering practical design guidelines and optimized self-cascoded topologies for next-generation energy-autonomous systems. Full article

This paper presents a rule-based LVS-driven methodology for parasitic RC extraction from CMOS layouts for post-layout SPICE simulation. The proposed approach operates directly within foundry-qualified rule environments, ensuring consistency with Process Design Kits (PDKs) and enabling seamless integration with existing design and verification flows without requiring field-solver execution during the production extraction flow. The methodology provides a generalized framework for deriving electrical parameters from layout geometries and is applicable to interconnects, contacts, vias, and gate structures in multilayer CMOS technologies. By decomposing conductive regions into directional components and applying geometric and Boolean operations, the method captures the impact of layout topology and process-dependent features on circuit-level behavior. In addition, a model-order reduction technique based on π-equivalent representations is introduced to simplify the resulting networks while preserving timing accuracy. This enables the scalable simulation of complex layouts with reduced computational overhead. The proposed framework supports layout optimization, variability-aware design, and process-technology co-design, particularly for mature and advanced planar nodes. The methodology is evaluated using register-file layout test cases and post-layout SPICE simulations. The results show that the proposed rule-based extraction and RC-merging flow preserve timing behavior while reducing netlist complexity. Full article

With the increasing complexity and connectivity of modern digital systems, verification has emerged as a critical bottleneck in the design flow. Assertion-Based Verification (ABV) has proven to be one of the most effective techniques for presilicon verification. Once assertions are generated, they can be synthesized into hardware monitors and incorporated into the design debug infrastructure. Many Design-for-Debug (DfD) methodologies leverage such hardware monitors to enhance the observability and controllability of internal system behavior, thereby accelerating verification and reducing time to market. Post-silicon debugging also benefits from the improved observability provided by these monitors. Furthermore, hardware monitors can be employed during runtime to detect and report undesired behaviors. To enable the seamless use of assertions, which are originally expressed in verification languages, throughout the entire design life cycle, several assertion synthesis approaches have been proposed. The objective of this survey is to present the existing assertion synthesis methods reported in the literature, discuss their current limitations, and identify directions for future research and improvement. Full article

This paper presents the Spike Processing Unit (SPU), a digital spiking neuron model based on a discrete-time second-order Infinite Impulse Response (IIR) filter. By constraining filter coefficients to powers of two, the SPU implements all internal operations via shift-and-add arithmetic on 6-bit signed integers, eliminating general-purpose multipliers. Unlike traditional models, computation in the SPU is fundamentally temporal; spike timing emerges from the interaction between input events and internal IIR dynamics rather than signal intensity accumulation. The model’s efficacy is evaluated through a temporal pattern discrimination task. Using Particle Swarm Optimization (PSO) within a hardware-constrained parameter space, a single SPU is optimized to emit pattern-specific spikes while remaining silent under stochastic noise. Results from cycle-accurate Python simulations and synthesizable VHDL implementations indicate that the learned temporal dynamics are preserved under hardware-constrained digital execution, supporting the feasibility of the proposed approach. This work demonstrates that discrete-time IIR-based neurons enable reliable temporal spike processing under strict quantization and arithmetic constraints. Full article

Hyperdimensional computing (HDC) provides a highly efficient alternative to neural networks for intracranial electroencephalography (iEEG) seizure detection on edge devices with strict resource limits. While sparse HDC can significantly reduce energy use, current hardware fails to capitalize on this for two reasons. First, existing designs do not optimize the encoding architecture specifically for sparse execution, leaving potential energy savings on the table. Second, researchers often ignore the “area” problem, the large physical space high-dimensional vectors take up on a chip, which must be solved to make these devices small enough for practical edge use. This work presents a sparse HDC accelerator that bridges these gaps through three key contributions. First, we streamline the sparse encoding architecture to improve energy and area efficiency by integrating a compressed item memory (CompIM) and simplified spatial bundling. Second, to address the area bottleneck and enable true edge deployment, we systematically explore area trade-offs via sequentialization techniques, evaluating both channel folding (CF) and vector folding (VF). Third, we push efficiency even further by proposing an item-memory-free (IM-free) architecture. By replacing the baseline segmented shift binding with a standard shift binding scheme, and gracefully utilizing raw local binary pattern (LBP) codes directly as shift amounts, we completely bypass the CompIM for simultaneous area and energy savings. However, this optimization incurs a drop in detection accuracy; hence, we ultimately present two tailored configurations. First, our energy-optimized IM-free design achieves a 5.55× area and 3.08× energy improvement over the sparse HDC baseline, alongside 8.20× and 13.37× improvements over the dense baseline. Second, to prioritize clinical performance, our balanced streamlined design utilizes a channel folding factor (CFF) of 4 to preserve higher accuracy. This balanced approach achieves a 5.97× area and a 4.66× energy improvement over the dense baseline, with a 4× latency increase. Full article

The rapid expansion of the Internet of Things (IoT) has opened resource-limited devices to novel physical threats, such as Side-Channel Attacks (SCAs) and Hardware Trojans (HTs). Traditional security mechanisms are often not capable of standing against such hardware-based attacks, specifically on low-power System-on-Chip (SoC) where static defenses can incur 2× to 3× overhead in silicon area and power. Herein, the gap between hardware security and embedded AI is compositionally formulated for discussion. We present a comprehensive survey of the current hardware threat landscape and analyze the emergence of “Secure-by-Design” paradigms, specifically focusing on the integration of Edge AI and TinyML as active, on-chip intrusion detection mechanisms. This review presents a critical analysis of trade-offs for running lightweight ML models on hardware by comparing state-of-the-art approaches. Our analysis highlights that optimized architectures, such as Mamba-Enhanced Convolutional Neural Networks (CNNs) and Gated Recurrent Unit (GRU), can achieve detection accuracies exceeding 99% against SCA and >92% against stealthy Hardware Trojans, while offering up to 75% lower power consumption compared to standard deep learning baselines. Finally, open challenges such as adversarial attacks on defense models are briefly discussed, and the focus is put on future directions toward constructing secure chips based on robust, AI-driven technology. Full article

For sensing applications, a complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a lateral overflow integration capacitor (LOFIC) is in high demand. The LOFIC CIS can achieve high-dynamic-range (HDR) imaging by combining a low-conversion-gain (LCG) signal for large maximum signal electrons and a high-conversion-gain (HCG) signal for a low electron-referred noise floor. However, the LOFIC CIS faces challenges regarding the power consumption and circuit area when reading both HCG and LCG signals. To address these issues, this study proposes a readout circuit composed of area-efficient MOS capacitors using a folding DC operating point technique and an in-column signal selector for an on-chip HDR merger of HCG and LCG signals. A 10-bit test chip was fabricated with a $0.18$ µm CMOS process with MOS capacitors. The fabricated chip maintains high linearity, achieving an integral nonlinearity (INL) of +7.17/−6.93 LSB for the HCG signal and +7.95/−7.41 LSB for the LCG signal. Furthermore, the proposed design achieves a $14.92\%$ reduction in the average power consumption of the total readout circuit and a $36.5\%$ reduction in the readout circuit area. Full article

The fast expansion of the Internet of Things (IoT) has increased the need for strong security measures to protect the enormous network of interconnected devices. This paper proposes a unique approach that combines optimization, intuitive design principles, and Least Weighted Elliptic Curve Cryptography (LWECC) to improve IoT device security while reducing power consumption. The proposed optimization strategy focuses on lowering computational overhead, which is critical for IoT devices with limited energy and processing power. The proposed method significantly reduces the amount of energy required for cryptographic operations by carefully selecting appropriate elliptic curves and optimizing cryptographic algorithms, ensuring that IoT devices may continue to function without compromising security. Furthermore, by selecting elliptic curves with minimal attack vulnerability, the use of LWECC provides an additional layer of protection. This technique ensures that, even in the face of emerging threats, IoT devices remain highly resilient, reducing the chance of security breaches while preserving functionality without using excessive power. Experimental results show a power consumption of only 0.156 W and 0.25 W for memory and router topologies, respectively, with an error margin of 0.01. The stated error margin pertains to the simulation-based evaluation of transmission-level data handling within the LWECC-enabled memory/router pipeline, rather than the risk of physical memory-cell failure or fabrication yield. The value shows the maximum amount of packet/data-stream loss detected during encrypted data transfer, rather than hardware memory reliability. Full article