Chips

The TDM Test Scheduler and TAM Optimization Toolkit is a novel, integrated, and user-friendly solution designed for engineers, researchers, and instructors working in the field of manufacturing tests. It effectively supports test planning for multicore, DVFS-based SoCs with multiple voltage islands, offering optimized solutions that minimize test costs while ensuring compliance with power and thermal constraints. The toolkit provides (a) a high-level language (HLL) for the intuitive representation of test processes, along with a smart syntax and logic checker for verification; (b) an advanced compilation and execution environment featuring two computationally efficient Time-Division Multiplexing (TDM)-specialized solvers; (c) a sophisticated Test Access Mechanism (TAM) optimization framework; (d) a customized visualization environment capable of depicting and animating power- and thermal-annotated test schedules; (e) a versatile testbed for educational and research activities. Full article

This work presents a cost-effective optical frequency comb generator (CEOFCG) solution for generating multiple, equally spaced carriers in wavelength-division-multiplexing coherent optical fiber communication systems (WDM-COFCS). It enables the replacement of multiple laser sources with a single continuous-wave laser, eliminating the need for additional amplification and filtering setups. The CEOFCG provides stable multicarrier spacing, broad phase coherence, and compatibility with advanced modulation formats, enhancing the performance of WDM-COFCS. Digital signal processing (DSP) techniques, including digital filtering, detection, and impairment compensation, contribute to high transmission and spectral efficiency (SE). The results demonstrate the potential of CEOFCG in achieving cost reduction, complexity reduction, high SE, and optimal utilization of optical fiber bandwidth, particularly in higher-order QAM-based COFCS. Full article

The rapid growth of the Internet of Things (IoT) has significantly expanded the deployment of resource-constrained devices, introducing new security and privacy challenges. To address these concerns, the National Institute of Standards and Technology (NIST) concluded a multi-year effort by announcing ASCON as the new lightweight cryptography standard in 2023. ASCON’s cipher suite includes both Authenticated Encryption with Associated Data (AEAD) and hashing functions, ensuring authenticity, confidentiality, and broad applicability. Since its standardization, there has been a significant research effort focused on enhancing ASCON’s performance under diverse application constraints as well as assessing its vulnerability to advanced side-channel attacks. This study offers a comprehensive overview of current ASCON hardware implementations on FPGA and ASIC platforms, examining key design trade-offs. Additionally, it examines the latest side-channel attacks on ASCON were examined. These attacks exploited weaknesses in the hardware implementations rather than in the algorithm itself. Being highly efficient, they could breach both unprotected and protected implementations. This survey also reviews the proposed countermeasures against these powerful attacks and analyzes how their associated overhead conflicts with the performance demands of real-world ASCON applications. The synthesis of these findings offers clear guidelines for designers seeking to implement ASCON. At the same time, areas requiring further investigation are identified. As ASCON sees ever more widespread deployment, this review serves as a reference for understanding the current state of research and guiding future developments toward efficient and secure implementations. Full article

This paper proposes novel two fault-tolerant routing methods for a 3D mesh network-on-chip (NoC). The existing method proposed by Boppana et al. combines two routing methods, minimal fully adaptive routing and fault-tolerant routing, for faulty region detouring. However, in the latter fault-tolerant routing, a detour direction is statically defined for each faulty region. Due to the long detour path and the use of eight virtual channels, this method has the problems of high communication latency and a large hardware overhead. To solve these problems, the first proposed method allows adaptive detours for faulty regions, and the second proposed method allows the passage of them. The simulation results show that, compared with the existing method, the second proposed method enables us to reduce the latency by about 30% and improve the throughput by about 3.1% with half of the virtual channels. Full article

With the increasing demand for efficient deep learning models in resource-constrained environments, Binary Neural Networks (BNNs) have emerged as a promising solution due to their ability to significantly reduce computational complexity while maintaining accuracy. Their integration into embedded and edge computing systems is essential for enabling real-time AI applications in areas such as autonomous systems, industrial automation, and intelligent security. Deploying BNN on FPGA using RISC-V, rather than directly deploying the model on FPGA, sacrifices detection speed but, in general, reduces power consumption and on-chip resource usage. The AI-extended RISC-V core is capable of handling tasks beyond BNN inference, providing greater flexibility. This work utilises the lightweight Zero-Riscy core to deploy a BNN on FPGA. Three custom instructions are proposed for convolution, pooling, and fully connected layers, integrating XNOR, POPCOUNT, and threshold operations. This reduces the number of instructions required per task, thereby decreasing the frequency of interactions between Zero-Riscy and the instruction memory. The proposed solution is evaluated on two case studies: MNIST dataset classification and an intrusion detection system (IDS) for in-vehicle networks. The results show that for MNIST inference, the hardware resources required are only 9% of those used by state-of-the-art solutions, though with a slight reduction in speed. For IDS-based inference, power consumption is reduced to just 13% of the original, while resource usage is only 20% of the original. Although some speed is sacrificed, the system still meets real-time monitoring requirements. Full article

Radiation effects on electronic devices represent a major concern in applications for harsh environments, such as aerospace and nuclear facilities. This article presents a review of fundamental aspects of radiation effects on semiconductors, with a primary focus on Single-Event Effects. It discusses charge collection models, destructive effects, applications in detectors, and impacts on digital devices, drawing from recent research findings. Full article

In this work, the simulation of deoxidation–oxidation of oxygen vacancies (V_Os) in an oxide matrix with embedded conductive nanocrystals (c-NCs) is carried out for the development of bipolar resistive switching memories (BRSMs). We have employed the three-dimensional kinetic Monte Carlo (3D-kMC) method to simulate the RS behavior of BRSMs. The c-NC is modeled as fixed oxygen vacancy (f-V_O) clusters, defined as sites with zero recombination probability. The three-dimensional oxygen vacancy configuration (3D-V_OC) obtained for each voltage step of the simulation is used to calculate the resistive state and the electrical current. It was found that the c-NC reduces the voltage required to switch the memory state from a high to a low resistive state due to the increase in a nonhomogeneous electrical field between electrodes. Full article

This article summarizes the current development status of nanoimprint lithography (NIL) technology and its application prospects in multiple industries. Nanoimprint lithography technology has significant advantages, such as low cost, high resolution, and no development, and is not affected by standing wave effects, making it a potential technology in industries such as semiconductors, photovoltaics, and LEDs. However, nanoimprint lithography technology still faces challenges in terms of film characteristics and material selection during application. This article analyzes existing research and discusses its application advantages in the fields of patterned sapphire substrates (PSSs), Light-Emitting Diode (LED) chips, photovoltaic cells, etc., and proposes the role of technological progress in promoting industrialization. This article summarizes the opportunities and challenges of nanoimprint lithography technology in the future industrialization process and anticipates its development prospects for large-scale production. Full article

The rapid advancement of artificial intelligence (AI) technologies has significantly increased the demand for high-performance computational hardware. Memristor-based compute-in-memory (CIM) technology, also known as resistive random-access memory (RRAM)-based CIM technology, shows great potential for addressing the data transfer bottleneck and supporting high-performance computing (HPC). In this paper, a multi-scale thermal model is developed to evaluate the temperature distribution in RRAM-based CIM chips and the influence of various factors on thermal behavior. The results indicate that hotspot temperatures can be mitigated by reducing the epoxy molding compound (EMC) thickness, increasing the substrate thickness, and lowering boundary thermal resistance. Moreover, optimizing the layout of analog computing circuits and digital circuits can reduce the maximum temperature by up to 4.04 °C. Furthermore, the impact of temperature on the conductance of RRAM devices and the inference accuracy of RRAM-based CIM chips is analyzed. Simulation results reveal that thermal-induced accuracy loss in CIM chips is significant, but the computation correction method effectively reduces the accuracy loss from 66.4% to 1.4% at 85 °C. Full article

High-dynamic-range (HDR) technology enhances the capture of luminance beyond the limits of traditional images, facilitating the capture of more nuanced and lifelike visual effects. This advancement has profound implications across various sectors, such as medical imaging, augmented reality (AR), virtual reality (VR), and autonomous driving systems. The evolution of complementary metal-oxide semiconductor (CMOS) image sensor (CIS) manufacturing techniques, particularly through backside illumination (BSI) and advancements in three-dimensional (3D) stacking architectures, is driving progress in HDR’s capabilities. This paper provides a review of the technologies developed over the past six years that augment the dynamic range (DR) of CIS. It systematically introduces and summarizes the implementation methodologies and distinguishing features of each technology. Full article

Leading-edge analog/mixed-signal LSI designs are still hand-crafted using graphic editors. These graphic editors do not include functionality for parameterized topologies in variable designs. Instead of graphic editors, we have developed the SWA (SoftWare Analog) language, which can describe and display placements and routing for analog/mixed-signal LSI layouts with less or similar labor time. By using SWA, we have developed an R-DAC (resistive digital–analog converter) layout with a parameterized topology and various parameters, such as ~1 Gsps, 4~12-bit (upper segment type + lower R-2R type) R-DAC, and 1~3.3 V logic with 1~3.3 V_pp analog output. Full article

Multiple serial interfaces have emerged to meet system requirements across devices, ranging from slower-speed buses, such as I²C, to high throughput serial interfaces, like JESD204. To address the need for a medium-speed protocol and to resolve I²C shortcomings, the MIPI Alliance developed the I3C specification, which is a royalty-free next-generation version of I²C with new features and backward compatibility. Since the MIPI Alliance’s I3C work only includes the specifications, it depends on third-party vendors to develop their own cores according to the specifications. Only a few processing systems contain I3C Controllers, each with its own partial implementation of the specification, and there are no open-source controller cores. Thus, this work presents an open-source I3C Controller HDL framework that operates at the maximum specified SDR frequency and is compatible with the Linux kernel. Both the core and Linux kernel drivers are available under permissive open-source licenses. The solution is mostly aimed at development boards with Xilinx Zynq and Intel Cyclone SoC; nevertheless, the structure of the project allows it to be ported to other vendors and carriers. Full article

This review discusses the principle of typical bandgap reference circuits and analyzes their sources of errors. In order to provide readers with a clear perspective, we categorize the error sources into four types: (a) amplifier offset; (b) high-order nonlinearity of $V_{BE}$; (c) current mirror mismatch; and (d) other error sources. For these error sources, the most commonly used methods to reduce or minimize them to achieve high accuracy are summarized. Furthermore, this review explores sub-1V bandgap reference design techniques, addressing the increasing demand for low-power and low-voltage applications. Finally, we provide some suggestions for a future high-accuracy reference design. Full article

A low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for operation up to 5 GHz (Giga-Hertz). The proposed adder utilizes current-starved inverters to implement low-power operation while still maintaining signal integrity for high-frequency sine signals. The circuit uses a differential input and output structure to mitigate potential noise coupling onto any high-frequency signal pathways. The proposed solution differs from standard adder architectures by utilizing a fully analog signal processing design, accepting analog inputs while outputting an analog signal, and offering suitable functionality at Giga-Hertz level signals as compared to other relevant works. The simulated experimental results show the power consumption to be approximately 150 nW at 0.8 V supply with an input-referred noise of 6.091 nV/Hz at 5 GHz. Full article

Physically unclonable functions (PUFs) represent emerging cryptographic primitives that exploit the uncertainty of the CMOS manufacturing process as an entropy source for generating unique, random and stable keys. These devices can be potentially used in a wide variety of applications ranging from secret key generation, anti-counterfeiting, and low-cost authentications to advanced protocols such as oblivious transfer and key exchange. Unfortunately, guaranteeing adequate PUF stability is still challenging, thus often requiring post-silicon stability enhancement techniques. The latter help to contrast the raw sensitivity to on-chip noise and variations in the environmental conditions (i.e., voltage and temperature variations), but their area and energy costs are not always feasible for IoT devices that operate with constrained budgets. This pushes the demand for ever more stable, area- and energy-efficient solutions at design time. This review aims to provide an overview of several weak PUF solutions implemented in CMOS technology, discussing their performance and suitability for being employed in security applications. Full article

This paper proposes efficient implementations of robot audition systems, specifically focusing on deployments using HARK, an open-source software (OSS) platform designed for robot audition. Although robot audition systems are versatile and suitable for various scenarios, efficiently deploying them can be challenging due to their high computational demands and extensive processing times. For scenarios involving intensive high-dimensional data processing with large-scale microphone arrays, our generalizable GPU-based implementation significantly reduced processing time, enabling real-time Sound Source Localization (SSL) and Sound Source Separation (SSS) using a 60-channel microphone array across two distinct GPU platforms. Specifically, our implementation achieved speedups of 23.3× for SSL and 3.0× for SSS on a high-performance server equipped with an NVIDIA A100 80 GB GPU. Additionally, on the Jetson AGX Orin 32 GB, which represents embedded environments, it achieved speedups of 14.8× for SSL and 1.6× for SSS. For edge computing scenarios, we developed an adaptable FPGA-based implementation of HARK using High-Level Synthesis (HLS) on M-KUBOS, a Multi-Access Edge Computing (MEC) FPGA Multiprocessor System on a Chip (MPSoC) device. Utilizing an eight-channel microphone array, this implementation achieved a 1.2× speedup for SSL and a 1.1× speedup for SSS, along with a 1.1× improvement in overall energy efficiency. Full article

This paper presents a novel procedure for designing robust high-speed asynchronous DC-DC converter controllers. The method relies on the use of Workcraft©, a plugin-based development system designed to synthesize and validate the asynchronous control logic, ensuring hazard-free implementation even in the case of non-persistent input signals. The simulation results (using a proprietary 90 nm technology) showed a typical time response from input to output of less than 1.4 ns, which fits the fast response requirements for DC-DC converters. Full article

This work introduces a novel custom-designed 16-bit RISC-V processor, intended for educational purposes and for use in low-resource equipment. The implementation, despite providing registers of 16 bits, is based on RV32E RISC-V ISA, but with some key differences like a reduced instruction set that is optimized for embedded systems, the removal of floating-point instructions, reduced register count, and modified data types. These changes enable the processor to operate efficiently in resource-constrained environments while still maintaining assembly-level compatibility with the standard RISC-V architecture. The educational aspects of this project are also a key focus. By working on this project, students can gain hands-on experience with digital logic design, Verilog programming, and computer architecture. The project also includes tools and scripts to help students transform assembly code into binary format, making it easier for them to test and verify their designs. Additionally, the project’s open-source nature allows for collaboration and the sharing of knowledge among students and researchers worldwide. Full article

We have developed SWA: SoftWare for Analog design automation. Its commands can describe analog and mixed-signal (AMS) layouts and schematics to replace the graphic editor with a program reflecting the knowledge of design experts. Also, it is able to utilize variables to parameterize schematics and layouts to fulfill design needs. We programmed a 10b 1 GS/s DAC using SWA with 8.3 K lines of code, which is about 1/10 compared with conventional programs. The programmed DAC is configurable with multiple voltages and multiple resolutions from 4 to 12 bits. The DAC schematic and layout generation with DRC and LVS SWA API can be finished in about 1 min. Full article