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Nanomaterials
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Nanodevices—Technologies and Applications in Semiconductor Industry
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Nanodevices—Technologies and Applications in Semiconductor Industry

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: closed (31 October 2023) | Viewed by 3043

Special Issue Editors

Prof. Dr. Yiming Li

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Guest Editor
Institute of Communications Engineering, College of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
Interests: physics and technology of semiconductor device
Prof. Dr. Yao-Jen Lee

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Guest Editor
Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
Interests: semiconductor processes, devices, characterization, and applications
Prof. Dr. Seiji Samukawa

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Guest Editor
1. Department of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2. Institute of Fluid Science, Tohoku University, Sendai, Japan
Interests: nanofabrication; nanomaterials; green nanotechnology; process and implementations

Special Issue Information

Dear Colleagues,

Semiconductor technology is bounded with several material options, i.e., from metal (M), oxide (O), to semiconductor characteristics (S). One and foremost prioritized option among them is the field effect transistors (FET), so-called the MOSFET. With this attention, several material options have been of great interest to the semiconductor industry and are under intensive investigation. This can be achieved by supporting these material options and allowed with the new processing techniques to develop most efficient choices in device technologies.

The Special Issue of Nanomaterials is focused on emerging semiconductor device technology initiating from FETs, high-electron mobility transistors (HEMTs), tunneling FETs (TFETs), and so on through novel structural and material options through modeling as well as fabrication. It is worth pointing that the material choices in device technologies have been advanced with the latest research findings by tsmc, Taiwan (Semiconductor industry) and MIT, USA (highly reputed university), i.e., 2D FETs for 1nm technology node (IEDM, 2022). Having said that, the several novel implementations on device options is always beneficial and needed for the emerging technology nodes in semiconductor industry. Here, 3D stacked multi-bridge vertical channel complementary FET, so-called the CFET with gate-all-around has also been invented to continue Moore’s law. In addition, the processing technological equipment’s are also important to implement such futuristic designs with less processing defects. To do this, a method of manufacturing semiconductor devices and advanced processing equipment’s are needed. Therefore, this Special Issue focuses on,

  • CMOS platform device technologies (FETs & CFETs, HEMTs, TFETs, etc.);
  • Process module innovations and progresses in device technology;
  • Material engineering and implementations in device technology;
  • Device to circuit interactions and applications.

Prof. Dr. Yiming Li
Prof. Dr. Yao-Jen Lee
Prof. Dr. Seiji Samukawa
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Nanomaterials is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2900 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • semiconductor devices
  • semiconductor materials
  • nanofabrication
  • process techniques
  • heterogenous integration
  • hybrid process
  • modeling
  • simulation
  • optimization
  • nanoelectronic devices

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Published Papers (2 papers)

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Research

11 pages, 2369 KiB  
Article
Effect of Film Morphology on Electrical Conductivity of PEDOT:PSS
by Aditya Saha, Daisuke Ohori, Takahiko Sasaki, Keisuke Itoh, Ryuji Oshima and Seiji Samukawa
Nanomaterials 2024, 14(1), 95; https://doi.org/10.3390/nano14010095 - 29 Dec 2023
Cited by 2 | Viewed by 1543
Abstract
Commercially available formulations of the popular conductive polymer, poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) are aqueous dispersions that require the addition of secondary dopants such as dimethyl sulphoxide (DMSO) or ethylene glycol (EG) for fabricated films to have the desired levels of conductivity. CleviosTM F [...] Read more.
Commercially available formulations of the popular conductive polymer, poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) are aqueous dispersions that require the addition of secondary dopants such as dimethyl sulphoxide (DMSO) or ethylene glycol (EG) for fabricated films to have the desired levels of conductivity. CleviosTM F HC Solar, a formulation of PEDOT:PSS produced by Heraeus, GmbH, achieves over 500 S/cm without these secondary dopants. This work studies whether secondary dopants such as DMSO have any additional effect on this type of PEDOT:PSS. The temperature dependencies of the conductivity of F HC Solar spin-coated thin films measured using a four-probe method seem to exhibit different charge transport properties compared with secondary doped PH1000. Observations made using atomic force microscopy (AFM) show that different concentrations of DMSO affect the orientation of the PEDOT domains in the thin film. These morphological changes cause room temperature conductivity to reduce from 640 S/cm in pristine films to as low as 555 S/cm after adding 7 wt% of DMSO along the film. Such tuning may prove useful in future applications of PEDOT:PSS, such as nanoprobes, transistors and hybrid solar cells. Full article
(This article belongs to the Special Issue Nanodevices—Technologies and Applications in Semiconductor Industry)
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19 pages, 5655 KiB  
Article
The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length
by Priyanka Saha, Rudra Sankar Dhar, Swagat Nanda, Kuleen Kumar and Moath Alathbah
Nanomaterials 2023, 13(23), 3008; https://doi.org/10.3390/nano13233008 - 23 Nov 2023
Cited by 4 | Viewed by 1057
Abstract
The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET [...] Read more.
The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold current. In this work, we used stacked high-k dielectric materials in a TG n-FinFET with three fins and a 10 nm channel length, incorporating a three-layered strained silicon channel to determine the short-channel effects. Here, we replaced the gate oxide (SiO2) with a stacked gate oxide of 0.5 nm of SiO2 with a 0.5 nm effective oxide thickness of different high-k dielectric materials like Si3N4, Al2O3, ZrO2, and HfO2. It was found that the use of strained silicon and replacing only the SiO2 device with the stacked SiO2 and HfO2 device was more beneficial to obtain an optimized device with the least leakage and improved drive currents. Full article
(This article belongs to the Special Issue Nanodevices—Technologies and Applications in Semiconductor Industry)
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