Search Results (145)

Three-dimensional bulk fin-type field-effect transistors (FinFETs) have been the dominant devices since the sub-22 nm technology node. Electrical characteristics of scaled devices suffer from different process variation effects. Owing to the trapping and de-trapping of charge carriers, random interface traps (RITs) degrade device characteristics, and, to study this effect, this work investigates the impact of RITs on the DC/AC/RF characteristic fluctuations of FinFETs. Under high gate bias, the device screening effect suppresses large fluctuations induced by RITs. In relation to different densities of interface traps (D_it), fluctuations of short-channel effects, including potential barriers and current densities, are analyzed. Bulk FinFETs exhibit entirely different variability, despite having the same number of RITs. Potential barriers are significantly altered when devices with RITs are located near the source end. An analysis and a discussion of RIT-fluctuated gate capacitances, transconductances, cut-off, and 3-dB frequencies are provided. Under high D_it conditions, we observe ~146% variation in off-state current, ~26% in threshold voltage, and large fluctuations of ~107% and ~131% in gain and cut-off frequency, respectively. The effects of the random position of RITs on both AC and RF characteristic fluctuations are also discussed and designed in three different scenarios. Across all densities of interface traps, the device with RITs near the drain end exhibits relatively minimal fluctuations in gate capacitance, voltage gain, cut-off, and 3-dB frequencies. Full article

The paradigm shift from FinFET to gate-all-around nanosheet (GAA-NS) transistor architectures necessitates fundamental innovations in channel material engineering. This work addresses the critical challenge of pFET performance degradation in GAA-NS technologies through the development of an advanced selective etching process for strain-engineered SiGe channel formation. We present a systematic investigation of Si selective etching using CF₄/O₂/N₂ gas mixture in a remote plasma source reactor. It is demonstrated that the addition of N₂ to CF₄/O₂ plasmas significantly improves the selectivity of Si to SiGe (up to 58), by promoting NO* radical-induced passivation layer disruption on Si surfaces. Furthermore, an increase in the F:O ratio has been shown to mitigate stress-induced lateral micro-trenching (“Si-tip”), achieving near-zero tip length at high CF₄ flow (500 sccm) while retaining selectivity (>40). Transmission electron microscopy and energy-dispersive X-ray spectroscopy confirm the complete removal of the Si sacrificial layer with minimal SiGe channel loss, validating the process for high-performance SiGe GAA-NS FET integration. These findings provide critical insights into strain-engineered SiGe channel fabrication, enabling balanced NFET/PFET performance in next-generation semiconductor technologies. Full article

In this study, we propose a lateral power-reduced surface field FinFET (LPR-FinFET) to achieve high breakdown voltage and low on-resistance. We investigate the electric field distribution within the reduced surface field (RESURF) structure under reverse-biased conditions, as well as forward transfer and output characteristics using TCAD simulation. The proposed LPR-FinFET demonstrates a high breakdown voltage of 247 V and a low specific on-resistance of 0.255 mΩ·cm² with a high-power figure of merit of 239.3 MW/cm². The superior characteristics of our proposed LPR-FinFET show the potential for applications as a lateral power semiconductor using silicon-on-insulator (SOI) technology. Full article

The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications—such as speech recognition, facial recognition, and object detection—has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to significant challenges in terms of memory access time and power consumption. Compute-in-Memory (CIM) architectures have emerged as an alternative by executing computations directly within memory arrays, thereby reducing the expensive data transfer between memory and processor units. In this work, we present a 6T SRAM-based CIM architecture implemented using FinFET technology, aiming to reduce both power consumption and access delay. We explore and simulate three different SRAM cell structures—PLNA (P-Latch N-Access), NLPA (N-Latch P-Access), and SE (Single-Ended)—to assess their suitability for CIM operations. Compared to a reference 10T XNOR-based CIM design, our results show that the proposed structures achieve an average power consumption approximately 70% lower, along with significant delay reduction, without compromising functional integrity. A comparative analysis is presented to highlight the trade-offs between the three configurations, providing insights into their potential applications in low-power AI accelerator design. Full article

This study conducts a comprehensive examination of a GaN channel-based nanobiosensor featuring a dielectrically modulated trigate FinFET structure, incorporating both uniform and Gaussian channel doping. The proposed device incorporates a nanocavity structure situated beneath the gate region, intended for the analysis of diverse biomolecules in biosensing applications. The proposed biosensor employs HfO₂ as the gate dielectric, characterized by a dielectric constant of 25, leading to an enhanced switching ratio for the device. This study examines the electrical properties relevant to biomolecule identification, including the switching ratio, DIBL, threshold swing, threshold voltage, and transconductance. The sensitivity of these properties concerning the drain current is subsequently assessed. Enhanced sensitivity increases the likelihood of detecting biomolecules. The electrical property of a biomolecule is examined in the absence of another biomolecule within the cavity. The apparatus is designed to detect neutral biomolecules. Simultaneously, further investigational research has been undertaken regarding the linearity behavior of GAA FET, nanobiosensors, and dielectrically modulated TGFinFET. This study’s results have been compared with those of GaN-based FinFET and GaN SOI FinFET technologies. The data indicates approximately ∼103% and ∼42% improvements in I_OFF and Switching ratio, respectively, when compared to IRDS 2025. The nanobiosensor (GAA FET) demonstrates enhanced linear performance concerning higher-order voltage and current intercept points, including VIP2, VIP3, IIP3, and P1dB. Full article

This work presents a high-common-mode-rejection-ratio (CMRR) and high-gain FinFET-based bio-potential amplifier with a novel CMRR reduction technique. In this paper, a feedback buffer is used alongside a capacitively coupled chopper-stabilized circuit to reduce the common-mode signal gain, thus boosting the overall CMRR of the circuit. The conventional pseudoresistor in the feedback circuit is replaced with a tunable parallel-cell configuration of pseudoresistors to achieve high linearity. A chopper spike filter is used to mitigate spikes generated by switching activity. The mid-band gain of the chopper-stabilized amplifier is 42.6 dB, with a bandwidth in the range of 6.96 Hz to 621 Hz. The noise efficiency factor (NEF) of the chopper-stabilized amplifier is 6.1, and its power dissipation is 0.92 µW. The linearity of the parallel pseudoresistor cell is tested for different tuning voltages (V_tune) and various numbers of parallel pseudoresistor cells. The simulation results also demonstrate the pseudoresistor cell performance for different process corners and temperature changes. The low cut-off frequency is adjusted by varying the parameters of the parallel pseudoresistor cell. The CMRR of the chopper-stabilized amplifier, with and without the feedback buffer, is 106.9 dB and 100.3 dB, respectively. The feedback buffer also reduces the low cut-off frequency, demonstrating its multi-utility. The proposed circuit is compatible with bio-signal acquisition and processing. Additionally, a machine learning-based arrhythmia diagnosis model is presented using a convolutional neural network (CNN) + Long Short-Term Memory (LSTM) algorithm. For arrhythmia diagnosis using the CNN+LSTM algorithm, an accuracy of 99.12% and a mean square error (MSE) of 0.0273 were achieved. Full article

In this paper, a novel enhancement-mode β-Ga₂O₃-based FinFET structure with a gate formed by the NiO/β-Ga₂O₃ heterojunction named HJ-FinFET has been proposed, and the excellent performance of the device has also been demonstrated. The primary operational mechanism of this structure involves integrating p-type NiO on both sides of the fin-shaped channel, which forms p-n junctions with β-Ga₂O₃. The depletion regions thus generated are utilized to establish electron channels, enabling enhancement-mode operation. The reverse p-NiO/n-Ga₂O₃ heterojunction diode is integrated to reduce the reverse free-wheeling loss. Compared with the conventional devices, the threshold voltage of the HJ-FinFET is greatly improved, and normally off operation is realized, showing a positive threshold voltage of 2.14 V. Meanwhile, the simulated breakdown voltage of the HJ-FinFET reaches 2.65 kV with specific on-resistance (R_on,sp) of 2.48 mΩ·cm² and the power figure of merit (PFOM = BV²/R_on,sp) reaches 2840 MW/cm², respectively. In addition, the influence of the doping concentration of the heterojunction layer constituting the gate, the doping concentration of the drift layer, and the channel width on the electrical characteristics of the devices were focused on. This structure provides a feasible idea for high-performance β-Ga₂O₃-based FinFET. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

This work investigates the effects of radiation on FinFET-based full adders, which are crucial components of arithmetic units, particularly in aerospace and space applications. While FinFETs offer significant advantages, they remain susceptible to single-event transients (SETs) induced by radiation, which can cause computational errors. We assess three circuit-level mitigation techniques against SETs in FinFET adders: decoupling cells (DCELLs), transistor sizing (TS), and a combined approach incorporating both methods. Our results demonstrate that the most sensitive nodes and critical vectors in the adders vary depending on the mitigation strategy, underscoring their impact on overall radiation resilience. By analyzing these techniques alongside critical node evaluation, we identify their advantages and limitations, providing insights to enhance the robustness of FinFET-based processors in radiation-prone environments. Full article

As semiconductor devices approach the sub-10 nm technology node, the self-heating effect (SHE) induced by confined geometries (e.g., FinFETs and nanosheet FETs) has emerged as a critical bottleneck affecting both performance and reliability. This challenge has prompted extensive research efforts to develop advanced characterization methodologies to investigate this effect and its corresponding influence on the device’s reliability issues. In this paper, we propose reflection-based ultra-fast measurement techniques for the continuous monitoring of the self-heating effect in advanced MOSFETs. With this approach, the self-heating effect-induced degradation of transistor drain current and the real-time temperature change can be continuously captured using a digital phosphor oscilloscope on a nanosecond scale. The thermal time constant of 17 ns and the thermal resistance of 34,000 K/W have been extracted for the short channel transistors used in this study with the help of this new characterization method. This reflection-based method is useful for the fast extraction of the thermal time constant and thermal resistance and for the continuous monitoring of current degradation as well as the real-time temperature. Therefore, this new characterization method is beneficial for the evaluation of the self-heating effect in advanced ultra-scaled MOSFETs. Full article

With the continuous scaling of CMOS technology, stress engineering has become increasingly critical at advanced technology nodes, especially in tall and narrow FinFET structures. Asymmetric layout environments (such as dual-Fin structures or poly cuts) can introduce stress imbalance originating from shallow trench isolation (STI), which in turn affects device performance. In this study, TCAD simulations were performed on n-type FinFETs representative of the 10 nm technology node, with a physical gate length of 20 nm, to investigate the correlation between asymmetric stress and device drive current. As the Fin width decreases, the asymmetric stress from STI induces noticeable performance fluctuations, with the mobility enhancement under saturation bias reaching a maximum of 8.42% at W = 6 nm. Similarly, as the Fin body angle deviates from 90° and the Fin top narrows, with W_top = 6 nm and W_bottom = 8 nm, the mobility enhancement peaks at 7.65%. The simulation results confirm that STI-induced asymmetric stress has a significant impact on the Fin sidewall channel, while its effect on the top channel is minimal. To mitigate these effects, CESL stress engineering is proposed as an effective solution to amplify the top channel current, thereby reducing the influence of asymmetric stress on device performance. A CESL stress of 2.0 GPa is shown to improve device stability by approximately 20%. Full article

Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single-Event Upset (SEU). An SEU occurs when a charged particle ionizes a sensitive node in the circuit, causing a stored bit to flip from one logical state to its opposite. This study estimates the saturation cross-section for the 16 nm FinFET technology and compares it with results from a 28 nm planar CMOS technology. The experiments were conducted at the SIRAD facility of INFN Legnaro Laboratories (Italy). The device under test was irradiated with the ion sources ⁵⁸$Ni$ and ²⁸$Si$, both with different tilt angles, to assess the number of SEUs with different LET and range values. Additionally, the study evaluates the effectiveness of the radiation-hardened by design technique, specifically the Triple Modular Redundancy (TMR), which is a technique commonly employed in planar technologies. However, in this particular case study, TMR proved to be ineffective, and the reasons behind this limitation are analyzed along with potential improvements for future designs. Full article

In this paper, a novel approach to symbolic regression using Kolmogorov–Arnold Networks (KAN) for developing gray-box Simulation Program with Integrated Circuit Emphasis models of generic transistors is proposed. Unlike traditional black-box models, such as artificial neural networks, (ANN), the developed KAN-based model enhances interpretability by generating explicit mathematical expressions while maintaining high accuracy in device modeling. By combining the computational efficiency of neural network approaches with the transparency of formula-based modeling, the SPICE model generation is significantly accelerated, thereby improving the efficiency of the design technology co-optimization (DTCO) process. The experimental results demonstrate that the expressions derived from the KAN model accurately represent the current–voltage (I–V) characteristics of the BSIM–CMG compact model and provide nearly symmetric results. To further validate the effectiveness and versatility of the approach, we embedded the trained I–V KAN model into a 12 nm FinFET SPICE model and performed 11-stage ring oscillator (RO) simulations. The results indicate that the KAN-based SPICE model achieves accuracy comparable to the original 12 nm FinFET SPICE model, demonstrating its potential to streamline device modeling for advanced technology nodes. Full article

As semiconductor technology and process nodes advance, three-dimensional devices like FinFET and NSFET are increasingly becoming the primary choice, replacing planar MOSFETs. However, the complex manufacturing processes and high process sensitivity of three-dimensional devices at advanced process nodes inevitably cause significant deviations from the ideal structure during actual fabrication, leading to notable changes in their electrical characteristics. This paper investigates the impact of source/drain region height fluctuations caused by etching and epitaxial growth variations on the electrical characteristics of FinFET and NSFET devices, as well as their related circuits. The electrical characteristics when height variations occur in single and multiple electrodes indicate that, although NSFET and FinFET generally exhibit similar properties such as a decrease in the ON-state current when the source/drain height is reduced, the independent nature of the nanosheets in NSFET and the unidirectional conduction of Schottky contact resistance cause significant differences in their electrical characteristics. Additionally, the related circuit-level simulations show that height fluctuations in the source/drain regions of devices can significantly impact circuit characteristics, including voltage and delay, and in severe cases, they may even lead to circuit failure. Full article

Decoders are among the most fundamental components in digital circuit design. They are widely used in combinational logic to convert and route binary data, as well as in memory array logic, for decoding binary addresses that point to the memory locations to be accessed. Due to their extensive utilization, optimizing decoder cells can potentially yield perceivable improvements in a digital system. This paper introduces 3-Transistor Logic (3TL), a new design approach for the optimization of CMOS decoder circuits, which combines static CMOS, Transmission-Gate Logic, and Dual-Value Logic. A complete transistor-level design methodology is demonstrated for decoder sizes from $2\times 4$ up to $8\times 256$, using 15 nm FinFET technology. Furthermore, an extensive comparative analysis is conducted with transistor-level simulations, evaluating the new circuits against conventional static CMOS and other previously proposed designs. The results show that 3TL circuits offer the best overall performance in terms of active power consumption, standby power consumption, and delay, owing largely to the fact that they are designed with logic efficiency and the minimum possible number of transistors. Full article