Optimization of CMOS Decoders Using Three-Transistor Logic

Abstract

Decoders are among the most fundamental components in digital circuit design. They are widely used in combinational logic to convert and route binary data, as well as in memory array logic, for decoding binary addresses that point to the memory locations to be accessed. Due to their extensive utilization, optimizing decoder cells can potentially yield perceivable improvements in a digital system. This paper introduces 3-Transistor Logic (3TL), a new design approach for the optimization of CMOS decoder circuits, which combines static CMOS, Transmission-Gate Logic, and Dual-Value Logic. A complete transistor-level design methodology is demonstrated for decoder sizes from $2\times 4$ up to $8\times 256$, using 15 nm FinFET technology. Furthermore, an extensive comparative analysis is conducted with transistor-level simulations, evaluating the new circuits against conventional static CMOS and other previously proposed designs. The results show that 3TL circuits offer the best overall performance in terms of active power consumption, standby power consumption, and delay, owing largely to the fact that they are designed with logic efficiency and the minimum possible number of transistors.

1. Introduction

In digital systems, binary codes are used to represent discrete quantities of information. An n-bit binary code can represent up to 2ⁿ distinct elements of coded data. Decoders are combinational circuits that convert binary information from n input lines to a maximum of 2ⁿ unique output lines [1]. The most fundamental decoder variant is the $n\times m$ line decoder (where m = 2ⁿ), which generates the 2ⁿ minterms of n input variables. The truth table for an $n\times m$ line decoder with inputs IN_<n−1:0> and outputs D_<m−1:0> is illustrated in Figure 1a. As can be observed, each input combination triggers the assertion of a unique output. The circuit is characterized by the following boolean equations, expressed both in AND and NOR logic:

$$D_0={\overline{IN}}_{\mathrm{n}-1}·{\overline{IN}}_{\mathrm{n}-2}\dots {\overline{IN}}_2·{\overline{IN}}_1·{\overline{IN}}_0=\overline{I{N}_{\mathrm{n}-1}+I{N}_{\mathrm{n}-2}+·+I{N}_2+I{N}_1+I{N}_0}$$

$$D_1={\overline{IN}}_{\mathrm{n}-1}·{\overline{IN}}_{\mathrm{n}-2}\dots {\overline{IN}}_2·{\overline{IN}}_1·I{N}_0=\overline{I{N}_{\mathrm{n}-1}+I{N}_{\mathrm{n}-2}+·+I{N}_2+I{N}_1+{\overline{IN}}_0}$$

$$D_2={\overline{IN}}_{\mathrm{n}-1}·{\overline{IN}}_{\mathrm{n}-2}\dots {\overline{IN}}_2·I{N}_1·{\overline{IN}}_0=\overline{I{N}_{\mathrm{n}-1}+I{N}_{\mathrm{n}-2}+·+I{N}_2+{\overline{IN}}_1+I{N}_0}$$

$$\dots \dots$$

$$D_{\mathrm{m}-1}=I{N}_{\mathrm{n}-1}·I{N}_{\mathrm{n}-2}\dots I{N}_2·I{N}_1·I{N}_0=\overline{{\overline{IN}}_{\mathrm{n}-1}+{\overline{IN}}_{\mathrm{n}-2}+·+{\overline{IN}}_2+{\overline{IN}}_1+{\overline{IN}}_0}$$

It is also possible, and sometimes more convenient, to generate minterms in their complemented form with an inverting line decoder. Figure 1b illustrates the truth table of an inverting $n\times m$ line decoder with inputs IN_<n−1:0> and outputs $\overline{D}$_<m−1:0>, where each input combination deasserts a unique output. After complementing the above equations, the circuit’s functionality is expressed in OR and NAND logic. For convenience, the rest of this paper will refer to ‘line decoder’ and ‘inverting line decoder’ simply as ‘decoder’ and ‘inv-decoder’, respectively.

An $n\times m$ CMOS decoder can be conventionally built with m gates of n inputs each. For example, a 2 × 4 decoder can be built with four 2-input gates. This approach does not scale well, since an 8 × 256 decoder would require 256 8-input gates, resulting in a high transistor count and large stacks of transistors that swing very slowly. A better approach is to use the predecoding technique, where blocks of k input bits can be predecoded into 2^k lines that serve as input to the next-stage decoder or postdecoder. This results in a tree of multiple stages, effectively improving the logical effort and area of the whole circuit [2]. As will be demonstrated, the optimal way to design a static decoder is by using 2-input gates and fully utilizing the predecoding scheme.

The main scope of this work is to optimize CMOS decoders on the transistor level, in order to achieve minimum transistor count and improved power-delay performance. The new design scheme is based on FinFET devices and aimed at being suitable and efficient for modern technology nodes. The rest of this paper is organized as follows. Section 2 presents the new design methodology for CMOS decoders. Section 3 comprises an extensive, simulation-based comparative analysis at the transistor level, comparing the proposed circuits against the conventional implementation and previously proposed designs. Finally, Section 4 provides the conclusion of this work, including further information about the source material and discussion on future prospects.

2. Proposed Circuits

2.1. Three-Transistor Logic (3TL)

In conventional Static CMOS (SCMOS) logic, inputs are only applied to the gate terminals of transistors. Pass-Transistor Logic (PTL) allows for inputs to be applied to the source/drain terminals (or ‘fin’ terminals, in the case of FinFET devices) as well, essentially building switches to propagate signals. Taking advantage of this extra functionality can result in the implementation of functions with fewer transistors. Additionally, FinFETs generally have larger gate capacitance and smaller source/drain capacitance than planar MOSFET devices [3], potentially making PTL design more efficient in FinFET processes. This section presents the Three-Transistor Logic (3TL) scheme for CMOS decoders [4]. 3TL is a design methodology that combines SCMOS with 2 PTL logic families, namely Transmission Gate Logic (TGL) [5] and Dual Value Logic (DVL) [6]. Prior works used this combination for the design of 2 × 4 and 4 × 16 decoders with reduced transistor count and low power consumption, in a scheme called mixed logic [7,8]. The 3TL scheme extends and enhances the mixed-logic scheme, preserving only the original 2 × 4 cell while introducing a systematic approach for designing optimized decoders from 3 × 8 up to 8 × 256 with minimal transistor count.

Figure 2 illustrates the fundamental NOR2/NAND2 pass-transistor gates that are used by 3TL, with inputs A and B: (a) TGL NAND2, (b) TGL NOR2, (c) DVL NAND2, and (d) DVL NOR2. These implementations require three transistors (thus the 3TL naming), as opposed to four in SCMOS, and have full-swinging capability. However, they also require the complement of one or two of the inputs, so extra inverters may need to be used. As can be observed from Figure 2, A is only applied in transistor gate terminals, whereas B is applied in fin terminals (TGL) or both (DVL). They will be referred to as the ‘gate input’ and the ‘pass input’ of a 3TL gate, respectively. The transistors in the schematics are FinFETs, therefore transistor widths are quantized and annotated in number of fins (f_p, f_n). Let us define f_p = f_n = 2 as the minimum FinFET size for a single transistor stack, so k stacked transistors will have f_p/f_n = 2·k. In FinFET processes, p-type and n-type devices often have approximately equal driving strength due to the strained silicon feature [9]. This is also the case with the FinFET model that is used in this work, so sizing for both p-type field-effect transistors (pFETs) and n-type field-effect transistors (nFETs) will be the same.

A common issue with PTL is the degradation of signals when cascading multiple gates with non-restoring output. This problem is avoided in 3TL by making sure that pass inputs are always driven by inverters and not another NOR/NAND gate. By following this rule, the maximum size of a series stack is 2, regardless of the size and number of stages of the decoder. Transistors that are connected to V_DD or ground are unit-sized (2 fins). Single pass-transistors on DVL gates are double-sized (4 fins) because they are part of a series stack of two, after considering the inverter that drives the pass input. Transistors on transmission gates are both unit-sized, even though they are also part of a series stack of two, since they both work in parallel to pass the input signal, effectively reducing the resistance.

Figure 3 illustrates the gate symbols of the four types of inverters used by 3TL: (a) unit inverter, (b) double-sized (DS) inverter, (c) low-skew (LS) inverter, and (d) high-skew (HS) inverter. The unit inverter (f_p = f_n = 2) will be used to drive signals that are only used as gate inputs. The DS inverter has double the driving strength of the unit inverter (f_p = f_n = 4) and will be used to drive pass inputs of TGL gates. The LS inverter favors the high-to-low transition (f_p = 2, f_n = 4) and will be used to drive pass inputs of DVL NAND gates. Finally, the HS inverter favors the low-to-high transition (f_p = 4, f_n = 2) and will be used to drive pass inputs of DVL NOR gates.

2.2. Design of CMOS Decoders with 3TL

The first fundamental decoding cell of 3TL is the 2 × 4 decoder, which is illustrated in Figure 4a. Minterms D₀ and D₂ are implemented with TGL NOR2, using $\overline{IN}$₀ as the pass input, whereas D₁ and D₃ are implemented with DVL NOR2, using $\overline{IN}$₁ and IN₁ as the pass input, respectively. Two HS inverters are used to drive IN₁, $\overline{IN}$₁ and one DS inverter to drive $\overline{IN}$₀, from the external inputs in_0–1. This specific arrangement of logic gates and gate/pass inputs eliminates the need for an inverter to drive IN₀, resulting in a circuit with only 18 transistors, as opposed to the 24 required with SCMOS. A similar approach is used to implement the 2 × 4 inv-decoder, as illustrated in Figure 4c. Inverted minterms $\overline{D}$₀ and $\overline{D}$₂ are implemented with DVL NAND2, using IN₁ and $\overline{IN}$₁ as the pass input, respectively, whereas $\overline{D}$₁ and $\overline{D}$₃ are implemented with TGL NAND2, using $\overline{IN}$₀ as the pass input. Two LS inverters are used to drive IN₁, $\overline{IN}$₁ and one DS inverter to drive $\overline{IN}$₀, from the external inputs in_0–1. Again, this arrangement results in 18 transistors. In fact, 3TL provides four different implementations for each 2 × 4 decoding cell that results in a 18 T circuit [4].

Figure 4b illustrates the 3TL 3 × 8 decoder. A 2 × 4 inv-decoder is used to produce intermediate signals $\overline{X}$_0–3 for the second stage, which consists of eight DVL NOR2 gates that combine $\overline{X}$_i with IN₂. The pass inputs of the second stage are driven by IN₂ and $\overline{IN}$₂, which are driven by two HS inverters. Similarly, a 3 × 8 inv-decoder (Figure 4d) is implemented with a 2 × 4 decoder for the X_0–3 signals, a second stage of eight DVL NAND2 and two LS inverters for IN₂, $\overline{IN}$₂. The 3TL 3 × 8 circuits have 46 transistors, as opposed to the 60 required for SCMOS. It can be observed that the circuits in Figure 4 have a maximum stack of two transistors, since pass inputs are always driven by inverters of proper driving strength. The 2 × 4 and 3 × 8 circuits presented here are used for the predecoding stage of larger decoders, as will be shown in the next subsection.

TGL and DVL gates are useful for the predecoding cells that receive primary inputs. The next stages of the decoder, however, can be more efficiently built with SCMOS using a shared stack node structure, since there is no need for extra inverters to obtain any complementary signals. Figure 5 illustrates the 3TL postdecoder cells: (a) N-NOR and (b) N-NAND, where N = 4, 8, 16. The N-NOR cell comprises N SCMOS NOR gates, where each of them receives a different $\overline{X}$_i input (i= 0, 1, …, N−1) from the X-predecoder and all of them share a common $\overline{Y}$_j input from the Y-predecoder. A single pFET controlled by $\overline{Y}$_j can feed all the gates through a shared stack node, achieving minimum transistor count. The shared transistor still only needs to drive one gate output at a time, due to the 1-hot nature of the NOR array. Similarly, the N-NAND cell comprises N SCMOS NAND gates, where each of them receives a different X_i input from the X-predecoder and all of them share a common Y_j input from the Y-predecoder. A single nFET controlled by Y_j feeds all the gates through the shared stack node.

Larger 3TL decoders can be designed by combining the predecoding structure, the 2 × 4 and 3 × 8 (inv-)decoders of Figure 4, and the postdecoder cells of Figure 5. The result of this design methodology is shown in Figure 6, which illustrates the block diagrams of proposed 3TL decoders: (a) 4 × 16 decoder, (b) 5 × 32 decoder, (c) 6 × 64 decoder, (d) 7 × 128 decoder, (e) 8 × 256 decoder, (f) 4 × 16 inv-decoder, (g) 5 × 32 inv-decoder, (h) 6 × 64 inv-decoder, (i) 7 × 128 inv-decoder, and (j) 8 × 256 inv-decoder. It can be observed that when the two predecoders are of different sizes (e.g., in the case of 5 × 32 and 7 × 128), the smaller one has to be used for Y_j ($\overline{Y}$_j), so that larger sets of gates can be grouped together with shared transistors at the final stage. Additionally, each logic stage has a maximum stack of two transistors, thus the main disadvantage of using PTL (signal degradation when cascading) is avoided. In general, the proposed design scheme combines the best characteristics of SCMOS and PTL and achieves the minimum possible transistor count to implement the decoders.

3. Comparative Evaluation

This section comprises a transistor-level comparison among various static decoder designs, including the proposed 3TL circuits, the conventional SCMOS implementation, and various static decoder designs from the relevant literature. Section 3.1 presents the circuits that are examined and compared. Section 3.2 describes the setup and methodology for the simulations. Finally, Section 3.3 presents and analyzes the results.

3.1. Examined Circuits

The following evaluation procedure consists of two parts. In the first part, decoders from 2 × 4 up to 8 × 256 are implemented with both 3TL and SCMOS using the predecoding structure. The SCMOS designs use the conventional two-input NOR/NAND gates with four transistors. Both a standard (‘3TL’/‘SCMOS’) and a buffered version (‘buf-3TL’/‘buf-SCMOS’) of the decoders is used; the buffered version consists of an inverting $n\times m$ decoder with unit inverters driving the outputs, thus the last stage has AND gates instead of NAND. Buffering the outputs with inverters is common in address decoders of memory arrays, which have to drive a large capacitive load [2]. A SCMOS decoder can also be built by using AND logic exclusively, i.e alternating NAND gates and inverters; this version will be referred to as ‘AND-SCMOS’ and will also be evaluated. It has been common practice in planar MOSFET processes to use subsequent stages of AND logic instead of alternating NOR/NAND, since this approach provides the lowest logical effort in SCMOS [2,10]. Nonetheless, there might be no benefit from using this approach in FinFET processes with balanced P/N driving strength.

The second part includes some alternative static decoder designs proposed in the literature: the ‘AND3’ decoder [11] (4 × 16), the ‘Block’ decoder [12] (4 × 16 and 5 × 32), the ‘2-level’ decoder [13] (4 × 16 and 5 × 32) and the ‘Replica’ decoder [14] (5 × 32). All these are compared to their 3TL counterparts. In general, all the examined decoders can be separated into two categories: the unbuffered ones that drive the output signals with NOR logic and the buffered ones that drive their outputs with inverters. The unbuffered set includes 3TL, SCMOS, Block, two-level, and Replica, whereas the buffered set includes buf-3TL, buf-SCMOS, AND-SCMOS, and AND3. For fair comparison, performance metrics will mostly be evaluated with respect to circuits of the same category. A more detailed presentation and analysis of all these circuits can be found in [4].

3.2. Simulation Setup

All examined circuits are implemented with the 15 nm FinFET model from FreePDK15 [15], which is based on the 14 nm Predictive Technology Model for Multi-Gate devices (PTM-MG) [16]. An independent review of predictive technology models has found FreePDK15 to be reasonably consistent with industry trends [9]; more details on FreePDK15 can be found online at [17]. The 3TL circuits are implemented as shown in the figures of Section 2. The rest of the circuits are implemented using the same sizing methodology, i.e., k stacked transistors have f_p/f_n = 2·k, where two is the minimum FinFET size. All their inputs are driven by a pair of unit inverters, since SCMOS requires both the normal and complementary value of all inputs. The tool used for the simulations is Synopsys HSpice. All circuits are simulated under the same conditions, i.e., nominal voltage (V_DD = 0.8 V) and typical operating temperature (T = 70 °C). All decoder outputs are loaded with C_L = 1.0 fF. Three performance metrics are evaluated: active power consumption, standby power consumption, and max delay. For active power simulations, the bit input frequency is F = 10 GHz, whereas for standby power simulations, the circuits are simulated with all inputs stable at logic 0. Since no switching activity occurs in this case, all dissipated power is due to leakage. Finally, delay is measured between the points in time that input signals and corresponding output signals are at 50% of the switching event (V_DD/2 = 0.4 V). The worst case delay is found with iterative simulations for each examined circuit.

3.3. Results and Discussion

Comparison of decoders from 2 × 4 up to 8 × 256 with predecoding structure is summarized in

Table 1. 3TL vs. SCMOS: transistor count.

Decoder	2 × 4	3 × 8	4 × 16	5 × 32	6 × 64	7 × 128	8 × 256
3TL	18	46	88	164	292	526	960
SCMOS	24	60	112	212	376	684	1248
buf-3TL	26	62	120	228	420	782	1472
buf-SCMOS	32	76	144	276	504	940	1760
AND-SCMOS	32	84	160	308	552	1012	1856

(transistor count),

Table 2. 3TL vs. SCMOS: active power consumption in microwatts.

Decoder	2 × 4	3 × 8	4 × 16	5 × 32	6 × 64	7 × 128	8 × 256
3TL	13.4	26.4	38.5	55.2	75.5	98.7	129.7
SCMOS	15.5	31.6	47.3	69.7	98.8	130.6	180.3
buf-3TL	15.9	30.0	43.6	62.8	89.3	122.2	173.6
buf-SCMOS	18.5	36.0	52.7	77.5	111.8	153.1	223.0
AND-SCMOS	18.5	39.5	58.7	89.5	128.3	173.1	248.2

(active power consumption in μW),

Table 3. 3TL vs. SCMOS: standby power consumption in microwatts.

Decoder	2 × 4	3 × 8	4 × 16	5 × 32	6 × 64	7 × 128	8 × 256
3TL	1.2	2.3	3.6	6.3	8.9	12.5	16.1
SCMOS	1.3	2.8	4.7	7.8	11.8	18.3	28.2
buf-3TL	1.4	3.5	6.1	10.5	17.6	30.8	54.9
buf-SCMOS	1.7	3.8	6.7	11.9	20.5	36.3	65.3
AND-SCMOS	1.7	4.2	7.5	13.6	23.1	40.4	71.0

(standby power consumption in μW), and

Table 4. 3TL vs. SCMOS: max delay in picoseconds.

Decoder	2 × 4	3 × 8	4 × 16	5 × 32	6 × 64	7 × 128	8 × 256
3TL	5.0	7.6	8.4	10.9	13.2	14.7	17.4
SCMOS	6.7	8.5	9.9	11.8	14.1	16.7	19.5
buf-3TL	6.3	8.8	9.4	11.9	14.1	16.0	18.5
buf-SCMOS	7.8	9.8	11.1	12.9	15.2	17.7	20.3
AND-SCMOS	7.8	10.9	12.2	15.2	17.7	20.5	23.5

(max delay in ps). According to these tables, 3TL decoders achieve a 21.4–25.0% improvement in transistor count, a 13.5–28.0% improvement in active power, a 7.7–43.0% improvement in standby power, and a 6.4–25.4% decrease in delay, compared to respective SCMOS decoders. Furthermore, buf-3TL decoders achieve a 16.4–18.8% improvement in transistor count, 14.1–22.2% in active power, 7.9–17.6% in standby power, and 7.2–19.2% in delay, compared to respective buf-SCMOS decoders. In comparison with the AND-SCMOS decoders, the corresponding improvements are 18.8–26.2%, 14.1–30.4%, 16.7–23.8% and 19.2–23.0%. The results are also illustrated in figures to provide a better comparative overview and visualization; Figure 7 contains the results for ‘small’ decoders (2 × 4 up to 5 × 32) and Figure 8 contains the results for ‘large’ decoders (5 × 32 up to 8 × 256).

In general, it can be concluded that 3TL has lower transistor count, power consumption, and delay than SCMOS for all decoder sizes. Notably, buf-3TL has lower active power consumption even than unbuffered SCMOS. Buffered designs have significantly higher standby power, because inverters are the main source of leakage in digital circuits; the leakage through two or more series transistors is significantly reduced due to the stack effect [18]. As a final note, AND logic performed worse than NOR/NAND logic for SCMOS. Implementing decoders with AND gates might have been beneficial in planar CMOS processes. However, in FinFET processes with balanced P/N driving strength, NOR gates are almost as efficient as NAND gates, thus there is no benefit in using AND logic; unless there is a large capacitive load to be driven, the extra inverters between stages only increase delay and power consumption.

The comparison of 4 × 16 and 5 × 32 decoders is summarized in

Table 5. Comparison of 4 × 16 decoders.

4 × 16 Decoder	3TL	Block [12]	2-Level [13]	Buf-3TL	AND3 [11]
Transistors	88	132	128	120	160
Active Power (μW)	38.5	53.1	58.6	43.6	73.9
Standby Power (μW)	3.6	5.7	5.1	6.1	6.4
Max Delay (ps)	8.4	11.6	13.0	9.4	20.0

and

Table 6. Comparison of 5 × 32 decoders.

5 × 32 Decoder	3TL	Block [12]	2-Level [13]	Replica [14]
Transistors	164	274	276	262
Active Power (μW)	55.2	90.0	127.9	82.2
Standby Power (μW)	6.3	11.1	9.1	10.8
Max Delay (ps)	10.9	15.8	23.5	11.9

, respectively; the results are also illustrated in Figure 9 and Figure 10. Regarding 4 × 16 decoders, 3TL achieves a 33.3–61.4% improvement in transistor count, 27.5–34.3% in active power, 29.4–36.8% in standby power, and 27.6–35.4% in delay, compared to the rest of the unbuffered designs. Additionally, buf-3TL achieves a 25.0% improvement in transistor count, 41.0% in active power, 4.7% in standby power, and 53.0% in delay, compared to the AND3 design. Regarding 5 × 32 decoders, 3TL achieves a 37.4–40.6% improvement in transistor count, 32.8–56.8% in active power, 30.8–43.2% in standby power, and 8.4–53.6% in delay, compared to all other circuits. To sum up, all alternative decoding schemes from the literature perform worse than the proposed ones and the standard SCMOS with predecoding, in all aspects. The AND gates, especially with more than two inputs, are inefficient; the Block scheme has too many stages and gates; the two-level scheme uses large and slow gates; and the Replica scheme uses too many extra inverters. According to our results, using the predecoding structure in conjunction with alternating NOR/NAND two-input logic yields the optimal results. On top of that, using 3TL brings a further reduction in transistor count, power, and delay.

4. Conclusions and Future Prospects

This paper presented the 3TL scheme for the optimization of CMOS decoders. The proposed design approach was analyzed and implemented at the transistor level using predictive 15 nm FinFET technology. The results demonstrated that, compared to conventional designs, 3TL achieves superior performance in terms of transistor count, active/standby power, and delay. The source material for this work is available in [4], which provides a comprehensive overview of 3TL design principles and methodology. It includes a detailed analysis of the multiple 3TL cell variants, along with the 3TL matrix layout technique for physical-level design. Furthermore, it presents the design of decoders with enable input and address decoders for memory arrays with emphasis on low area and leakage reduction.

As a future prospect, 3TL schematic and layout schemes can be extended to other combinational circuits that include some form of decoding functionality or are primarily composed of NOR/NAND logic. Potential applications include other types of binary decoders, multiplexers, demultiplexers, encoders, and parallel-prefix trees. Furthermore, 3TL can be incorporated into standard-cell libraries and whole memory blocks (such as SRAM), in order to assess the impact of replacing SCMOS with 3TL at the digital system level, in terms of overall performance and area efficiency. The increased complexity of 3TL circuits compared to SCMOS introduces new design considerations. Further investigation is required to evaluate the trade-offs between optimization and complexity, especially in large-scale implementations where design overhead and layout constraints become increasingly critical.