Search Results (96)

Microphysiological systems (MPSs) have emerged as alternatives to animal testing in drug development, following the FDA Modernization Act 2.0. Double-layer channel-type MPS chips with porous membranes are widely used for modeling various organs, including the intestines, blood–brain barrier, renal tubules, and lungs. However, these chips faced challenges owing to optical interference caused by light scattering from the porous membrane, which hinders cell observation. Trans-epithelial electrical resistance (TEER) measurement offers a non-invasive method for assessing barrier integrity in these chips. However, existing electrode-integrated MPS chips for TEER measurement have non-uniform current densities, leading to compromised measurement accuracy. Additionally, chips made from polydimethylsiloxane have been associated with drug absorption issues. This study developed an electrode-integrated MPS chip for TEER measurement with a uniform current distribution and minimal drug absorption. Through a finite element method simulation, electrode patterns were optimized and incorporated into a polyethylene terephthalate (PET)-based chip. The device was fabricated by laminating PET films, porous membranes, and patterned gold electrodes. The chip’s performance was evaluated using a perfused Caco-2 intestinal model. TEER levels increased and peaked on day 5 when cells formed a monolayer, and then they decreased with the development of villi-like structures. Concurrently, capacitance increased, indicating microvilli formation. Exposure to staurosporine resulted in a dose-dependent reduction in TEER, which was validated by immunostaining, indicating a disruption of the tight junction. This study presents a TEER measurement MPS platform with a uniform current density and reduced drug absorption, thereby enhancing TEER measurement reliability. This system effectively monitors barrier integrity and drug responses, demonstrating its potential for non-animal drug-testing applications. Full article

High-frequency (h. f.) harmonic distortion (HD) of advanced SiGe heterojunction bipolar transistor (HBT)-based power cells (PwCs), featuring optimized metallization interconnections between individual HBTs, was investigated. Single tone input power (P_in) excitations at 1, 2, 5, and 10 GHz frequencies were employed. The output power (P_out) of the fundamental tone and its harmonics were analyzed in both the frequency and time domains. A rapid increase in the third harmonic of P_out was observed at input powers exceeding −8 dBm for a fundamental frequency of 10 GHz in two different PwC technologies. This increase in the third harmonic was analyzed in terms of nonlinear current waveforms, the nonlinearity of the HBT p-n junction diffusion capacitances, substrate current behavior versus P_in, and avalanche multiplication current. To assess the RF power performance of the PwCs, scalar and vectorial load-pull (LP) measurements were conducted and analyzed. Under matched conditions, the SiGe PwCs demonstrated good linearity, particularly at high frequencies. The key power performance of the PwCs was measured and simulated as follows: input power 1 dB compression point (P_{in_1dB}) of −3 dBm, transducer power gain (G_T) of 15 dB, and power added efficiency (PAE) of 50% at 30 GHz. All measured data were corroborated with simulations using the compact model HiCuM L2. Full article

High efficiency and high power density are key targets in modern power conversion. Operating power converters at high switching frequencies enables the use of smaller passive components, which, in turn, facilitate achieving high power density. However, the concurrent increase in switching frequency and power density leads to efficiency and overheating issues. Soft switching techniques are typically employed to minimize switching losses and significantly improve efficiency by reducing power losses. However, the hysteresis behavior of the power electronics devices’ output capacitance, C_OSS, is the cause of regrettable losses in Super-Junction (SJ) MOSFETs, SiC MOSFETs, and GaN HEMTs, which are usually adopted in soft switching-based conversion schemes. This paper reviews the techniques for measuring hysteresis traces and power losses, as well as the understanding of the phenomenon to identify current research trends and open problems. A few studies have reported that GaN HEMTs tend to exhibit the lowest hysteresis losses, while Si superjunction (SJ) MOSFETs often show the highest. However, this conclusion cannot be generalized by comparing the results from different works because they are typically made across devices with different (when the information is reported) breakdown voltages, on-state resistances, die sizes, and test conditions. Moreover, some recent investigations using advanced TCAD simulations have demonstrated that newer Si-SJ MOSFETs employing trench-filling epitaxial growth can achieve significantly reduced hysteresis losses. Similarly, while multiple studies confirm that hysteresis losses increase with increasing dv/dt and decreasing temperature, the extent of this dependence varies significantly with device structure and test methodology. This difficulty in obtaining a general conclusion is due to the lack of proper figures of merit that account for hysteresis losses, making it problematic to evaluate the suitability of different devices in resonant converters. This problem highlights the primary current challenge, which is the development of a standard and automated method for characterizing C_OSS hysteresis. Consequently, significant research effort must be invested in addressing this main challenge and the other challenges described in this study to enable power electronics researchers and practitioners to develop resonant converters properly. Full article

The objective of the proposed work was to investigate the electrical performance of a 250 µm-thick 4H-SiC p-n junction detector after irradiation with DT neutrons (14.1 MeV energy) at high temperature (500 °C). The results showed that the current–voltage (I-V) characteristics of the unirradiated SiC detector were ideal, with an ideality factor close to 1.5. A high electron mobility (µ_n) and built-in voltage (V_bi) were also observed. Additionally, the leakage current remained very low in the temperature range of 298–523 K. High-temperature irradiation caused a deviation from ideal behaviour, leading to an increase in the ideality factor, decreases in the µ_n and V_bi values, and a significant rise in the leakage current. Studying the capacitance–voltage (C-V) characteristics, it was observed that neutron irradiation induced reductions in both Al-doped (p⁺-type) and N-doped (n⁻-type) 4H-SiC carrier concentrations. A comprehensive investigation of the deep defect states and impurities was carried out using deep-level transient spectroscopy (DLTS) in the temperature range of 85–750 K. In particular, high-temperature neutron irradiation influenced the behaviours of both the Z_1/2 and EH_6/7 traps, which were related to carbon interstitials, silicon vacancies, or anti-site pairs. Full article

The high switching speed of SiC MOSFETs can induce resonance between parasitic inductors and capacitors, owing to rapid changes in current and voltage, leading to excessive crosstalk parasitic oscillation. This can increase SiC MOSFETs’ gate oxide voltage stress, reducing their service life and even directly leading to gate overvoltage failure. However, there is still a lack of investigations of active control of gate driving in systematic converters because crosstalk parasitic oscillation, indicated by high frequencies in MHz, is challenging to control in a power converter with gate voltage stability and high switching speed. This paper investigates an active gate drive based on negative feedback to fully drive SiC MOSFETs with high efficiency and stable gate voltage to exploit the advantages of high dv/dt over 20 V/ns in SiC MOSFETs and further realize the miniaturization of power conversion systems. It first investigates a dynamic model of SiC MOSFET gate-interfered oscillation in parallel application derived from a circuit with equivalent junction capacitance in power devices. Then, the operating principle of the Negative Feedback Active Gate Drive (NFAGD) application strategy for parallel SiC MOSFETs is demonstrated. Finally, the experiment verifies the proposed strategy’s effectiveness in suppressing crosstalk parasitic oscillation in parallel SiC MOSFETs, and an 8 kW synchronous buck converter prototype is built to verify the NFAGD’s performance in systematic converter applications. Full article

The contact interfaces of a press-pack insulated-gate bipolar transistor (PP-IGBT) module under fluctuating thermal stress will undergo minor friction and mutual sliding during service, which results in damage to the contact surface and a decline in the thermal performance of the contact interface. Therefore, the temperature inside the module will continue to increase, leading to eventual failure. In this work, a life prediction method based on thermal resistance degradation within a PP-IGBT module is established. The junction temperature can be determined via power loss and a resistance-capacitance (RC) thermal network model, and a life prediction model of the PP-IGBT module is developed based on thermal resistance degradation. The method considers the service quality under power cycling conditions and the influence of the self-accelerating effect of damage accumulation at the contact interface of the PP-IGBT module on fatigue life. The experimental results verify that the proposed PP-IGBT module life prediction method can effectively predict service life under power cycling conditions. Full article

This paper focuses on the modeling challenges of a multi-cell heterojunction bipolar transistor (HBT) used in radio frequency (RF) power amplifiers and proposes an innovative linear small-signal modeling method. Based on devices with an emitter size of 3 μm × 40 μm × 2–6 (emitter width × emitter length × emitter index-cell number), an equivalent circuit model including peripheral parasitic parameters is constructed by analyzing device layout characteristics in response to additional parasitic effects introduced by the multi-cell structure. A step-by-step parameter extraction method is used, with particular attention paid to the correction of saturated current parameters, temperature coefficients, thermal resistance correction, and the optimization of junction capacitance parameters based on the capacitance ratio relationship. After the extraction of parasitic parameters, the input and output reflection coefficient errors of the model under zero-bias conditions are below 1.66% in the 0.7–25 GHz frequency band. The accuracy of this model is significantly improved compared to the directly parallel single-cell model. The power simulation results match the measured results very well at frequencies of 2.6 GHz and 3.5 GHz. This modeling method significantly improves the model accuracy of multi-cell HBT devices in RF circuit design and provides an effective tool for high-power amplifier optimization. Full article

Antimony selenide (Sb₂Se₃) is an Earth-abundant and non-toxic material that stands out as a promising absorber for the fabrication of thin film solar cells. Despite significant advancements in recent years, all the devices reported in the literature exhibit open-circuit voltages well below the theoretical value. Identifying the factors contributing to this low voltage is an essential step for increasing the efficiency beyond the recently attained 10% milestone and moving closer to the theoretical limit. In this paper, we present the results of an in-depth analysis of a Sb₂Se₃ solar cell in the common superstrate configuration. By making use of current density–voltage characteristic as a function of both temperature and wavelength, capacitance–voltage measurements, and admittance spectroscopy, we ascribe the low open-circuit voltage to the presence of a potential barrier within the absorber material near the junction interface Furthermore, it was observed that the junction behavior in the dark and under illumination changes, which is compatible with the presence of deep electronic levels connected with intrinsic point defects. Full article

This study proposes a method for estimating the junction temperature of power semiconductors, particularly IGBTs (Insulated Gate Bipolar Transistors) and diodes. Traditional temperature measurement methods using NTC (Negative Temperature Coefficient) sensors have limitations in reflecting dynamic conditions in real time, as temperature changes take time to reach the sensors. To address this, this study proposes a junction temperature estimation method using RC curve fitting and a thermal impedance model. This model represents the thermal behavior of IGBTs and diodes using a Foster thermal network that considers the resistance and capacitance of the heat transfer path. In particular, transient temperature estimation considering thermal coupling enables the prediction of temperature changes in IGBTs and diodes. To verify the proposed temperature estimation method, experiments were conducted to build the model based on data measured with an infrared thermal camera and NTC sensors. The model’s estimated results were compared with actual values across 25 operating regions, achieving a maximum MAE (Mean Absolute Error) of 2.26 °C. A comparative analysis of first-, second-, third-, and fourth-order Foster networks revealed that, while higher orders improve accuracy, gains beyond the second order are minimal relative to computational demands. This study contributes to enhancing not only the reliability of power semiconductor modules but also minimizing the temperature margin for inverters by estimating the junction temperature with better dynamic performance than that achieved by NTC sensors. Full article

The paper investigates and addresses the “dead time” of a synchronous step-down converter implemented with P-channel and N-channel transistors. The transistors are controlled by a single driver, and “dead time” is implemented with external circuits and Schottky diodes. The influence of the Schottky diode capacitance on “dead time” is considered. Mathematical expressions were derived, showing the ratio of the value of this capacitance to the input capacitance of the transistor and the influence of this ratio on the shape of the leading edge of the pulse for switching on the transistor. The results of computer simulations are given for different ratios of the two capacitances. It was found that the capacitance of the Schottky diode must be much lower than the input capacitance of the transistor. The results of the mathematical description and computer simulations were used to select a suitable transistor and Schottky diode and are applied in the subsequent practical implementation. Conclusions and recommendations were made for a synchronous step-down converter, as well as for other cases of implementing “dead time” in the manner considered. Full article

Semiconductor radiation detectors usually use a specific signal conditioning circuit, ensuring the required detection system parameters. This paper details the noise properties of specific input stages in photoreceivers that detect various types of radiation. For this purpose, the popular silicon PIN photodiode (BPW34) and two different types of low-noise operational amplifiers (AD797A and ADA4625-1) were used. In the presented experiments, noise measurements were provided for voltage and transimpedance amplifiers operating in input stages, comparing their noise and bandwidths. This made it possible to obtain results for bipolar junction transistor (BJT)- and field-effect transistor (FET)-based input stages of circuity, cooperating directly with a photodiode. Analyzing the obtained characteristics and considering the photodiode operation mode, it is evident that the transimpedance amplifier and photoconductive mode should be considered a typical first-choice solution. In some cases, the performances, such as bandwidth and noise, may be similar to those of voltage. Nevertheless, the bias method used in TIA and feedback compensation can also affect the resulting output noise spectral characteristics due to the photodiode and other capacitances existing in the circuit. In the case of a high transimpedance, the FET-based op-amps ensure lower output noise than the BJT-based ones due to the significantly lower current noise. The simple radiation detector with two-channel differential TIA was also proposed and tested based on the results obtained. Full article

This work develops a novel compact Silicon-Controlled Rectifier (SCR) model incorporating self-heating effects, extending the conventional Ebers–Moll (E–M) framework for Bipolar Junction Transistors (BJTs) by comprehensively integrating parasitic effects. The temperature dependence of critical device parameters, including junction capacitances, emitter resistances, and saturation currents, is systematically characterized to accurately predict the device’s electrical behavior under Electrostatic Discharge (ESD) stress. Furthermore, a self-heating modeling approach is introduced based on the SCR layout characteristics. The impact of self-heating on SCR transient response was verified by comparing simulation results with measurements from SCR devices fabricated in a 0.18 µm Bipolar-CMOS-DMOS (BCD) process. Comparative analysis demonstrates superior accuracy over existing models. The proposed SCR model includes a complete definition of parameters and electrical relationships, ensuring compatibility with various Electronic Design Automation (EDA) platforms. Full article

This study investigates the fabrication and characterization of flexible PN diode devices using phosphorus- and boron-doped carbon nanotube (CNT) paper, also known as Buckypaper (BP). The BP substrate is fabricated from multi-walled carbon nanotubes (MWCNTs) and doped with phosphorus and boron to form N-type and P-type semiconductors, respectively. Various experimental techniques, including Raman spectroscopy, Hall effect measurements, and scanning electron microscopy (SEM), are employed to analyze the properties of the doped BP. The results reveal that the current-voltage (I-V) and capacitance-voltage (C-V) characteristics preliminarily exhibit the basic electrical properties of a diode after doping with P-type and N-type carriers. Subsequently, optimized vertical stacking combined with parallel electrode configurations for the BP diode devices demonstrates that vertical series stacking gradually enhances the thermoelectric voltage, while horizontal parallel connections approximately scale up the thermoelectric and photovoltaic voltages proportionally. The findings underscore the critical role of creating heterogeneously doped CNT-paper PN junction electric fields in improving the performance of carbon-based semiconductor devices. Furthermore, we demonstrate that these directionally oriented energy devices, when stacked, can form modular systems with enhanced efficiency. This work highlights the potential of flexible carbon material-based devices for advanced thermoelectric and photovoltaic applications. Full article

The placenta plays a critical role in nutrient and oxygen exchange during pregnancy, yet the effects of medicinal drugs on this selective barrier remain poorly understood. To overcome this, this study presents a cost-effective bioimpedance spectroscopy (BIS) system to assess tight junction integrity and monolayer formation in BeWo b30 cells, a widely used model of the multinucleated maternal–fetal exchange surface of the placental barrier. Cells were cultured on collagen-coated porous membranes and treated with forskolin to induce controlled syncytialization. Electrical impedance was measured using an entry level impedance analyzer, while immunofluorescence staining was used to confirm monolayer formation and syncytialization. The measurements and staining confirmed the formation of a confluent monolayer on day 4. In fact, the electrical resistance tripled for treated samples indicating a more electrically restrictive barrier. This resistance remained constant for treated samples reflecting the intact barrier’s integrity over the next 3 days. The measurements show that, on day 4, the electrical capacitance of the cells decreased for the treated samples as opposed to the untreated samples. This reflects that the surface area of the BeWo b30 cells decreased when the samples were treated with forskolin. Finally, a COMSOL model was developed to explore the effects of electrode positioning, depth, and distance on TEER measurements, explaining discrepancies in the literature. In fact, there was a substantial 97% and 39.4% difference in the obtained TEER values. This study demonstrates the AD2 device’s feasibility for monitoring placental barrier integrity and emphasizes the need for standardized setups for comparable results. The system can hence be used to analyze drug effects and nutrient transfer across the placental barrier. Full article

A novel planar silicon carbide (SiC) MOSFET integrated with both MOS-channel diode (MCD) and junction barrier Schottky diode (JBS) on the same chip (MCD-JBSFET) is proposed and investigated through Technology Computer-Aided Design (TCAD) simulations in this paper. The proposed device features the lowest turn-on voltage and the best current conduction capability under the reverse-biased conditions, allowing it to achieve the same reverse conduction capability with fewer MCDs compared to conventional MOSFET with MCD structures (MCDFET). This reduction in the number of MCDs enables more channels to operate under forward-biased conditions, thereby improving power density. Compared to a conventional MOSFET integrated with JBS structure (JBSFET), the reverse current in the MCD-JBSFET flows through both the MCD and JBS, which suppresses the peak lattice temperature at Schottky contact and enhances the high-temperature robustness, especially under surge current conditions. In addition, the split-gate structure in the proposed structure optimizes the reverse capacitance and the figure of merit R_on,sp × Q_g by factors of 0.65 and 2.15, respectively. Finally, the switching losses are reduced by 40.2%, indicating the suitability of MCD-JBSFET for high-frequency and high-current applications. Full article