Search Results (66)

This article presents a low ripple, high voltage-conversion-ratio (VCR = 6), two-stage step-up converter intended for power-burst applications. The first boost stage raises the battery voltage to a maximum of 35 V, while the subsequent low dropout regulator (LDO) stage suppresses the ripple of the final output. Unlike conventional structures in which control circuits operate above a ground-referenced rail, the proposed shunt-current-reusing technique places most of the control circuits within a narrow floating dropout region (V_DROP) between the boost output (V_BST) and the LDO output (V_OUT), thereby achieving nearly 100% current efficiency through current recycling. Adaptive adjustment of V_DROP (0.5 V at light load and 0.65 V at heavy load) balances output ripple against the loss of the LDO stage. Consequently, the proposed converter achieves both high efficiency (>85%) and low ripple (<2 mV) over a load range from 200 μA to 100 mA, with a peak efficiency of 90.4% at a 20 mA load. Hysteretic control of the boost stage combined with the high bandwidth (BW = 1.2 MHz) of the LDO stage yields a fast transient response (<20 μs). The proposed techniques address the requirements of applications that demand high intermittent power bursts (>1 W) at high supply voltage (>20 V) while maintaining low quiescent current consumption under most load conditions (<10 mA), as exemplified by light detection and ranging (LiDAR), haptic sensors, and micro electromechanical system (MEMS) drivers. Full article

This paper introduces a fully integrated gate-pole-dominant low-dropout regulator (LDO) that eliminates the need for external capacitors while sustaining high power-supply rejection (PSR) over a broad load current range. A loop-gain booster (LGB) is proposed to maintain the DC operating point of the error amplifier output at its optimal value, thereby preserving a high unity-gain frequency (UGF) even as the load current varies from zero to 200 mA. The parallel signal paths within the LGB inherently produce a left-half-plane (LHP) zero, which cancels one of the poles within the UGF of the feedback loop and guarantees robust stability under diverse operating conditions. Fabricated in a 40 nm CMOS technology, the prototype occupies only 0.008 mm² with a 4 pF on-chip compensation capacitor. The proposed LDO achieves a PSR of −72 dB at 1 MHz and −40 dB at 10 MHz when I_L = 200 mA and V_DO = 0.1 V, and maintains a PSR better than −78 dB at 1 MHz and −42 dB at 10 MHz when I_L = 1 mA and V_DO = 0.1 V. The LGB-enhanced regulator achieves excellent load and line regulation figures of 29 μV/mA and 0.75 mV/V, while the LGB itself consumes merely 7 μA out of a total quiescent current of 108 μA. Full article

This paper presents a flipped-voltage-follower low-dropout regulator (FVF-LDO) for power supply rejection enhancement and low-power operation in CMOS transimpedance amplifiers for optical receiver applications. The proposed FVF-LDO ensures high stability and reliable regulation over a wide range of load conditions by employing a flipped-voltage follower for fast local feedback and improved power supply rejection, while a super-source follower enhances the transient response through increased current-driving capability. A bandgap reference with a 3-bit trimming DAC is adopted to compensate process variations and support stable LDO operations, achieving a temperature coefficient of 19.6 ppm/°C over a wide range of −25 °C to 125 °C. The FVF-LDO exhibits a 101 mV undershoot under a 100 µA-to-10 mA load step with a 100 ns edge time. When applied to an optoelectronic inverter-based active-feedback transimpedance amplifier (TIA), the regulated supply improves the power supply rejection ratio (PSRR) from −6 dB to −38.3 dB. The proposed optoelectronic TIA realized in a 180 nm CMOS process achieves 67 dBΩ transimpedance gain, 869 MHz bandwidth, 66 dB dynamic range, 6.68 pA/√Hz input-referred noise current spectral density, and 4.68 mW power consumption from a single 1.8 V supply. The proposed TIA chip occupies a core area of 940 × 162 µm². Full article

A new approach to end-to-end power delivery for increasingly sought-after hierarchical power delivery units (PDUs) is presented, improving the power efficiency of portable systems. The benefits of the technique are demonstrated through a PDU comprising multiple DC–DC converters, such as low-dropout regulators (LDOs), and the support of heterogeneous loads. A properly tailored Q-algorithm is combined with power gating to manage the power supplied by a multi-level PDU. The effectiveness of the proposed method is evaluated via a realistic PDU for different combinations of loads. The learning-based technique yields up to 13% higher total end-to-end power efficiency in the case of similar loads by utilizing four available LDOs compared to the case of a single LDO, which supports the same span of loads. Moreover, the proposed method improves power efficiency by up to 5% in the case of heterogeneous loads when compared to other autonomous state-of-the-art power management units. Full article

High-performance low dropout regulator (LDO) chips are core components that provide clean power for high-precision sensors, radio frequency (RF) circuits, low noise amplifiers and other noise-sensitive circuits. In the reported literature, the designed LDO chip has advantages in certain parameters, but it cannot meet all the requirements of a high power supply rejection ratio (PSRR), low output noise and low standby current at the same time, which makes the high-end applications of LDOs greatly limited. In this paper, an LDO chip with high PSRR, low output noise and low standby current has been designed and fabricated. By increasing the loop gain, introducing an improved feedforward path, and adopting isolated power supply, the PSRR of the LDO at different frequency bands is greatly improved. By optimizing the design of the error amplifier (EA) and adding a low-pass filter to filter out the reference noise, the output voltage noise of the LDO is reduced. Within the depletion process and an optimized reference structure, the standby power consumption of the LDO is reduced without damaging the output voltage accuracy. The chip is taped out with SMIC’s 0.18 μm/5 V/BCD process. The measured PSRR of the chip is as high as 95dB at a frequency of 1 kHz, and the high-frequency (1 MHz) PSRR is above 45 dB. The amplitude of integrated output noise is below 5.4 μVrms within the frequency range of 10 Hz to 100 KHz. When the load current is zero, the measured standby current is less than 400 nA. The test results indicate that the chip has excellent performance in terms of PSRR, output noise and standby power consumption. Full article

Low-dropout regulators (LDOs) are critical modules in aerospace electronic systems. However, they are susceptible to single-event transient effects, which can impact the stability of the power system. Currently, almost all aerospace LDOs employ analog design to achieve robust output current characteristics. In this paper, three LDO architectures including analog LDO, digital LDO, and hybrid LDO are investigated, and a novel multi-loop hybrid LDO featuring analog proportional and digital integral control is proposed. A load detection module is introduced to allow the analog loop to operate independently under light-load conditions, thereby eliminating limit cycle oscillation (LCO) issues. In addition, a falling edge detection module is implemented to accelerate the transient response of the circuit. Three LDO circuits are designed using a 28 nm CMOS process, and their single-event transient responses are compared using double-exponential current pulse simulations. The results show that the proposed hybrid LDO exhibits the strongest transient response and best immunity to single-event effects under heavy-load conditions, achieving an efficiency of 99.975%. Full article

Temperature is a crucial indicator in monitoring industrial operations. Two-wire temperature transmitters, known for their precise measurements, are extensively used in sectors like crude oil extraction, refining, and fine chemicals. These transmitters can handle a maximum input voltage of 36 V and output a current signal up to 20 mA, enhancing resistance to electromagnetic interference and line noise while improving system compatibility and safety. In contrast, traditional low-dropout linear regulators (LDOs) typically have an input voltage below 6 V and suffer from limitations such as low power supply rejection ratio (PSRR), inadequate current driving capability, and significant temperature drift. This paper proposes a wide-input-range LDO with enhanced output accuracy and digital trimming, designed using the 180 nm BCD process. It incorporates dynamic mismatch compensation, digital trimming, and a strong-drive buffer, achieving a broad input voltage range and high PSRR with minimal temperature drift. The input voltage spans 6 V to 60 V, the output voltage is 1.8 V, and the PSRR reaches 124.5 dB. Across a temperature range of −40 °C to 130 °C, the maximum output voltage error is only 0.3%. This makes it highly suitable for high-precision circuit power supplies in industrial process control. Full article

Improving the transient response performance is a critical challenge in low-dropout regulator (LDO) design. This paper proposes a novel on-chip capacitor-less LDO based on substrate technology implemented in an SMIC (Semiconductor Manufacturing International Corporation) 0.18 μm CMOS (complementary metal oxide semiconductor technology) process. Central to this innovation is a fast response loop between the PMOS driver’s body and gate, which leverages the body effect to enhance driver control without complex bulk-driven techniques. The proposed LDO achieves a quiescent current of 4.5 μA, an efficiency of $88\%$, an overshoot/undershoot of $12\mathrm{mV}/22\mathrm{mV}$, and a settling time of 1.2 μs. The comparative analysis confirms that this structure increases the maximum load current and reduces the loop response time relative to those for conventional LDOs. These results validate a significant improvement in the transient performance, marking an important advance in integrated voltage regulator technology. Full article

This work proposes a methodology for the automated sizing of transistors in analog integrated circuits, based on a modular and hierarchical representation of the circuit. The methodology combines structured design techniques and systematic design flow to generate a hierarchy of simplified macromodels that define their specifications locally and are interconnected with other macromodels or transistor-level primitive blocks. These primitive blocks can be described using symbolic models or pre-characterized data from look-up tables (LUTs). The symbolic representation of the system is obtained using Modified Nodal Analysis (MNA), and the exploration of each block is performed using local design spaces constrained by top-level specifications. The methodology is validated through the design of low dropout voltage regulators (LDOs) for DC-DC integrated power systems using open-source tools and three process design kits: Sky130A, GF180MCU, and IHP-SG13G2. Results show that the methodology allows the exploration of several topologies and technologies, demonstrating its versatility and modularity, which are key aspects in analog design. Full article

This paper proposes a hybrid energy-harvesting chip that utilizes both radio-frequency (RF) energy and solar energy for low-power applications and extended service life. The key contributions include a wide input power range, a compact chip area, and a high maximum power conversion efficiency (PCE). Solar energy is a clean and readily available source. The hybrid energy harvesting system has gained popularity by combining RF and solar energy to improve overall energy availability and efficiency. The proposed chip comprises a matching network, rectifier, charge pump, DC combiner, overvoltage protection circuit, and low-dropout voltage regulator (LDO). The matching network ensures maximum power delivery from the antenna to the rectifier. The rectifier circuit utilizes a cross-coupled differential drive rectifier to convert radio frequency energy into DC voltage, incorporating boosting functionality. In addition, a solar harvester is employed to provide an additional energy source to extend service time and stabilize the output by combining it with the radio-frequency source using a DC combiner. The overvoltage protection circuit safeguards against high voltage passing from the DC combiner to the LDO. Finally, the LDO facilitates the production of a stable output voltage. The entire circuit is simulated using the Taiwan Semiconductor Manufacturing Company 0.18 µm 1P6M complementary metal–oxide–semiconductor standard process developed by the Taiwan Semiconductor Research Institute. The simulation results indicated a rectifier conversion efficiency of approximately 41.6% for the proposed radio-frequency-energy-harvesting system. It can operate with power levels ranging from −1 to 20 dBm, and the rectifier circuit’s output voltage is within the range of 1.7–1.8 V. A 0.2 W monocrystalline silicon solar panel (70 × 30 mm²) was used to generate a supplied voltage of 1 V. The overvoltage protection circuit limited the output voltage to 3.6 V. Finally, the LDO yielded a stable output voltage of 3.3 V. Full article

Conventional successive approximation recursive (SAR) control hybrid low-dropout regulators (LDOs) have problems such as significant reverse overshoot and discontinuous current switching. Based on trajectory optimization in the phase plane, this paper presented initial/last-state-correlated SAR control to address the aforementioned issues. Firstly, the operating principles of the conventional SAR controller are elucidated, which is depicted by a finite state machine (FSM). Secondly, large reverse overshoot and discontinuous current switching of the SAR control hybrid LDO are analyzed through the phase plane trajectory. Then, the initial/last-state SAR control is proposed by FSM to optimize the trajectory, thereby reducing the reverse overshoot and smoothing current switching. Finally, a series of design challenges of the initial/last-state-correlated SAR control are discussed. Implemented at 1.11 mm × 0.567 mm in a 180 nm bipolar-CMOS-DMOS (BCD) process, under a 0.1 nF output capacitor, the 6-bit hybrid LDO in this paper achieved an output voltage overshoot of 76 mV and a transient time of 18.8 μs at a 152 mA load current change. The experimental result demonstrates the distinct dynamic response advantages of the initial/last-state SAR control. Full article

The technological advances in internet of things (IoT) devices have raised the demand for cost-efficient and sustainable energy sources. Piezoelectric energy harvesters (PEHs) are promising low-cost and eco-friendly energy sources but require robust power management circuits (PMCs) for voltage conversion and regulation. This work presents a complementary metal–oxide–semiconductor (CMOS)-based PMC, integrating a reconfigurable AC-DC rectifier and a low-dropout (LDO) voltage regulator designed using 0.18 µm Taiwan semiconductor manufacturing company (TSMC) CMOS technology. This design includes an intermediate coupling stage to reduce voltage drop and improve the transfer efficiency of the PMC. In addition, we develop numerical simulations of the PMC performance, achieving a voltage conversion efficiency (VCE) between 72.8% and 43.21% using input voltages from 0.7 V to 2.8 V with a 50 kΩ load resistance. Compared to previous designs, the proposed circuit demonstrates improved stability, reduced area (66.28 mm²), and extended operating voltage range, allowing its potential application for ultra-low-power IoT nodes. This PMC contributes to the development of autonomous systems with reduced battery dependency and enhanced sustainability. Full article

This article introduces an innovative, fully integrated low-dropout (LDO) specifically designed for low-power applications, capable of handling a wide range of load currents. By employing dynamic biasing to enhance noise performance, the LDO shows a noise equal to 14 $\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{Hz}}$ at f < 1 kHz. The LDO demonstrates remarkable efficiency with a load regulation (LDR) of 3.8 mV/A and a line regulation (LNR) of 0.71 mV/V. It boasts a rapid settling time of 1 $\mathsf{\mu }$s during load transitions up to 100 mA and a minimal quiescent current of 5 $\mathsf{\mu }$A. The regulator consistently provides a 2.6 V output for input voltages between 2.8 V and 4.8 V, with a dropout voltage of 67 mV, supporting load currents from 0 mA to 100 mA over a temperature range of −25 °C to +125 °C. The design is based on a 150 nm CMOS process to ensure high sensitivity and high performance, making it an ideal choice for battery-operated systems. Full article

A programmable gain amplifier (PGA) is commonly used to optimize the input dynamic range of high-performance systems such as headphones and biomedical sensors. But PGA is rather sensitive to electromagnetic interference (EMI), which limits the precision of these systems. Many capacitor-less low-dropout regulator (LDO) schemes with high power supply rejection have been proposed to act as the independent power supply for PGA, which consumes additional power and area. This paper proposed a PGA with a high power supply rejection ratio (PSRR) and low power consumption, which serves as the analog front-end amplifier in the 20-bit sigma-delta ADC. The PGA is a two-stage amplifier with hybrid compensation. The first stage is the recycling folded cascode amplifier with the gain-boost technique, while the second stage is the class-AB output stage. The PGA was implemented in the 0.18 μm CMOS technology and achieved a 9.44 MHz unity-gain bandwidth (UGBW) and a 57.8° phase margin when driving the capacitor of 5.9 pF. An optimum figure-of-merit (FoM) value of 905.67 has been achieved with the proposed PGA. As the front-end amplifier of a high-precision ADC, it delivers a DC gain of 162.1 dB, the equivalent input noise voltage of 301.6 nV and an offset voltage of 1.61 μV. Within the frequency range below 60 MHz, the measured PSRR of ADC is below −70 dB with an effective number of bits (ENOB), namely 20 bits. Full article

Digital low-dropout (LDO) regulators are popular in research today as compact power supply solutions. This paper provides a unique approach to analyze digital LDO feedback mechanics and stability, to reduce voltage ripple and extend operating speed over the state-of-the-art. A novel error-subtracting counter is proposed to exponentially improve the response time of any digital LDO, to keep the loop stable outside the typical operating limits, and to increase power-supply rejection (PSR). This leverages the fact that digital LDOs are fundamentally one-bit relaxation oscillators in steady-state. Theory and simulations show how the analog-to-digital (ADC) and digital-to-analog converters (DAC) in these systems affect stability. When compromised, a digital LDO produces uncontrolled sub-clock oscillations at the output that the proposed error-subtracting counter removes. Full article