Advances in System-on-Chip Design

Dear Colleagues,

The increasing complexity of modern system-on-chip (SoC) architectures is limited by several contrasting factors such as limited power budgets, design costs, and security concerns. On one hand, the end of Dennard’s scaling limits the number of transistors that can be active at the same time. Thus, designers are promoting specialization, resulting in heterogeneous architectures composed of several processing elements (e.g., general-purpose processors and dedicated hardware accelerators). On the other hand, the scalability of interconnection systems may limit the number of processing elements that can be integrated. Therefore, designers are enforcing regularity by promoting the use of network-on-chip (NoC) interconnection subsystems. This allows the integration of components designed independently.

Heterogeneous SoC architecture can bring significant benefits in terms of performance and energy efficiency. Hence, they are becoming extremely popular in academia and industry. However, there are still several open challenges, especially concerning efficient memory design and protection from cybersecurity threats, which must be addressed by the designers.

The main aim of this Special Issue is to seek high-quality submissions that address emerging challenges in complex SoC architectures, such as the design of specialized accelerators, their integration with pre-existing components, the design of scalable and efficient memory architectures, and the identification of additional vulnerabilities arising from the integration of several different components. The topics of interest include but are not limited to:

• Novel SoC architectures and design methodologies;
• Layout- and energy-driven SoC architectures;
• Design space exploration methods for SoC design;
• High power density dower electronic systems;
• High-level synthesis and hardware/software co-design methodologies;
• Efficient memory architectures for scalable and distributed SoC architectures.;
• Hardware security and hardware-assisted security in SoC architectures.

Dr. Christian Pilato
Guest Editor

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