Novel Interleaved Converter with Extra-High Voltage Gain to Process Low-Voltage Renewable-Energy Generation

Abstract

This paper presents a novel interleaved converter (NIC) with extra-high voltage gain to process the power of low-voltage renewable-energy generators such as photovoltaic (PV) panel, wind turbine, and fuel cells. The NIC can boost a low input voltage to a much higher voltage level to inject renewable energy to DC bus for grid applications. Since the NIC has two circuit branches in parallel at frond end to share input current, it is suitable for high power applications. In addition, the NIC is controlled in an interleaving pattern, which has the advantages that the NIC has lower input current ripple, and the frequency of the ripple is twice the switching frequency. Two coupled inductors and two switched capacitors are incorporated to achieve a much higher voltage gain than conventional high step-up converters. The proposed NIC has intrinsic features such as leakage energy totally recycling and low voltage stress on power semiconductor. Thorough theoretical analysis and key parameter design are presented in this paper. A prototype is built for practical measurements to validate the proposed NIC.

1. Introduction

Since fossil fuels will be depleted in the next decades, development of green energy power generation systems becomes urgent. Among renewable energy generation systems, photovoltaic (PV), wind turbine, energy storage systems, and fuel cells attract a lot of attention [1,2,3,4]. Nevertheless, low output voltage is their common shortcoming, especially in grid connection or electric vehicle (EV) applications. Therefore, a step-up converter to achieve high voltage gain is required. Conventional boost-type converters, like boost, buck-boost, and flyback, are able to step-up input voltage. However, in order to meet high-voltage gain requirements, they have to operate in heavy-duty ratio or adopt a high turns ratio transformer, which will decrease the conversion efficiency dramatically. Cascading more boost-type converters can avoid the above problem but issues of volume, cost, and efficiency emerge. Therefore, the high step-up DC/DC converter is the current design trend.

High step-up converters can be mainly classified into two categories: single-stage and interleaved structure. Single-stage topology incorporates coupled inductors and/or switched capacitors to complete high voltage gain. Even though its input voltage is boosted, a large magnitude of input current ripple occurs, limiting the converter power rating significantly [5,6,7,8]. The interleaved converter has the ability of suppressing input current ripple by means of adding a parallel current path, which is a better choice for high power applications [9,10,11]. However, the conventional interleaved converters have voltage gain limitation, which confines their applications in grid-tied systems. To overcome the aforementioned disadvantages, various high step-up interleaved converters were proposed in [12,13,14,15,16]; nevertheless, the shortcomings of lower voltage gain, higher voltage stress, and large component count still exist. An interleaved Boost converter combining voltage doubler is introduced in [12], while a coupled inductor is examined in [13]. In order to achieve high voltage gain, the converters in [12,13] have to be operated at heavy-duty ratio or adopt a magnetic transform with high turns ratio, which results in low conversion efficiency or high voltage stress. Even though Lai et al. [14] proposed another high step-up converter, incorporating coupled inductor and switched capacitor, into an interleaved Boost configuration, the converter intrinsically has the demerits of higher voltage stress and sophisticated structure. An interleaved step-up converter with winding-cross-coupled inductors and voltage multiplier cells is presented in [15]. This converter is composed of eight semiconductor devices and two three-winding coupled inductors. That is, a large number of power devices must be used. Tseng et al. [16] utilized the characteristics of forward, flyback, and interleaved converters to boost input voltage, but voltage gain still is limited.

This paper proposes a novel interleaved converter (NIC), which can accomplish a high voltage conversion ratio and is capable of processing low voltage, high power distributed resources. Its power stage is depicted in Figure 1. The proposed NIC mainly includes three parts: one interleaved-boost converter cell and two voltage multipliers. The interleaved-Boost converter cell is in charge of lowering input current ripple, increasing current rating, and primarily stepping input voltage. The two voltage multipliers can further stack up voltage level. The series voltage of the three parts determines the magnitude of output voltage. Since the proposed converter only uses two coupled inductors, three capacitors, four diodes, and two active power switches, it has a lower component count and a simple circuit structure. The advantages of the proposed NIC are summarized as follows:

(1)

The NIC can suppress input current ripple.

(2)

The energy stored in leakage inductance can be recycled.

(3)

The voltage stress of the semiconductor device is low enough so that a power switch with lower on-state resistance and smaller parasitic capacitance can be chosen.

(4)

As compared with a conventional interleaved high step-up converter, the proposed NIC can achieve a much higher voltage gain under the same power component count.

2. Operation Principle of the Proposed Converter

In Figure 1, L_m1 and L_m2 denote the magnetizing inductances of the coupled inductors T₁ and T₂, respectively. The L_k1 and L_k2 represent the primary leakage inductances of T₁ and T₂, in turn, while L_k3 stands for the total leakage inductance at the secondary windings of both coupled inductors. Turns ratios of primary to secondary of T₁ and T₂ are denoted as n₁ and n₂, respectively. C₁, C₂, and C₃ are the main capacitors employed in the circuit. It is supposed that the NIC operates in continuous conduction mode (CCM) and the two active switches S₁ and S₂ are controlled in interleaved manner. Accordingly, the operation of the NIC can be divided into ten operation modes over one switching cycle. The corresponding equivalents are illustrated in Figure 2, while Figure 3 depicts key waveforms. Analysis of the proposed NIC begins by making these assumptions:

(1)

All parasitic capacitances and internal resistances are neglected. Moreover, all diodes are ideal.

(2)

The voltages across capacitors C₁, C₂, C₃, and C_o are time-invariant.

(3)

Magnetizing inductances, L_m1 and L_m2, are much larger than the leakage inductances L_lk1, L_lk2 and L_lk3.

(4)

The switching period is T_s. Both switches are closed for time DT_s and open for (1 − D)T_s.

Mode 1 (t₀–t₁) (Figure 2a): This mode is the initial mode of the all operation procedures. During this time interval, both active switches S₁ and S₂ are closed. Diodes D₁, D₃ and D_o are in reverse-bias, but D₂ is forward-biased. Input voltage V_in is across the primaries of T₁ and T₂ directly. Then, the current flowing through S₂ starts increasing linearly from zero, while the switch current i_S1, having an initial value determined by the end of Mode 10, also increases linearly. In addition, the energy remained in L_k3 will be recycled to C₂ via D₂. At the time that the diode current i_D2 drops to zero, and this mode ends.

Mode 2 (t₁–t₂) (Figure 2b): During this time interval, active switches S₁ and S₂ are still closed, and V_in remains across the two coupled inductors_. Thus, the current i_Lm1 and i_Lm2 are continuously increasing. In this mode, the current flowing through leakage inductances i_lk1 and i_lk2 are equal to magnetizing-inductance currents i_Lm1 and i_Lm2, respectively. This mode ends when the switch S₁ is turned off.

Mode 3 (t₂–t₃) (Figure 2c): In this mode, S₂ remains in on state but S₁ becomes off. Diodes D₂, D₃ and D_o are reversely-biased but D₁ is in forward-bias. The V_in, L_m1, L_k1 and C₂ dump energy to L_k3 and C₁ via D₁ and S₂, so the current flowing through D₁ and S₂ increases. This mode finishes when D₃ becomes forward-biased and L_k3 starts to release energy.

Mode 4 (t₃–t₄) (Figure 2d): Over the whole interval of Mode 4, S₂ is still kept in on state while S₁ in off state. The D₁ remains forward-biased and D₃ becomes closed. Meanwhile, both diodes D₂ and D_o continue the off status. Magnetizing-inductance L_m1 pumps energy to C₃ via the coupled inductor. Capacitor C₁ is charged continuously, the circuit behavior of which is the same as in the previous mode. When the leakage-inductance L_k1 releases over its stored energy, i_D1 will drop to zero. That is, diode D₁ becomes reversely-biased and this mode ends.

Mode 5 (t₄–t₅) (Figure 2e): During this time interval, S₂ is still closed and S₁ is open. Diodes D₁, D₂ and D_o are reversely-biased but D₃ is in forward-bias. V_in and L_m1 supply energy to C₃ simultaneously by the T₁ and T₂ in turn. This mode finishes as S₁ is turned on.

Mode 6 (t₅–t₆) (Figure 2f): During this mode, S₁ and S₂ are both in on state. Diodes D₁, D₂ and D_o are off, but D₃ is on. L_m1 starts to draw energy from V_in. The stored energy in L_k3 will releases to C₃ through D₃. This mode sustains until i_D3 decreases to zero.

Mode 7 (t₆–t₇) (Figure 2g): During this time interval, S₁ and S₂ are both in on state, but D₁, D₂, D₃ and D_o are all reversely-biased. Since the primaries of the two coupled inductors are in parallel, V_in will supply energy to L_m1, L_m2, L_k1 and L_k2. Therefore, i_Lm1 and i_Lm2 will increase linearly, which are identical to i_S1 and i_S2, respectively. This mode is ended when S₂ is turned off.

Mode 8 (t₇–t₈) (Figure 2h): During this time interval, S₁ remains in on state, but S₂ in off state. D₁, D₂ and D₃ are off, but D_o is on. The L_m2 starts to release its stored energy so that the current flowing through L_m2 decays. Meanwhile, the current i_lk3 increases. The input V_in and the voltages across L_m2, L_k2, C₁, and C₃ will be stacked up to supply C_o. This mode terminates when L_k3 starts to charge C₂.

Mode 9 (t₈–t₉) (Figure 2i): In this mode, S₁ is still closed and S₂ is open. The V_in will charge C₂ via coupled inductor T₁; meanwhile, the energy stored in L_m2 will also be transferred to the secondary of T₂ for powering C₂. Therefore, i_Lm2 drops and C_o keeps on charging. In Mode 9, the energy in L_k2 is recycled to the output. This mode ends as i_lk2 falls to zero.

Mode 10 (t₉–t₁₀) (Figure 2j): The diode D_o will become reversely biased when i_lk2 drops to zero. In Mode 10, S₁ proceeds with on-state conducting and S₂ remains in off state. With respect to diode status, the diodes D₁, D₃ and D_o are in reverse-bias and D₂ is still in on state. The V_in and L_m2 will forward energy to C₂ through the coupled inductors T₁ and T₂, respectively. This mode ends when S₂ is turned on again, and then the operation returns to Mode 1.

3. Voltage Gain Derivation

Voltage gain is the most important characteristic of a high step-up converter. As the analysis in Section 2 shows, the switched capacitors C₁ and C₃ have the benefit of voltage stacking for achieving extra-high voltage gain. This section focuses on the voltage gain derivation of the proposed NIC. For high power applications, the converter is designed in CCM. Assumptions made in Section 2 are also adopted for simplifying the derivation. Furthermore, the coupling coefficients of the coupled inductors are both supposed at unity; that is, there is no leakage inductance.

According to the description for Mode 4 in Section 2, C₁ is charged by V_in, C₂, T₁, and T₂, whereas C₃ is charged by the two coupled inductors. Referring to Mode 9 in Section 2, if the leakage inductances are ignored, the output port is supplied by V_in, T₁, T₂, C₁, and C₃. Hence, to determine the voltage gain, V_o/V_in, the relationships of V_C1, V_C2 and V_C3 in terms of V_in have to be found in advance.

3.1. The Ratio of V_C3 to V_in

As S₁ is closed, V_in will supply energy to L_m1. After an on-time interval DT_s, the change in i_Lm1 can be estimated as:

$${\left(\Delta i_{\mathrm{Lm}1}\right)}_{\mathrm{on}}=\frac{V_{\mathrm{in}}D{T}_{\mathrm{s}}}{L_{\mathrm{m}1}}$$

(1)

In the opposite switch statuses, that is, S₁ off and S₂ on, the energy stored in L_m1 will be transferred to the secondary of the coupled inductor T₁ and then be forwarded to C₃ by the loop of N₂-N₁₂-D₃-C₂. In addition, the source voltage V_in also supplies energy to C₃ via T₂. By Kirchhoff's voltage law (KVL) and from the closed loop N₂-N₁₂-D₃-C₂, it can be found that:

$$n_2{V}_{\mathrm{Lm}2}-n_1{V}_{\mathrm{Lm}1}-V_{C3}=0$$

(2)

Since voltage across L_m2 is V_in, rewriting Equation (2) becomes:

$$V_{\mathrm{Lm}1}=\frac{n{V}_{\mathrm{in}}-V_{\mathrm{C}3}}{n}=L_{\mathrm{m}1}\frac{\mathrm{d}{i}_{\mathrm{Lm}1}}{\mathrm{d}t}$$

(3)

From Equation (3), the current change in L_m1 after a switch-off interval (1 − D)T_s, is found by:

$${\left(\Delta i_{\mathrm{Lm}1}\right)}_{\mathrm{off}}=\frac{\left(n{V}_{\mathrm{in}}-V_{C3}\right)\left(1-D\right)T_{\mathrm{s}}}{n{L}_{\mathrm{m}1}}$$

(4)

In steady state, over one switching cycle the net change of inductor current i_Lm1 is zero. That is:

$$n{V}_{\mathrm{in}}D{T}_{\mathrm{s}}+\left(n{V}_{\mathrm{in}}-V_{\mathrm{C}3}\right)\left(1-D\right)T_{\mathrm{s}}=0$$

(5)

Rearranging the above equation can obtain the voltage of V_C3 in terms of V_in as follows:

$$V_{\mathrm{C}3}=\frac{n{V}_{\mathrm{in}}}{(1-D)}$$

(6)

3.2. The Ratio of V_C2 to V_in

With respect to the ratio of V_C2 to V_in, the current change in L_m2 has to be dealt with first. The current flowing through L_m2 increases when S₂ is closed. After DT_s, the change (Δi_Lm2)_on can be expressed as:

$${\left(\Delta i_{\mathrm{Lm}2}\right)}_{\mathrm{on}}=\frac{V_{\mathrm{in}}D{T}_{\mathrm{s}}}{L_{\mathrm{m}2}}$$

(7)

when switch S₂ is open for (1 − D)T_s and S₁ is in on state. The energy stored in L_m2 will be released to C₂ by coupled inductor T₂ as well as the loop of N₁₂-N₂-C₃-D₂. Therefore:

$$n{V}_{\mathrm{Lm}1}-n{V}_{\mathrm{Lm}2}-V_{\mathrm{C}2}=0$$

(8)

In Equation (8), the voltage across L_m1 equals V_in, thus:

$$V_{\mathrm{Lm}2}=\frac{n{V}_{in}-V_{\mathrm{C}2}}{n}=L_{m2}\frac{\mathrm{d}{i}_{\mathrm{Lm}2}}{\mathrm{d}t}$$

(9)

The total current drop in L_m2 can be found by:

$${\left(\Delta i_{\mathrm{Lm}2}\right)}_{\mathrm{off}}=\frac{\left(n{V}_{\mathrm{in}}-V_{\mathrm{C}2}\right)\left(1-D\right)T_{\mathrm{s}}}{n{L}_{\mathrm{m}2}}$$

(10)

In steady state, over one switching cycle the net change of the inductor current i_Lm2 is zero. That is:

$$n{V}_{\mathrm{in}}D{T}_{\mathrm{s}}+\left(n{V}_{\mathrm{in}}-V_{\mathrm{C}2}\right)\left(1-D\right)T_{\mathrm{s}}=0$$

(11)

Thus, the voltage of V_C2 in terms of V_in is as follows:

$$V_{\mathrm{C}2}=\frac{n{V}_{\mathrm{in}}}{(1-D)}$$

(12)

3.3. The Ratio of V_C1 to V_in

While S₁ is open and S₂ is closed, from the current flow path of V_in-L_m1-D₁-C₂-N₂-N₁₂-C₁-S₂, the following relationship can be found:

$$V_{\mathrm{Lm}1}=\frac{V_{\mathrm{in}}+V_{\mathrm{C}2}+n{V}_{\mathrm{Lm}2}-V_{\mathrm{C}1}}{\left(1+n\right)}=L_{\mathrm{m}1}\frac{\mathrm{d}{i}_{\mathrm{Lm}1}}{\mathrm{d}t}$$

(13)

Since the voltage across L_m2 in Equation (13) is V_in, the current decrease on L_m1 is derived as:

$${\left(\Delta i_{\mathrm{Lm}1}\right)}_{\mathrm{off}}=\frac{(V_{\mathrm{in}}+V_{\mathrm{C}2}+n{V}_{\mathrm{in}}-V_{\mathrm{C}1})(1-D)T_{\mathrm{s}}}{\left(1+n\right)L_{\mathrm{m}1}}$$

(14)

In addition, the total amount of current increase on L_m1 over the S₁-closed interval has been depicted as Equation (1). This increment is equal to the decrease amount in i_Lm1 over one switching cycle, which yields:

$$\frac{V_{\mathrm{in}}D{T}_{\mathrm{s}}}{L_{\mathrm{m}1}}+\frac{(V_{\mathrm{in}}+V_{\mathrm{C}2}+n{V}_{\mathrm{in}}-V_{\mathrm{C}1})(1-D)T_{\mathrm{s}}}{(1+n)L_{\mathrm{m}1}}=0$$

(15)

Rearranging Equation (15) results in:

$$V_{\mathrm{C}1}=\frac{(1+2n)}{(1-D)}{V}_{\mathrm{in}}$$

(16)

3.4. The Ratio of V_o to V_in

Under the condition that S₁ is closed and S₂ is in off state, the voltage V_Lm2 can be determined by applying KVL to the loop enclosed by V_in, L_m2, C₁, N₁₂, N₂, C₃, D_o, and C_o. Therefore:

$$V_{\mathrm{Lm}2}=\frac{V_{\mathrm{in}}+V_{\mathrm{C}1}+n{V}_{\mathrm{in}}+V_{\mathrm{C}3}-V_{\mathrm{o}}}{\left(1+n\right)}=L_{\mathrm{m}2}\frac{{\mathrm{di}}_{\mathrm{Lm}2}}{\mathrm{dt}}$$

(17)

Thus, the decreased quantity of i_Lm2 is expressed as:

$${\left(\Delta i_{\mathrm{Lm}2}\right)}_{\mathrm{off}}=\frac{\left(V_{\mathrm{in}}+V_{\mathrm{C}1}+n{V}_{\mathrm{in}}+V_{\mathrm{C}3}-V_{\mathrm{o}}\right)\left(1-D\right)T_{\mathrm{s}}}{\left(1+n\right)L_{\mathrm{m}2}}$$

(18)

From the increment (Δi_Lm2)_on in Equation (7) and the condition (Δi_Lm2)_off = (Δi_Lm2)_on, the following relationship holds:

$$\frac{V_{\mathrm{in}}D{T}_{\mathrm{s}}}{L_{\mathrm{m}2}}+\frac{\left(V_{\mathrm{in}}+V_{\mathrm{C}1}+n{V}_{\mathrm{in}}+V_{\mathrm{C}3}-V_{\mathrm{o}}\right)\left(1-D\right)T_{\mathrm{s}}}{\left(1+n\right)L_{\mathrm{m}2}}=0$$

(19)

After simplifying, the following equation can be obtained:

$$V_{\mathrm{in}}\frac{\left(1+n\right)D}{\left(1-D\right)}+V_{\mathrm{in}}+V_{\mathrm{C}1}+n{V}_{\mathrm{in}}+V_{\mathrm{C}3}-V_{\mathrm{o}}=0$$

(20)

Substituting Equations (6) and (16) into Equation (20) can obtain the voltage gain of the proposed converter, V_o/V_in, and yields:

$$\frac{V_{\mathrm{o}}}{V_{\mathrm{in}}}=\frac{2\left(2n+1\right)}{(1-D)}$$

(21)

4. Voltage Stress of Power Component

This section begins with the determination of voltage stresses across S₁ and S₂. Supposing that all leakage inductances are neglected, Modes 4 and 9 in Section 2 will therefore dominate the estimation of voltage stress. When S₁ is open, from Figure 2d it can be found that the blocking voltage of S₁, V_DS1,stress, can be expressed as

$$V_{\mathrm{DS}1,\text{stress}}=V_{\mathrm{C}1}-V_{\mathrm{C}2}-V_{\mathrm{C}3}=\frac{1}{1-D}{V}_{\mathrm{in}}$$

(22)

With respect to active switch S₂, its blocking voltage, V_DS2,stress, can be determined from Figure 2i and the following relationship can be found:

$$V_{\mathrm{DS}2,\text{stress}}=V_{\mathrm{o}}-V_{\mathrm{C}3}-V_{\mathrm{C}2}-V_{\mathrm{C}1}=\frac{1}{1-D}{V}_{\mathrm{in}}$$

(23)

Equations (22) and (23) reveal that the voltage stresses of S₁ and S₂ are identical and irrelative to turns ratio of coupled inductor. Voltage stresses across active switches only depend on duty ratio and input voltage. Rewriting Equations (22) and (23) in terms of V_o results in:

$$V_{\mathrm{DS}1,\mathrm{stress}}=V_{\mathrm{DS}2,\mathrm{stress}}=\frac{V_{\mathrm{o}}}{2(1+n)}$$

(24)

Equation (24) implies that the voltage stresses of S₁ and S₂ are much lower than output voltage. Considering the statues of S₁ on and S₂ off, the voltage across D₁ and D₃ can be determined as follows:

$$V_{\mathrm{D}1,\text{stress}}=V_{\mathrm{o}}-V_{\mathrm{C}3}-V_{\mathrm{C}2}=\frac{2(1+n)}{1-D}{V}_{\mathrm{in}}$$

(25)

and:

$$V_{\mathrm{D}3,\mathrm{stress}}=V_{\mathrm{C}3}+V_{\mathrm{C}2}=\frac{2n}{1-D}{V}_{\mathrm{in}}$$

(26)

With respect to D₂ and D_o, their voltage stresses are calculated during the time interval of S₁ off and S₂ on. The corresponding voltage stress calculations can be:

$$V_{\mathrm{D}2,\mathrm{stress}}=V_{\mathrm{C}2}+V_{\mathrm{C}3}=\frac{2n}{1-D}{V}_{\mathrm{in}}$$

(27)

and:

$$V_{\mathrm{D}\mathrm{o},\text{stress}}=V_{\mathrm{o}}-V_{\mathrm{C}1}=\frac{1+2n}{1-D}{V}_{\mathrm{in}}$$

(28)

According to Equations (25)–(28), it can be observed that D₁ endures the highest voltage stress among the four diodes.

Table 1. Comparison among the proposed and other high step-up converters.

Items	Converter Introduced in [13]	Converter Introduced in [14]	Converter Introduced in [15]	Converter Introduced in [16]	Proposed Converter
Voltage gain	$\frac{1+n}{1-D}$	$\frac{2+nD-n{D}^2}{1-D}$	$\frac{2(1+n)}{1-D}$	$\frac{2(1+n)}{1-D}$	$\frac{2(1+2n)}{1-D}$
Number of active switches	4	2	2	2	2
Number of diodes	4	4	6	4	4
Number of capacitors	3	3	5	4	4
Number of transformers	1	1	2	2	2
Number of inductors	2	2	0	0	0
Maximum voltage stress of active switch	$\frac{V_{\mathrm{o}}}{1+n}$	$\frac{V_{\mathrm{o}}}{2+nD-n{D}^2}$	$\frac{V_{\mathrm{o}}}{2(1+n)}$	$\frac{V_{\mathrm{o}}}{2(1+n)}$	$\frac{V_o}{2(1+n)}$
Maximum voltage stress of diode	Vo	$\frac{2V_{\mathrm{o}}}{2+nD-n{D}^2}$	$\frac{(1+2n)V_{\mathrm{o}}}{2(1+n)}$	$\frac{n{V}_{\mathrm{o}}}{1+n}$	$\frac{(1+n)V_{\mathrm{o}}}{1+2n}$

summaries the comparison between NIC and other high step-up converters proposed in [13,14,15,16]. If the duty cycle D is 0.6, and the transformer turns ratio n is 1, the proposed converter can boost 15-times input voltage. However, the voltage gains of the converters in [13,14,15,16] are 5, 5.6, 10, and 10, respectively. It is obvious that the proposed NIC can exceed these high step-up converters in voltage gain. With respect to voltage stress across semiconductor device, if under the same condition that D = 0.6, n = 1, and V_o = 380 V, the maximum voltage stress of the active switches in [15,16] and the proposed NIC are all 95 V, but the converters in [13,14] are up to 190 V and 170 V, respectively. That is, the proposed converter features an advantage over other high step-up converters.

5. Experimental Results

To validate the proposed NIC, a prototype based on the specifications summarized in

Table 2. Specifications of the proposed converter.

Symbols	Items	Values
Vin	Input voltage	24 V
Vo	Output voltage	380 V
Po	Output power	200 W
D	Duty cycle	0.62
fs	Switching frequency	50 kHz
n	Transformer turns ratio	1
Lm	Magnetizing inductance	93 μH
Llk	Leakage inductance	1.9 μH
C1, C2, and C3	Capacitances	68 μF
Co	Output capacitance	330 μF

is designed, built, and tested. The types of semiconductor devices used in the prototype are given in

Table 3. Semiconductor devices used in the prototype.

Components	Types	Absolute Maximum Ratings
D1 and Do	FEP16GT	400 V/16 A
D2 and D3	VS-8ETH03-1PbF	300 V/8 A
S1 and S2	IRFSL4615PbF	150 V/33 A

. The power MOSFET, IRFSL4615PbF (International Rectifier, El Segundo, CA, USA), is selected to serve as active switches for controlling the current flow, of which maximum on-state resistance R_DS(on) is 42 mΩ. The FEP16GT (Fairchild, Sunnyvale, CA, USA) is employed as diodes D₁ and D_o, of which forward voltage is 1.3 V and reverse recovery time is 50 ns. With regard to diodes D₂ and D₃, the hyper-fast rectifier VS-8ETH03-1PbF (Nichicon, Kyoto, Japan) is considered, which has 1.25 V forward voltage and 35 ns reverse recovery time. The voltage waveforms of active power switches and control signals are shown in Figure 4a,b, which indicate that the voltage across S₁ and S₂ are both near 65 V. This value also demonstrates a relatively low voltage stress across the active power semiconductor, as compared with other high step-up converters.

Figure 5a,d is the practical measurements of voltage waveforms of diodes D_o, D₁, D₂ and D₃, in turn, at the condition D = 0.62 and in CCM operation. Figure 5a illustrates that the maximum blocking voltage of D_o is nearly 200 V. With respect to D₁, its voltage stress approaches to 280 V, as shown in Figure 5b. Diodes D₂ and D₃ endure the same voltage of 130 V. In Figure 5, all the diode voltage stresses are in compliance with Equations (25)–(28).

Figure 6 shows the waveforms of input current and the corresponding control signals. It indicates that the magnitude of input ripple current is limited to less than 2 A. Figure 7 depicts the measured and simulated efficiencies from light load to full load. In the simulations, the considered conditions include forward voltage of diode, R_DS(on) of MOSFET, copper loss of the coupled inductor, switching loss of MOSFET, and the equivalent resistance of diode. The maximum value of the measured efficiency is 93.7% at P_o = 140 W. Figure 8 is the photo of test bench, in which PV simulator Chroma 62050H-600S (Taoyuan, Taiwan) serves as input source, electronic load Chroma 6320 draws power from the converter, and all waveforms are measured by oscilloscope KEYSIGHT DSOX4024A (Santa Rosa, CA, USA).

6. Conclusions

This paper proposes a NIC, which is applicable to PV systems or fuel cells for grid-connected high-power applications. The proposed converter utilizes the interleaved technique for current sharing to decrease input current ripples. Furthermore, the proposed converter can achieve a much higher voltage gain than a conventional interleaved converter. The operation principle and steady-state analysis of the proposed converter are described in detail. A 24 V/380 V 200 W prototype has been examined to demonstrate the feasibility of the proposed NIC. The maximum measured efficiency of the proposed converter is 93.7%. This value is a little lower than some of other high step-up converters. However, if the soft-switching technique is employed to make the switches operate at zero-voltage-switching or zero-current-switching condition, the efficiency of the proposed NIC can be improved significantly.