Charge-Line Dual-FET High-Repetition-Rate Pulsed Laser Driver

Abstract

Most modern pulsed laser systems require versatile laser diode drivers. A state-of-the-art pulsed laser driver should provide precise peak power regulation, high repetition rate, and pulse duration control. A new, charge line dual-FET transistor circuit structure was developed to provide all these features. The pulsed modulation current is adjustable up to I_max = 1.2 A, with the laser diode forward voltage acceptable up to U_{F max} = 20 V. The maximum repetition rate is limited by a charge line circuit to f_{rep max} = 20 MHz. Compared to the conventional single transistor drivers, the solution proposed in this paper allows a precise, high resolution width regulation to be obtained, whereas a low pulse jitter is ensured. In the solution, two separate, out-of-phase signals are used to trigger the individual Field Effect Transistors (FET). The resultant pulsed modulation current full-width-at-half-maxima (FWHM) is regulated from ~200 ps up to 2 ns. All control and timing signals are generated with a popular Field-Programmable Gate Array (FPGA) digital circuitry. The use of standard FPGA devices ensures the low cost and high reliability of the circuit, which are not available in laser drivers consisting of sophisticated analogue adjustable delay circuits.

1. Introduction

Nowadays, high-power short laser pulses are the subject of great interest in many fields of application, e.g., Light Detection and Ranging (LIDAR) [1,2], time resolved spectroscopy [3], or picosecond gain switched lasers [4]. The pulsed current source might also be applied to the electrically tunable Near Infra-Red (NIR) [4] or Quantum Cascade Lasers [5]. However, the main application of the solution presented in this paper is the seed laser driver for high-power (kW-level) fiber lasers. Optical pulse quality and reproducibility are vital for a stable and reliable operation of the whole fiber laser system.

The direct modulation of the semiconductor laser current is a commonly used technique to produce fast optical pulses [1,2,6,7,8] and has the advantage of simple and inexpensive operation. Many different topologies have been discussed so far [1,2,6,7]; however, noise parameters are rarely recalled. Considering those facts, a novel direct laser current modulator was designed and constructed resulting in the outstanding noise and switching properties.

2. Foundation of Charge-Line Pulsed Laser Driver

2.1. Dual-FET Output Stage Topology

One of the most popular solutions dedicated to high-power drivers utilizes single switching devices [1,2,6,7]. For this reason, the avalanche transistors for over 60 years [9] were the commonly used devices in laser pulsed generators [6,7]. However, nowadays most of the modern systems utilize Field Effect Transistors (FET) [1,2]. The basic example topologies, shown in Figure 1, are based on charge storage passive elements. In order to briefly analyze their principle of operation, a steady state (transistors are switched-off and storage elements are charged) is assumed.

If the trigger signal is applied, the C_C capacitor in Figure 1a is discharged through a semiconductor switch and a laser diode, resulting in an optical pulse of Gaussian shape [1,2]. The amplitude of the laser pulse is determined both by the +HV voltage applied to the driver, and the C_C capacitance. Therefore, it is impossible to adjust the pulse width and amplitude separately. Nevertheless, the main advantage of this simple circuit is its high laser current [1,6], limited only by the parasitic inductances and resistances of the Cc, Q_CAP, and laser diode itself.

In the other topology, which is shown in Figure 1b, an open-end delay line was utilized as a charge storage element. When the trigger signal (denoted as Trg) is applied, the transistor Q_LINE starts to discharge the line. The delay line acts then as a constant current sink (the peak current is determined by the characteristic impedance Z0 of the transmission line and initial line voltage) by the time needed by the falling edge signal to propagate back and forth through the passive element. The duration of the optical pulse resulting from the square wave applied to the laser is approximately 2 ∙ DL, thus a pulse width adjustment is possible only by replacing the physical element (i.e., the delay line). On the other hand, the peak power is independent of the pulse timing and might be adjusted by the +HV voltage setting.

The novel topology of the pulsed laser driver described in this paper is shown in Figure 2. It combines two symmetrical structures from Figure 2b, although a single shared delay line is used [7]. The operation of the circuit can be divided into two adjacent phases. During the first phase, the transistor Q₁ is switched on at time t₁ and a pre-charged delay line supplies the laser diode (assures the current flow). If no trigger signal is applied to the Q₂, the resulting optical pulse width is 2 ∙ DL, as in the circuit shown in Figure 1b. However, if a second trigger signal is also supplied to the Q₂ in the succeeding second phase, i.e., t₂ = t₁, the transistors Q₁ and Q₂ start to discharge the delay line at the same time. This causes the premature termination of the lasing current at time t₁ + DL. By adjusting the mutual position t₂ and t₁ in the time domain, according to Equation (1), the available regulated laser pulse width ranges from 0 to 2 ∙ DL.

t_FWHM = t₂ − t₁ + DL

(1)

where t_{FWHM MIN} → 0 and t_{FWHM MAX} = 2 ∙ DL

The lasing peak current is adjusted via the +HV voltage, applied to the driver. According to Equation (2), the main current limiting factors in the dual-FET topology are laser forward voltage, Q₁-on resistance and Z₀ of the delay line.

$${\mathrm{I}}_{\mathrm{LAS}} = \frac{U_{+HV}- U_{F LAS}}{R_{on Q1}+Z_0}$$

(2)

2.2. Circuit Timing

The circuit in Figure 2 requires synchronized clock sources responsible for the triggering of Q₁ and Q₂. There are common approaches that incorporate either an adjustable delay obtained with the use of either the Direct Digital Synthesis (DDS) circuit (Figure 3a) [10,11,12] or an analogue approach based on the ramp source and a programmable comparator (see Figure 3b) [10,11,12]. The analogue solution is relatively inexpensive; however, several drawbacks of an analogue delay line may decrease the functionality of the laser driver. The first drawback results from the temperature influence on the parameters of component parameters (i.e., capacitance, intrinsic propagation delays, and threshold voltages). Therefore, a thermal compensation of the circuit is necessary. The second drawback results from the noise processes affecting the relative position of the delayed clock slopes. On the contrary, the digital solutions based on the DDS ensuring sub-nanosecond resolutions are expensive or require high clock speeds.

Modern Field-Programmable Gate Array (FPGA) devices offer advanced clocking resources like a Phase Locked Loop (PLL) or a Digital Clock Manager (DCM) [13]. They allow the obtaining of various frequencies, clock delays, and phase shifts within the FPGA device, with the use of just a single external clock source. In the proposed solution we have utilized a modern Xilinx Spartan 6 FPGA device (XC6SLX16), in which the DCM is implemented as a programmable delay line depicted in Figure 4.

The principle of operation of the device in Figure 4 is based on the phase loop, in which the phase detector alters the delay of the delay chain formed of delay blocks by the adjustment of the multiplexer (MUX). Therefore, the DCM offers both a relatively small jitter and a high resolution (low step). The single-cycle jitter measured with the Agilent 53,200 counter/timer for the XC6SLX16 device used in the proposed laser driver did not exceed 20 ps, whereas the resolution (interval between subsequent steps) was δ_r = 18 ps. These parameters decide on the overall performance of the circuit proposed in Figure 2; however, further system measurements (see Section 4) show that they are sufficient for our driver’s implementation. In order to ensure total independence from the external circuitry of our solution, we used a 100 MHz crystal clock connected to the global clock source (GCK) of the FPGA. The 100 MHz source was used as the input for the DCM device, which produces an adjustable delay within the 0–2 ns range at the CLK0 output (see Figure 5). This output acted as a timing of a simple digital subcircuit formed of two D flip-flops (DFFs) that was responsible for the repetition frequency limitation of our driver. The GCK and delayed CLK0 clock signals from the DCM were used as the timing sources at the clock inputs of the DFFs. The phase-shifted rising slope (edge) at the clock inputs together with constant positive supply at the data input (D) of the DFF enforce a delayed appearance of logical ‘1’ at the DFF Q outputs. This way we are able to obtain a phase delay (δ) of the rising edges at DFFs outputs (denoted as Q in Figure 5). On the other hand, the Chip Enable (CE) inputs of DFFs allowed us to periodically disable the signal at Q outputs of DFFs. The low logical level at CE inputs disables the laser pulse for a single GCK and CLK0 period, and, as a result, decreases the laser average pulse repetition rate. Therefore, the driver is able to decrease (control) the number of pulses available at Trg1 and Trg2 outputs, which activate the switching transistors (and the laser). After each excitation of the laser, caused by the appearance of logical ‘1’ at Q outputs, a clear (CLR) signal must be applied in order to reset both DFFs and switch off the transistors.

The block diagram of the digital timing circuit is shown in Figure 5, and also contains a Finite State Machine, which is responsible for proper DCM and D flip-flop timing. The Finite State Machine adjusts the delay setting of the DCM according to the 8-bit input value, and ensures the limited repetition rate (output frequency of Trg1 and Trg2, despite the GCK frequency. The output signals Trg1 and Trg2 are directly connected to the input buffers (74AC series) shown in Figure 2.

3. System Implementation

To achieve the best performance of the pulsed laser driver, care must be taken in order to choose adequate transistors and passive elements. Sub-nanosecond high-current switching requires low inductance transmission lines on PCB and dense element placement.

3.1. Tranistor Switches

The proper choice of semiconductor switches was aimed at minimizing the noise and maximizing the driver’s speed of operation. The avalanche transistors exhibit fast and high-current pulses [6,7], but they suffer from the thermal drift and high power loses. On the other hand, large gate and parasitic capacitances of high-power Metal-Oxide Semiconductor (MOS) devices make them suitable only in resonant circuits [1,2]. Therefore, instead of using bipolar or MOS devices, GaN High-Electron-Mobility Transistors (HEMT) with parameters listed in

Table 1. GaN High-Electron-Mobility Transistors (HEMT) electrical characteristics.

Parameter	Rating
UDS MAX	84 V
ID SAT (UDS = 6 V, UGS = 2 V)	2 A
RDS ON	<2 Ω
Operation frequency	DC to 6 GHz
Pdiss max	8 W

were used. HEMTs are modern microwave components used in the pulsed and continuous wave high power Radio-Frequency (RF) devices. They exhibit a very low gate charge and, due to the pulse mode of gate driving applied, fast and high-current switching is achievable.

3.2. Delay Line and Charging Resistor

In the presented solution, approximately 25 cm of a high quality RF coaxial cable was used to obtain the maximum pulse width of approximately t_{FWHM MAX} = 2 ∙ DL = 2 ns. The characteristic impedance of the transmission line is of the commonly used standard, i.e., Z₀ = 50 Ω. If the boundary values of parameters in Equation (2) are considered, the maximum lasing current is described by Equation (3).

$${\mathrm{I}}_{\mathrm{LAS} \mathrm{MAX}} = \frac{U_{+HV}- U_{F LAS}}{R_{on Q1}+Z_0}=\frac{U_{DS MAX}- U_{F MAX}}{R_{DS ON}+Z_0}=\frac{84 V-20 V}{2 \mathsf{\Omega }+50 \mathsf{\Omega }}=\mathrm{1,23} \mathrm{A}$$

(3)

Each generated pulse discharges the delay line, whereas the recharging process takes place during successive repetitions. The R_C resistor supplies the delay line with a time constant τ_line = R_C ∙ C_line, where C_line is approximately 23 pF. In order to ensure a stable pulse amplitude in a wide range of repetition rate (DC to 20 MHz), R_C should fully charge the line in the shortest period between the two following pulses at Trg1 and Trg2 (i.e., t_min = 46 ns). If the time constant relation of Equation (4) is assumed, the line will charge to >98% of the final voltage.

τ_line = 4 ∙ R_C ∙ C_line < t_min
R_C < 500 Ω

(4)

3.3. Matching Resistor of the Line

If the delay line quenching pulse generated by the Q₂ switch has a higher amplitude compared to the pulse generated by Q₁, a negative current flow will occur in the laser diode. It may lead to the permanent damage of the laser structure, thus a matching resistor R_M was used in the circuit. The R_M value was set experimentally to 10 Ω.

3.4. Input Buffers

In the pulse mode, high current transient states in HEMT transistors are observed. Therefore, the process of switching at inputs (gates) of HEMTs should be as short as possible. Moreover, the low inclination of Trg1 and Trg2 rising edges could be easily affected by interferences caused by glitches coming from the switching process of HEMTs. Therefore, in order to ensure the fast switching of the transistors, each input buffer (between FPGA outputs and HEMT gates) combines four connected in-parallel AC family Complementary Metal Oxide Semiconductor (CMOS) logic gates. The buffers’ inputs are directly driven by the FPGA timing subsystem shown in Figure 5.

3.5. +HV DC–DC Converter

The peak pulse power of the laser diode is regulated directly via the +HV supply voltage (see Figure 2). In order to increase the versatility of the laser driver system, a DC–DC converter, regulated from 10 V up to 80 V was implemented.

3.6. PCB Layout

A complete ready-to-use laser driver device is shown in Figure 6a. A two layer PCB and short component connections ensure low impedance current paths. For the test purposes, instead of the laser, a loading resistor R_L was connected to the driver’s output.

The trigger signals (Trg1 and Trg2) are routed to the buffers in the top-right side of the dual-FET PCB and are connected to the miniature FPGA board shown in Figure 6b. In order to avoid trigger signal reflections and minimize the jitter of the trigger signals, the FPGA board consists of the line matching resistors at the IO pins.

4. Test Results

4.1. Preliminary Tests of the System

During preliminary tests of the electrical parameters of the presented driver, a resistive load R_L = 33 Ω was used. The Figure 7a shows different settings of the FPGA timing signal leading to different intervals obtained at the dual-FET driver. The maximum pulse width is approximately 2 ns, which is in a good agreement with the design assumptions. The measured current-pulse rise times t_{r 10%–90%} < 140 ps and fall times t_{f 10%–90%} < 430 ps are sufficient to generate sub-nanosecond laser pulses. The falling edge negative current undershoot and spike is noticeable in Figure 7a. To compensate this effect, the increase of the matching resistor R_M value might be considered.

Figure 7b shows the pulse peak current regulation via +HV voltage adjustment. In the test load configuration (R_L = 33 Ω), the maximum peak current of 0.96 A was obtained.

Operating with higher repetition rates leads to the peak power amplitude compression. In Figure 8, a less than 2.5 dB drop of the initial current amplitude is observed for f_{rep max} = 20 MHz. The obtained f_repmax frequency at 1.25 A pulse current is high, when compared to professional solutions available on the market [14].

4.2. Pulsed Laser Driver Integrated with Infra-Red Laser

The final tests of the presented solution were performed with the Osram SPL PL90_3 NIR laser [15]. Parameters of this high-power optical source are listed in

Table 2. Near Infra-Red (NIR) laser catalogue typical parameters (room temperature).

Parameter	Symbol	Value
Threshold current	Ith	0.75 A
Operating forward voltage	UF	9 V
Wavelength	λpeak	905 nm
Maximum output power	Po max	75 W
Rise/fall time	tr/tf	1 ns/1 ns

. The pulse characterization was performed using a high-speed (f_BW = 5 GHz) THORLABS DET08CFC photodetector [16].

The effect of the pulse width regulation obtained with the designed driver is shown in Figure 9a. The shortest measured pulse has a symmetrical Gaussian shape and duration of 322 ps, which confirms the high-speed and high-current switching performance of the solution. The maximum pulse width is limited to 940 ps, because of the particular laser`s turn-on delay time. However, all measured optical pulses are characterized with rise time <220 ps and fall time <680 ps, which is much shorter than the laser manufacturer’s specification (see Table 2).

The optical pulse power regulation is shown in Figure 9b. The maximum pulsing current for U_+HV = 80 V was measured to be approximately 1.3 A and is sufficient do drive most of the market-available 1 W NIR lasers.

The measurements shown in Figure 9 prove that the developed laser driver is capable of independent regulation of the pulse width and amplitude, although one of the key parameters of the developed laser driver is a very low timing noise. In Figure 10a, family of time domain waveforms corresponding to multiple optical pulses generated by the laser diode are shown. The “blur” observed at the falling edges represents the phase fluctuations of the signal (noise in the time domain)—jitter. The maximum measured jitter is σ_t = 28 ps for t_FWHM = 500 ps. This ensures stable and reproducible optical pulse generation, regardless of the width of the optical pulse.

The pulse-to-pulse optical signal amplitude stability measurements are shown in Figure 11. The amplitude fluctuations-over-time parameter σ_A (std. dev.) is not affected by t_FWHM or f_rep adjustments. However, as listed in

Table 3. Pulse-to-pulse amplitude stability (t_FWHM = 900 ps, f_rep = 1 MHz).

Optical Pulse Measurements
Amplitude [mW]	σA [mW]	SA = Amp./σA
250 (U+HV = 45 V)	6.5	38
520 (U+HV = 60 V)	17.3	30
750 (U+HV = 80 V)	28.6	26
Electrical Pulse Measurements (RL = 33 Ω)
Amplitude [mA]	σC [mA]	Sc = Amp./σC
510 (U+HV = 45 V)	1.3	392
705 (U+HV = 60 V)	1.8	391
960 (U+HV = 80 V)	2.5	384

, the optical pulse amplitude instability increases with higher modulation currents. To present amplitude instability relative to peak pulse amplitude, the S_A and S_C parameters were included in Table 3. The S_A ratio is not constant and, compared to the S_C, measured with resistive load R_L = 33 Ω; we suspect that both the NIR laser and detection system exhibit an additional 1/f or excess noise.

The long term stability was measured with an optical peak power of 750 mW and t_FWHM = 750 ps, while the repetition rate was set to 1 MHz. Figure 12 presents the data set after 12 h of continuous optical signal sampling. The laser driver showed a high and reproducible performance with negligible pulse width and amplitude drift.

5. Conclusions

In this paper a new approach of utilizing delay-line based pulsed current source for generating short optical pulses was presented and described. With the use of modern HEMT transistors and modern reconfigurable device (FPGA), a fast and high-current switching driving stage was designed.

The novelty of the presented solution lies in the independence of the pulse width adjustment ranging from <300 ps to 2 ns and the peak pulse current adjustment (reaching up to I_max = 1.2 A), with the repetition rate form single-shot up to f_{rep max} = 20 MHz. Moreover, all the control and timing signals are sourced from the FPGA timing circuit, which makes the presented solution a complete, stand-alone device.

It was shown that the driver integrated with a NIR laser can generate high-power optical pulses with precisely adjusted amplitude and duration. Very low timing noise, amplitude reproducibility, and long-term stability has proven the high performance of the developed system.