High-Performance On-Chip Racetrack Resonator Based on GSST-Slot for In-Memory Computing
Abstract
:1. Introduction
2. Device Principle and Parameter Optimization
2.1. Device Design and Scalar Multiplication Concepts
2.2. Parameter Optimization
3. Device Simulation
3.1. Switching Simulation
3.2. Thermal Simulation
4. Scalar Multiplication
5. Recognition Test
6. Fabrication Method
7. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Data Availability Statement
Conflicts of Interest
References
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Material | Cp (J/kgK) | K (W/mK) | ρ (kg/m3) |
---|---|---|---|
aGSST [27] | 213 | 0.19 | 5870 |
cGSST [27] | 199 | 0.57 | 6270 |
Si [20] | 720 | 149 | 2330 |
SiO2 [20] | 740 | 1.38 | 2200 |
Device Type | PCM Size (μm3) | Resonator Circumference (μm) | ER-Through/ ER-Drop (dB) | IL-Through/ IL-Drop (dB) | RW Shift (nm) | Ewrite/ Eerase (pJ) |
---|---|---|---|---|---|---|
GST disk/ Si3N4-microing [28] | 0.25 × 0.785 × 0.01 | - | 13.64/ 21.25 | 0.46/ 0.75 | ~1 | 200/- |
GST pad/ Si-racetrack [29] | 3 × 1.5 × 0.02 | 37.4 | 12.36/- | 2.5/- | 0.2 | 3600/ 900 |
GST embed/ Si-microing [14] | 1 × 0.48 × 0.02 | 31.4 | 25.57/ 18.75 | 1.95/ 5.04 | 4.63 | 1063/ 181 |
GSST pad/ Si-racetrack [15] | 15 × 0.3 × 0.045 | 92.8 | 18/- | 0.19/- | ~0 | - |
GSST slot/ Si-racetrack (this study) | 1 × 0.25 × 0.22 | 43.4 | 30.22/ 29.64 | 0.93/ 0.16 | 7.13 | 500/ 200 |
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Zhu, H.; Lu, Y.; Cai, L. High-Performance On-Chip Racetrack Resonator Based on GSST-Slot for In-Memory Computing. Nanomaterials 2023, 13, 837. https://doi.org/10.3390/nano13050837
Zhu H, Lu Y, Cai L. High-Performance On-Chip Racetrack Resonator Based on GSST-Slot for In-Memory Computing. Nanomaterials. 2023; 13(5):837. https://doi.org/10.3390/nano13050837
Chicago/Turabian StyleZhu, Honghui, Yegang Lu, and Linying Cai. 2023. "High-Performance On-Chip Racetrack Resonator Based on GSST-Slot for In-Memory Computing" Nanomaterials 13, no. 5: 837. https://doi.org/10.3390/nano13050837