A High Performance 0.18 μm RF Switch for Multi-Standard

Abstract

This paper proposes a stacked field-effect transistor (FET) single-pole, double-throw (SPDT) RF switch which is capable of multi-standard. Negative voltage generator (NVG), logic controller, level shifter, and RF Switch branches are integrated. A PMOS self-biased strategy is proposed to improve linearity and simplify the design of the logic controller and level shifter. In order to reduce the influence of NVG, a new charge pump (CP) is proposed, and a low pass filter (LPF) is added to stabilize bias voltages. A new layout of the switch FET is proposed to minimize the product of on-state resistance and off-state capacitance (time constant). The RF switch proposed in this paper was implemented in the 0.18 μm silicon on insulator (SOI) process. The measured results show the P1 dB of 40 dBm, and the isolation (ISO) and insert loss (IL) at 1 GHz/5 GHz of 37 dB/22 dB, and 0.36 dB/0.55 dB. The operating frequency range is DC-6 GHz. Supply current is 37uA with the supply voltage of 2.6V.

1. Introduction

RF switch is important in RF front-end modules. Different communication standards focus on different merits, the key requirements of the RF antenna switches for GSM, WIFI (802.11x) and WCDMA are listed in

Table 1. Performaces required in different standard.

Wireless Standard	Peak Power (dBm)	Band (GHz)	IL (dB)	ISO (dB)	IIP3 (dBm)
GSM	35	0.95/1.95	<1	35	65
802.11x	18	2.4/5.8	<1	25	58
WCDMA	25	0.85/1.9/2.1	<1	25	65

. To cover the different standards, we must achieve a trade-off on these parameters, which is difficult.

A lot of work has been done to improve the performance of the RF switch. Many of those works are implemented in SOI or bulk CMOS process, The two processes are similar, but the former offers better ISO by adding Buried Oxide(BOX) Layer to reduce the leakage current. The optimization methods for these two processes are similar. To improve the power capacity of switches, [1,2,3] adopted a floating-body structure in the CMOS process, a resistor is added between the ground and the body terminal of the transistor, The results in [4] show that the P1 dB of the floating-body switch is 5 dB better than that of the traditional one. Similarly, [5] adopted the same structure in the SOI process, but the resistor is not needed because of the resistance of the BOX layer in large. The LC tuning technique is used in [6] to improve the power handling capacity by reducing the parasitic capacitance of transistors, but the frequency of the switch is limited. Apart from those, there have been a lot of attempts made to achieve high-power switches with SOI or CMOS processes, such as using negative supply voltage to the body substrate [7,8,9,10,11], differential switch structure [12,13], Asymmetric branches [6,14,15,16], and feedforward capacitors [6,17,18] is adopted to address the issue of the unequal voltage division caused by the Asymmetric parasitic capacitance of switch FETs.

In addition to SOI and bulk CMOS processes, there are some other processes adopted. For example, the SiGe HBT process is used for a high-frequency application, and the working frequency of the switch proposed in [19] is dc-110 GHz. MEMS technology is used in RF switch design owing to its reduced size, low power consumption, and superior RF response. However, its reliability issues need to be considered [20,21].

Some works proposed the new structures of the switch. The classical series-parallel structure can improve the performance of the switch, but when the operating frequency exceeds 10 GHz, the parasitic capacitance of the parallel path deteriorates IL. To solve this problem, [22] proposed a switch structure without parallel branches and adjusted the layout of the switch FET to further reduce the effect of parasitic capacitance.

In addition to the optimization of RF switches alone, there are some works that design RF switches together with other modules, such as ESD [23,24], antenna [13], impedance matching networks [12] and NVG [25,26,27]. The performance of RF switches in these works is not outstanding, but the whole module can achieve good performance.

In this paper, a PMOS self-biased RF switch with a reduced time constant and a new NVG block is designed and implemented in the 0.18 μm SOI process. Section 2 introduces the blocks of RF switch. A PMOS self-biased strategy is proposed to minimize the nonlinear capacitance which degrades power capacity. To stabilize bias voltages, a new CP is proposed and an LPF is added at the output of the low dropout regulator (LDO). The parasitic resistance and capacitance of FET are analyzed, and a method to reduce the time constant is given, the proposed layout of FET is designed accordingly.

2. SOI SPDT Switch Design

2.1. Biasing Strategy

The performance of the switch is strongly dependent on biasing strategy. Traditional FB-FETs biasing technique utilizes the buried oxide (BOX) layer of SOI FETs, leaving a floating body of FET [7,28]. But the nonlinear capacitance degrades power capacity badly when the switch FET is turned off. The junction capacitance is the main component of nonlinear capacitance, and it is given in (1):

$$C_j=C_{j0}/\left(1+\frac{V_{bs}}{{\varphi }_B}\right)$$

(1)

where $V_{bs}$ is the reverse voltage across the junction, ${\varphi }_B$ is the junction built-in potential, and m is a power typically in the range of 0.3 and 0.4. $C_j$ can be reduced by improving the absolute value of $V_{bs}$, which indicates the source/drain-body junction of FET should be strongly reverse biased in off-state.

A self-biased PMOS strategy is proposed in this work, and a circuit of RF switch branches is shown in Figure 1. The self-biased PMOS is added between the gates and source of each FET switch. The gates of FET switches in the serial path are biased at a positive voltage in on-state, so, the PMOS is turned off for being reverse biased, and the body of the FET is biased close to the ground because the source/drain-body parasitic diodes are slightly reverse biased. While switch FET is turned off, the gate of the FET is biased at a negative voltage, and the PMOS of it is turned on, the body of FETs are biased to a negative voltage. Additional bias voltages are not needed in the design. In conclusion, the proposed biasing strategy improves power capacity by reducing nonlinear capacitance and the number of bias voltages is just the same as FB-FETs biasing technique.

2.2. Circuit of NVG

NVG is necessary because the negative bias voltage is required in the self-biased PMOS biasing strategy. CP is widely used in NVG, the circuit of traditional CP is shown in Figure 2, charge1 and discharge1 are the charging path and discharging path when CLK is 0, and charge2 and discharge2 are that when CLK is 1.

The first problem of the traditional CP is the leakage current, which happens when the PMOS and NMOS, such as MN2 and MP2 shown in Figure 2, are simultaneously turned on for a short time at the transitions of CLK. This results in higher power consumption and the degradation of output voltage. Figure 3 is used to illustrate the influence of the leakage current, $V_B$ and $V_C$ are the voltages of drain and gate of MN3 and MP3, MN3 works in triode region from 0 to t1, and works in saturation region from t1 to t2, the duration of the transition is t0. The power consumption introduced by the overlapping of CLK1 and CLK2 is given in (2) [27]:

$$P=f{V}_{DD}^3{t}_0[\frac{5}{16}{\mu }_n{C}_{ox}{(\frac{w}{l})}_n{(1-{\alpha }_n)}^3+\frac{2}{3}{\mu }_P{C}_{ox}{(\frac{w}{l})}_P{(1-{\alpha }_P)}^3]$$

(2)

where ${\alpha }_n=V_{thn}/V_{DD}$, ${\alpha }_P=V_{thP}/V_{DD}$. For the situation that the PMOS and NMOS are perfectly matched, ${\alpha }_n={\alpha }_n=\alpha$, ${\mu }_n{C}_{ox}{\left(\frac{w}{l}\right)}_n={\mu }_n{C}_{ox}{\left(\frac{w}{l}\right)}_P=\beta$, (2) reduces to (3):

$$P=f{V}_{DD}^3\beta t_0{(1-\alpha )}^3$$

(3)

Another problem is the asymmetry of CLK and NCLK (a transmission gate is adopted in this design to reduce the asymmetry). In Figure 4 are the simulation results of traditional CP, the asymmetry between B and C is even worse than that of CLK and NCLK. As a result, the discharge1 and discharge2 paths are turned on at the same time between t1 and t2 shown in Figure 3 when CLK falls, so the discharging current is larger and the fluctuation of the output voltage is worse. Similarly, the charge1 and charge2 paths are turned on at the same time when CLK rises. As a result, the voltage fluctuations on the rising and falling edges of the CLK are different. The simulation results shown in Figure 5 also prove this. (The timing of the rising edge of CLK is changed to place the curves in the same graph for comparison).

To solve those problems, a new CP with four-phase non-overlapping clocks is proposed. As shown in the Figure 6, the CP consists of three CPs, two of which are auxiliary CPs, they are used to convert the four-phase clocks into the control signals of the main CP. The auxiliary CPs adopt the structure of traditional CP, but since the transistors and capacitors in auxiliary CPs are much smaller than that of the main charge pump, its effect on the output voltage is negligible. Figure 7 is the timing diagram of non-overlapping clocks. Due to the phase differences (p1 and p2), the PMOS and NMOS, such as PM2 and NM2, will not be turned on at the same time. The simulation results of the proposed CP are given in Figure 5, The output voltage of the proposed charge pump produces much less fluctuation than the conventional charge pump, and the output voltage is also closer to -VDD.

The diagram of the RF switch chip is given in Figure 8. The oscillator and the four-phase non-overlapping clocks generator induce glitches in positive bias voltage. To minimize the influence of this process, a LPF is added between V1 and V2.

The post-simulation results in Figure 9 show the negative voltage with and without the proposed CP, and Figure 10 show the fluctuation in the input and output voltage of the added LPF. It can be seen from the results that the fluctuation in the bias voltages of the proposed circuit is neglectable compared to that of the traditional circuit. is also small compared. The effectiveness of the proposed CP and the added LPF is proved.

2.3. Reduced Time Constant

2.3.1. Analysis of IL and ISO

The equivalent-circuit of RF switch is shown in Figure 11. Suppose the width of the FETs in the series and the shunt branch are w and $\beta w$ separately, then the $R_{on}$ and $C_{off}$ of shunt branch are $R_{on}/\beta$ and $\beta C_{off}$. The IL is given in (4) and is simplified as (5). The $k_2$ is neglectable compared to ($2Z_0+R_{on}$) because $C_{off}$ is smaller than 100fF. Equation (3) indicates that the IL is mainly depended on $R_{on}$, reducing $R_{on}$ produces better IL. ISO is given in (6), and it can be simplified as (7), so ISO is related with $C_{off}$, $\beta$ and $R_{on}$.

$$\mathrm{IL}=\frac{2k_1}{(1+s\beta C_{off}{Z}_0)k_1+R_{on}+Z_0+s\beta C_{off}{R}_{on}{Z}_0}$$

(4)

$$k_1=Z_0\left|\right|(\frac{1}{s{C}_{o}ff}+\frac{R_{on}}{\beta })$$

$$\mathrm{IL}=\frac{2Z_0}{(2Z_0+R_{on})+k_2}$$

(5)

$$k_2=s\beta C_{off}{Z}_0^2+s\beta C_{off}{R}_{on}{Z}_0+(R_{on}+Z_0)Z_0{k}_3+s\beta C_{off}{R}_{on}{Z}_0^2{k}_3$$

$$k_3=\frac{s\beta C_{o}ff}{\beta +s{C}_{off}{R}_{on}}$$

$$\mathrm{ISO}=\frac{2k_4}{(k_4+\frac{1}{s{C}_{off}})(1+\frac{\beta Z_0}{R_{on}})+Z_0}$$

(6)

$$k_4=Z_0\left|\right|(R_{on}+\frac{1}{s\beta C_{off}})$$

$$\mathrm{ISO}\approx \frac{2Z_0}{(Z_0+\frac{1}{s{C}_{off}})(1+\frac{\beta Z_0}{R_{on}})+Z_0}$$

(7)

ISO can be improved with greater $\beta$ because the larger size of the shunt switch FETs will reduce the $R_{on}$. But, $\beta C_{off}$ increases, the performance of the harmonic degrades as a result, and a larger chip area is required.

IL and ISO are related to various parameters, the best solution can be calculated from (5) and (7) while $R_{on}$ and $C_{off}$ are assumed. In this work, the width of FET in serial branch and $\beta$ are decided to be 15 μm × 250 and 0.6.

2.3.2. FET with Reduced Time Constant

IL and ISO can be improved by reducing $R_{on}$ and $C_{off}$ respectively according to Equations (5) and (7). The cross section of FET is established in Figure 12, only metal1 and metal2 are taken into consideration here. $R_{on}$ and $C_{off}$ can be reduced by adjusting process, but it is unavailable for circuit designers. The parasitic capacitance between metal wire strongly depends on the layout of components, parasitic capacitance can be reduced with better layout. Equation (8):

$$C_{off}=C_P+C_m=\frac{1}{2}(C_{g}d+C_{b}d)+[\frac{1}{2}\left(C_{Cnt-g}\right)+C_{m1-g})+C_{m1-m1})+C_{m2-m2}\left)\right]$$

(8)

is the total off-capacitance of a FET according to Figure 12, where C_p is the capacitance related with process, and $C_m$ is the capacitance introduced by metal wire. $C_P$ is consisted of $C_{gd}$ and $C_{db}$, and $C_m$ is composed of the capacitance between contact and gate ($C_{Cnt-g}$), metal1 and gate ($C_{m1-g}$), metal1 and metal1 ($C_{m1-m1}$), metal2 and metal2 ($C_{m2-m2}$), metal1 and metal2 ($C_{m1-m2}$).

To reduce the parasitic capacitance between metals, the area between metals should be reduced. To keep the same current density, Metal1 should not be adjusted. And Metal2, as the connection line between devices, is shortenable. According to this, the traditional layout and proposed layout were shown in Figure 13, the metal2 wire in the proposed layout is shorter than the traditional one. Ignoring the $C_{Cnt-g}$, $C_{M1-g}$ and $C_{m1-m2}$, $C_{\ast -unit}$ is the capacitance of per unit length of $C_{\ast }$. The off-state capacitance of the traditional layout ($C_{off-tra}$) and the proposed layout ($C_{off-pro}$) is expressed as (9) and (10) according to (8).

$$C_{off-tra}=\frac{1}{2}(C_{gdo}w+C_{j}wl)+(C_{M1-M1-unit}+C_{M2-M1-unit})w$$

(9)

$$C_{off-pro}=\frac{1}{2}(C_{gdo}w+C_{j}wl)+C_{M1-M1}w$$

(10)

As for Ron, it is given in (11):

$$R_{on}=R_{Par}+R_{Ch}=(R_{M2}+R_{via-t}+R_{M1}+R_{Cnt-t})+R_{Ch}$$

(11)

$R_{Ch}$ is the resistance of channel, and Rpar is everything else, in which the resistance of M1 ($R_{M1}$), M2 ($R_{M2}$), via ($R_{via-t}$) and contact ($R_{Cnt-t}$) are taken into consideration here. The num-ber of vias and contacts are n and m, and they are set to be 12 and 15 in this work. The resistance of a single contact and a single via are $R_{Cnt}$ and $R_{via}$. Ron for traditional layout ($R_{on-tra}$) and proposed layout ($R_{on-pro}$) are calculated with (12) and (13).

$$R_{on-tra}=\frac{R_{via}}{n}+\frac{R_{Cnt}}{m}+R_{Ch}$$

(12)

$$R_{on-pro}=\frac{2R_{via}}{n}+\frac{R_{Cnt}}{m}+R_{Ch}$$

(13)

In

Table 2. Parameters for the adopted process.

Parameter	Value	Parameter	Value
$C_{m1-m1-unit}$	90.0 pF/m	$R_{Cnt}$(0.24 μm × 0.24 μm)	10 $\mathsf{\Omega }$
$C_{m2-m2-unit}$	85.2 pF/m	$R_{M1}$	0.085 $\mathsf{\Omega }/\square$
$C_{gdo}$	0.547 nF/m	$R_{via}$(0.285 μm × 0.285 μm)	3.9 $\mathsf{\Omega }$
$C_{jo}$	1.03 × 10${}^{-3}$ F/m${}^2$	$R_{M2}$	0.080 $\mathsf{\Omega }/\square$

are the parameters of the adopted process. Because the resistance introduced by via is small, the increase in on-resistance has a negligible effect on performance. But the parasitic capacitance is reduced by 12.06% according to (9), (10) and Table 2. As shown in the Figure 14, the ISO at 5 GHz of the switch with proposed layout is 1.5 dB better than that of the switch with traditional layout, and the degration of IL is negenactable. The improvement of ISO caculated with the 12.05% reduced parasitic capacitance is 1 dB, the difference is expected to result from the neglected capacitance in Equations (9) and (10).

3. Measured Results

The photo of the fabricated chip is given in Figure 15. The RF Switch propoesd in this work was designed and implemented in 0.18 μm SOI process. The total area of the chip is $0.71\times 0.82$ mm${}^2$ with two branches, an NVG block, a level-shifter, a logic controller, and the surrounding pads and ESD circuits integrated. The rated operating voltage is 3 V, the output of LDO is 2.35 V, and the output of NVG is closed to −2.35 V. The control voltage is 2.6 V/0 V. The measured total supply current is 37 μA. The measurement results are calibrated with the thru-line loss of the PCB traces and SMA connectors [29].

Figure 16, Figure 17 and Figure 18 are measurement results of the proposed RF switch. The switch achieves the IL and ISO of 0.31 dB/0.6 dB and 55 dB/18 dB at 100 MHz/6 GHz. In the operating frequency band of DC-6 GHz, the IL is better than 0.6 dB and the ISO is better than 18 dB for both branches. The measured 3rd harmonic power ($H_3$) is shown in Figure 19, and the measured $P_{1dB}$ is shown in Figure 18. The RF switch can handle the input power of 39.5 dBm. In

Table 3. Performance comparison with published works.

Parameter	[10]	[6]	[30]	[31]	[5]	This Work
RF switch	SPDT	SP8T	SP6T	SP4T	SP4T	SPDT
Band (GHz)	1/3	0.9/1.9	0.9/1.9	DC/6	0.55/2.5	DC/6
IL (@1/2 GHz)	0.7/0.9	0.45/0.52	0.82/0.88	0.3/0.4	0.55/0.75	0.36/0.43
ISO (@1/2 GHz)	23/27	46.7/22.7	32/28	38/32	39.4/32	37/31
P1 dB (dBm)	20.5	39.2	42.2	37.2	35	39.5
Supply current (μA)	-	50.4	-	80	<1	37
Size (mm${}^2$)	0.26	1.1	0.57 × 0.82	-	1.15 × 0.85	0.71 × 0.82
Biasing technique	floating-body	negative biasing	negative biasing	negative biasing	dc-lifting	negative biasing
Technology	0.18 μm CMOS	0.18 μm SOI	0.18 μm SOI	0.18 μm SOI	0.18 μm SOI	0.18 μm SOI

, the comparison of the proposed RF switch and published works are shown.

Table 3 shows the comparison of the proposed RF switch and the published works. The proposed RF switch shows comparable bandwidth, ISO, and IL while the operating frequency range is markedly better than that of other works, the overall performance of the proposed RF switch is excellent in the frequency range of 1–6 GHz. In terms of power consumption, because the NVG module is used in this paper, the power consumption is significantly higher than the work without NVG, but the supply current is the lowest in the RF switches that use the NVG module. Comparing with the literature using the CMOS process, it can be seen that the RF switches using the SOI process have significant improvements in ISO and $P_{1dB}$.

4. Conclusions

In this paper, a PMOS self-biased RF switch is proposed. The number of biased voltages is the same as that of the FB-FETs biasing technique. By biasing the body terminal of the switch FETs at negative voltage in off state, the power capacity is increased to 39.5 dBm which is good enough for many wireless standards. A new CP is proposed and an LPF was added to stable the bias voltages, the post-layout simulation results verify the effectiveness of proposed CP and the added LPF. The factors influencing ISO and IL are analyzed, and the layout of FET has been improved based on the analysis results. The post-layout simulation results show that the ISO of the RF switch with the proposed layout is 1.5 dB better than that of the traditional one at 5 GHz. The measured results and the comparison with published works indicate that the proposed RF switch achieves a trade-off, and is capable of industry-standard results.