A Novel Autocorrelation Combined MM-CDR Time-Interleaved ADC Timing Calibration in 28 nm CMOS Technology

Abstract

With the great improvement in data transmission rate requirements, the analog-to-digital converter (ADC)-based wireline receiver has received more attention due to its flexible and powerful equalization capability. Time-interleaved ADC (TI-ADC) is the most commonly used architecture in high-speed ADC-based receivers. One of the major challenges in TI-ADC is the timing mismatch between the parallel sub-ADCs. The traditional skew detection and calibration circuits consume substantial power and area of the receiver system. In this article, we propose a novel calibration method using the autocorrelation principle combined with an existing Mueller–Müller clock and data recovery circuit (MM-CDR). This new method reuses the existing error-direction information of the MM-CDR in the ADC-based wireline receiver and combines the autocorrelation principle to obtain the timing mismatch information in the TI-ADC without adding an additional skew deviation extraction circuit, which greatly reduces the area and power consumption. In order to demonstrate the effectiveness and superiority of our skew calibration method, we designed a complete ADC-based wireline receiver circuit using the 28 nm CMOS technology. The simulation results show that our proposed calibration method could obtain 0.193 sensitivity per 1% skew, which was superior to traditional calibration methods. To verify the speed and accuracy of the convergence of our calibration method, the initial skews were set to +0.4 ps, +0.2 ps, −0.59 ps, and 0 ps for our 4 × 8 TI-ADC; the spurious free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) of the ADC were increased from 37.24 dB and 31.28 dB to 48.07 dB and 34.56 dB, respectively, after timing calibration with a 50 fs step. In order to compare the area and power consumption required by different skew calibration methods, we synthesized the expressions of various methods using the 28 nm CMOS technology, and the area and power consumption of our proposed skew calibration loop were 695 μm² and 0.126 mW, respectively, which were the smallest among these methods.

1. Introduction

As the data rate of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections, and crosstalk become more pronounced. Traditional slicer-based receivers struggle to recover the signal with high quality under such a high-loss channel. Therefore, more attention is devoted to analog-to-digital converter (ADC)-based wireline receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) and more powerful ability of equalization [1,2]. Utilizing this back-end DSP can realize complex digital equalization, while also reducing process, voltage, and temperature sensitivity. Furthermore, ADC-based receivers offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes.

The 32 Gb/s ADC-based receiver used in this work shown in Figure 1 utilizes a continuous-time linear equalizer (CTLE), four track and hold (T&H), a 32-way time-interleaved (TI) 6 bit successive approximation register (SAR) ADC, DSP, Mueller–Müller clock and data recovery circuit (MM-CDR), polyphase filter (PPF)/divider for four-phase clock generation, duty cycle detection (DCD)/duty cycle correction (DCC), quadrature error detection (QED)/quadrature error correction (QEC), phase interpolator, and delay cells. One key issue with the TI-ADC receiver is the calibration of the ADC nonideal factors such as offset, gain and timing mismatches [3,4]. The offset and gain mismatches are relatively easy to calibrate in the digital domain.

The task of timing mismatch calibration consists of two functions, namely, detection and correction, each of which can be performed in the analog or digital domain. Detection in the analog domain is prone to the mismatches of the measurement circuitry itself and is, hence, impractical for high resolutions. Detection in the digital domain can be more accurate according to autocorrelation and time derivation. The digital correction approach is based on TI-ADC followed by digital filters which correct the timing mismatch. This approach needs a large number of filter taps, which consumes substantial power and increases the complexity of the digital processor. Compared with the digital method, the analog correction approach using a variable delay line (VDL) is a cost-effective and low-power method.

Several conventional timing mismatch detection methods used in the past are introduced below; by analyzing their different disadvantages [5], we propose a better novel detection method, as described in Section 2.

1.1. A Sinewave-Input FFT-Based Foreground Method

A sinewave-input FFT-based foreground method sends a sinusoid signal at a frequency equal to the sampling rate to the receiver input [6,7]. Then, the computer calculates the FFT of the measured ADC outputs to get the skew mismatch information between different T/H [8,9,10]. The sinewave-input FFT-based foreground method entails two drawbacks; it may overestimate the mismatch by testing only the highest input frequency, and it cannot perform background calibration while the receiver is working.

1.2. Autocorrelation Method

According to the theory of the autocorrelation principle, there is a linear relationship between the output data of the adjacent two-channel ADC and the sampling interval [11,12,13,14]. By continuously accumulating the output data of the adjacent two-channel ADC, the skew mismatch information according to the adjacent sampling time can be obtained [15,16,17]. The main disadvantage of this approach is that the estimation of timing skew through autocorrelation requires the output of ADC for statistics. Greater numbers of bits of the ADC lead to greater hardware overhead.

1.3. Combined Clock and Data Recovery Circuit Method

Recently, a skew detection method combined with clock and data recovery (CDR) was also discussed [18,19,20,21]. The Mueller–Müller CDR is the most popular form of baud-rate CDR. MM-CDR receives data and error-direction information and generates ‘up’ or ‘down’ signals according to the current data and next data if the current error direction is equal to the next error direction. The updated equation for MM-CDR is given by

Δτ_j = e_jd_j−1 − e_j−1d_j,

(1)

where Δτ_j is the time deviation between the current and the ideal sampling time, e_j is error-direction value, and d_j is the data value. Other information is discarded, and CDR holds the current phase. However, the discarded cases include information about sampling distance, equal to the clock skew between the multiphase clocks of the TI-ADC. The authors of [19] used the following equation to get skew information:

Δτ_j = e_jd_j−1 + e_j−1d_j.

(2)

However, although the method of using CDR discarded cases to obtain skew information can reduce hardware overhead, it may encounter the more serious problem of less information, and more cycles need to be accumulated to obtain information than the autocorrelation method.

2. Proposed CDR-Based Timing Calibration

For high-speed interconnection of integrated circuit chip applications, a low-cost and low-power solution is required. Thus, a timing mismatch calibration process based on existing circuits is preferred. In this work, we propose a new TI-ADC timing mismatch calibration scheme using the autocorrelation principle combined with existing MM-CDR.

Figure 2a takes a two-channel ADC as an example to explain the data correlation between channels. Suppose that channel 0 captures input signal x₀ at time t₀ and input signal x₂ at time t₂, while channel 1 captures input signal x₁ at time t₁. Then, the correlation of the sampled data in the two adjacent channels can be expressed as follows:

$$E\left(x_0{x}_1\right)=E\left(x\left(t\right)·x\left(t+T_S+\Delta T\right)\right)=R\left(T_S+\Delta T\right)\approx R\left(T_S\right)+\Delta T{\frac{dR\left(\tau \right)}{d\tau }|}_{\tau =T_S}.$$

(3)

E(x₁x₂) can be obtained in the same way. By calculating E(x₁x₂) − E(x₀x₁), the information related to the deviation ΔT at the sampling time can be obtained. However, there is a multiplication operation in this scheme, which cannot meet the requirement of low- complexity error extraction. The authors of [17] showed that the value of |x₂ − x₁| − |x₁ − x₀| is also proportional to ΔT. Therefore, by extracting the information of |x₂ − x₁| − |x₁ − x₀|, the sampling time deviation can be extracted, as shown in Figure 2b, avoiding the use of the multiplication unit.

2.1. Timing Mismatch Effect in CDR

When TI-ADC is used in a high-speed wireline receiver, CDR is often used to adjust the optimal sampling time of TI-ADC S/H in the digital domain by accumulating Mueller–Müller phase detector output to update a phase interpolator code shown in Figure 3. The digital CDR loop framed by the blue dotted line includes a Mueller–Müller phase detector, decimation block, frequency integrator, phase integrator, and phase interpolator. The skew loop framed by the red dotted line is our proposed method of reusing MMPD data to extract skew information, which is described in detail later.

In the ADC-based receiver system, the CDR loop needs to average the phase information from all the sub-ADCs in order for frequency and phase integrators in the digital domain to work normally; thus, it averages the timing mismatch. However, even if the average sampling phase is at the desired position, each sub-ADC may sample earlier or later. This loop’s averaging feature mixes all the phase information and essentially hides timing mismatches. Hence, we can add a skew loop based on MM-PD to send the skew information to the skew calibration logic shown in Figure 3, and then the skew calibration logic can adjust the delay cell embedded in four parallel sub-ADCs.

2.2. Timing Mismatch Detection Based on MM-PD

In most high-speed links, due to the fact that the digital clock is much slower than the symbol rate, it is necessary to convert high-speed serial data into multiple parallel data and send it to the digital domain for calculation. In addition, it is common practice that the number of the digital parallel lanes is an integer multiple of the number of sub-ADCs. Thus, each digital lane can be associated with a specific sub-ADC. With this insight, the output of every digital lane can be used for timing skew identification. In this work, we add a skew loop in the MM-CDR, adopting the autocorrelation principle to get the skew information by using the MM-PD error-direction information shown in Figure 4. This scheme solves the drawback of traditional autocorrelation methods without requiring additional circuits and saves hardware overhead due to the use of sign–sign error-direction information.

We can see from the Figure 4 that Data <1:64> and Error <1:64> can be associated with a specific sub-ADC. d₁, d₅, …, d₆₁ and e₁, e₅, …, e₆₁ correspond to the first sub-ADC. d₂, d₆, …, d₆₂ and e₂, e₆, …, e₆₂ correspond to the second sub-ADC, and so on. Therefore, in this work, the symbol information in the MM-PD in the CDR loop is shared to extract the sampling time deviation information from different channels completed in the skew loop.

e_j can be expressed as

$$e_j=x_j-d_{j}h\left(\tau \right),$$

(4)

where x_j is the output value of ADC.

From Equation (4), we can know that e_j contains information of the output signal x_j. Thus, it is also a preferable method to use e_j instead of x_j to obtain skew information, which can be expressed as

$$\begin{array}{ll}E\left(e_j{e}_{j+1}\right)& =E\left\{\left[x_j-d_{j}h\left(\tau \right)\right]\left[x_{j+1}-d_{j+1}h\left(\tau \right)\right]\right\} \\ & =E\left(x_j{x}_{j+1}\right)-h\left(\tau \right)E\left(x_j{d}_{j+1}-x_{j+1}{d}_j\right)+h^2\left(\tau \right)E\left(d_j{d}_{j+1}\right).\end{array}$$

(5)

Therefore, compared with E(x_jx_j+1), E(e_je_j+1) will also be affected by h(τ)E(x_jd_j+1 – x_j+1d_j) – h²(τ)E(d_jd_j+1). Considering that d_j is a decision value obtained as a function of x_j, if the noise of the signal is large enough to affect the decision of d_j, the performance of E(e_je_j+1) will also be affected.

From the perspective of further simplifying the design, this work adopts |e_j+1 – e_j| − |e_j – e_j−1| to achieve skew information. According to the above theoretical analysis, we deal with the value of error-direction for skew detection. Five adjacent error items are taken at each point (e.g., e₁, e₂, e₃, e₄, and e₅), before subtracting two adjacent error items and taking the absolute value of the result (|e₂ – e₁|, |e₃ – e₂|, |e₄ – e₃|, and |e₅ – e₄|). In the same way, the five adjacent error terms of the next group are taken (e₅, e₆, e₇, e₈, and e₉), before subtracting two adjacent error items and taking the absolute value of the result (|e₆ – e₅|, |e₇ – e₆|, |e₈ – e₇|, and |e₉ − e₈|), and so on. Lastly, the absolute value of the same path is accumulated to get the skew information Esum1–4. Esum1 represents the cumulative result of the deviation of the sampling time between the second and the first ADC, where Esum2–4 have the same meaning as Esum1.

In order to verify the effectiveness of using error-direction information e_j to extract skew information, we built a Simulink model, and we also added the method using the output result x_j of ADC for comparison. Because the skew information is extracted using a statistical method, we observed the skew difference in the size of the output signal by setting different statistical times for each iteration cycle and artificially setting the fixed skew size and the noise of the input signal. In this simulation, we added skews of different sizes to the second ADC, and we counted the size of the cumulative results that can be obtained using the ADC output result |x₃ − x₂| − |x₂ − x₁| and the error-direction information |e₃ − e₂| − |e₂ − e₁|. Figure 5a,b show that the cumulative number of output signals is directly proportional to the size of skew and the statistical time of each iteration cycle, where Tck is the period of each of the clocks and ΔT/Tck reflects the size of skew. As long as the cumulative number of |e₃ − e₂| − |e₂ − e₁| and skew can maintain a linear relationship, it does not affect the judgment of the skew size, and the performance of the ADC affected by timing mismatch is only limited by the step of calibration.

We also plot the accumulated numbers of |x₃ − x₂|, |x₂ − x₁|, |e₃ − e₂|, and |e₂ − e₁| to illustrate the accuracy and sensitivity of the method in Figure 6a,b. We can see that, under each skew condition, the values of |x₃ − x₂|, |x₂ − x₁|, |e₃ − e₂|, and |e₂ − e₁| increase linearly with simulation time. Hence, we can define an expression to compare the sensitivity of different methods. For x_j, sensitivity is equal to (|x₃ − x₂| − |x₂ − x₁|)/[(|x₃ − x₂| + |x₂ − x₁|)/2], where the numerator (|x₃ − x₂| − |x₂ − x₁|) reflects the size of the extracted skew, and the denominator (|x₃ − x₂| + |x₂ − x₁|)/2 reflects the size of accumulated numbers without skew. Similarly, the sensitivity is equal to (|e₃ − e₂| − |e₂ − e₁|)/[(|e₃ − e₂| + |e₂ − e₁|)/2] when using e_j to extract skew information. According to Figure 6a,b, when the sizes of skew were set to 5%, 2.4%, and 0.4%, the sensitivities using x_j were equal to 0.140, 0.074, and 0.014, and the sensitivities using e_j were equal to 0.713, 0.409, and 0.077, respectively.

In the Simulink model, in addition to the clock jitter and circuit thermal noise, we consider the effect of second harmonic distortion (HD2) and third harmonic distortion (HD3) caused by ADC non ideal factors. We add a function of y = x + ax² + bx³ before the T&H input to simulate different sizes of HD2 and HD3 and observe the difference in output results under the same skew. In this simulation, we set a skew of 0.5 ps only for clk Q, and a and b were set to the same size, increasing from 0 to 0.15. As shown in Figure 7a, the spurious free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) decreased with the increase in a and b. However, as shown in Figure 7b, with the increase in a and b, although the absolute values of Esum1–4 were slightly affected, the relative relationship among Esum1–4 was not affected; hence, the judgment of skew size was consistent, and higher harmonics had little effect on using e_j for skew extraction.

In the Simulink model, we also set different sizes of skew for the four-way T&H clock of TI-ADC to observe how the size of skew would affect the performance of ADC. In this simulation, we added skew to the Q and Qb clocks, leaving the I and Ib clocks at their ideal positions. As can be seen from Figure 8a,b, a larger skew led to a faster decline in SFDR and SNDR of ADC. In order to obtain better ADC performance, the size of the skew needs to be calibrated within 100 fs. Monte Carlo simulations of the 8 GHz clock paths in this design suggest that, for a maximum mismatch of 0.8 ps, the delay tuning range should be wide enough to accommodate the maximum mismatch. Thus, we set 32 delay cell units to realize a −0.8 to 0.8 ps skew correction range with a 50 fs step for each delay cell.

2.3. Timing Mismatch Calibration

After skew information Esum1–4 is extracted, a reasonable timing mismatch calibration is required, which can be implemented in either the foreground or the background. Foreground calibration may be used in an environment where circuit performance remains stable [6]. However, in applications where circuit parameters vary or where disconnecting the ADC is not an option, such as in serial links, foreground calibration is not a practical solution. Background calibration enables continuous calibration of the correction parameters with the ADC running uninterrupted in normal operation as adopted in this work.

In this work, the skew time calibration consisted of skew calibration logic and an analog variable delay line. The skew calibration logic received the Esum1–4 signal sent by the skew detection, discriminated the skew of different sub-ADCs, and adjusted the delay line. Each delay cell embedded in four parallel sub-ADCs consisted of 32 delay cell units, and the initial setting was half open, such that the delay cell could move forward or backward at the sampling time by opening or closing the delay cell unit. If there is no skew among the four ADCs, the values of Esum1–4 should be approximately equal. On the contrary, if there is a skew among the four ADCs, then the value of Esum1–4 should differ. According to this basic principle, we can set the skew calibration logic. First, we calculated the average value of Esum1–4 and set the difference Edif1–4 between Esum1–4 and its average value Eave. Secondly, we judged whether the difference Edif1–4 was less than the threshold Eth. If the absolute difference Edif1–4 for Esum1–4 is less than the threshold Eth, this indicates no skew. If the absolute difference Edif1–4 is more than Eth, this indicates the presence of skew. The third step is to determine in turn whether the multiplication of two adjacent items of Edif1–4 is less than 0 and to adjust the delay cell according to the results of Edif1–4. After the delay cell is adjusted, Esum1–4 is cleared and accumulated again repeatedly until Edif1–4 is less than Eth. The complete calibration logic is shown in Figure 9.

3. Simulation Results

To verify the effectiveness of our proposed skew calibration method, we implemented a complete 32 Gb/s ADC-based receiver circuit based on 28 nm CMOS technology. Figure 10 is the layout of our complete RF transceiver chip, where the red box is our wireline transceiver circuit, which includes four-lane transmit circuits, a PLL circuit, and four-lane ADC-based receiver circuits. It can be seen from Figure 10 that the ADC-based receiver circuit included a T-coil inductor, PPF/divider, DCD/QED, DCC/QEC, phase interpolator, CTLE, T/H, delay cell, and 32-way time-interleaved SAR ADC implemented with analog circuits. The data demux, DSP, MM-CDR, and skew calibration logic are implemented in the digital domain. The whole ADC-based receiver with the exception of the DSP and MM-CDR occupied an area of 0.34 mm × 0.8 mm, and the area of the TI-ADC only occupied 0.0648 mm². According to the post-simulation results, it was determined that the power consumption of the TI-ADC was 82.6 mW.

To verify the robustness of extracting skew information using error-direction information e_j and the convergence of the calibration loop, we compared the calibration loop convergence for the signals with different amplitude of the noise under the same skew initial setting, where A_noise is the amplitude of the noise, and A_signal is the amplitude of the signal. In the Simulink model and AMS digital–analog hybrid post-simulation, we set each skew information iteration cycle to 4 µs and the initial skew setting to +0.4 ps to the first ADC, +0.2 ps to the second ADC, −0.59 ps to the third ADC, and 0 ps to the fourth ADC. Figure 11a shows the cumulative number of Esum1–4 in each iteration, and Figure 11b shows the time behavior of the delay cells. We can observe that the loop settled in 24 cycles, and Esum1–4 was approximately equal. For comparison, Figure 12a shows that, when the noise amplitude was increased tenfold, whereby the cumulative number of Esum1–4 in each iteration became smaller under the same skew condition. Although the difference among Esum1–4 decreased, the relative relationship of error information could be accurately reflected. It can be seen from Figure 12b that the switch of the delay cell was consistent with the first low-noise case, and Esum1–4 eventually converged to almost the same number.

Figure 13a,b display the simulated output spectrum before and after skew calibration, respectively, with a 15.84375 GHz input before and after calibration. As can be seen from Figure 13a,b, when the initial skew was set for the clocks of the four ADCs, the SFDR and SNDR of the ADC were 37.24 dB and 31.28 dB, respectively. After skew calibration, it can be seen that the SFDR increased to 48.07 dB, and the SNDR increased to 34.56 dB. Therefore, the quality of skew performance was crucial to the performance improvement of the TI-ADC [22,23].

Table 1. Performance comparison of state-of-the-art TI-ADC wireline receiver.

Reference	[12]	[13]	[19]	[22]	[23]	This Work
Technology	65 nm CMOS	40 nm CMOS	10 nm CMOS	40 nm CMOS	14 nm CMOS	28 nm CMOS
Architecture	8 TI FLASH ADC	8 TI SAR ADC	8 × 4 TI SAR ADC	4 × 4 TI FLASH ADC	2 TI FLASH-SAR	4 × 8 TI SAR ADC
Sampling rate (GS/s)	12	36	28	20	10	32
Resolution (bits)	5	4	7	6	8	6
SNDR (dB) @ Nyquist Frequency	25.1	18.6	-	30.1	37.2	34.56
Supply (V)	1.1	0.9/1.2/1.8	0.75/0.85/1.2	0.9	0.8	0.9/1.4
Area (mm2)	1.3 0.44 *	5.328	0.72	0.1 *	0.285 *	0.272 0.0648 *
Power (mW)	81 *	780 *	107.8 40.88 *	56.2 *	14.8 *	82.6 *

* Only TI-ADC part.

summarizes the comparison of our ADC-based wireline receiver circuit with previously published results for TI-ADCs. Our work achieved a relatively good SNDR after the proposed skew calibration. Since we added a low dropout regulator (LDO) to improve the stability of the power supply, the power consumption of our circuits was not greatly reduced, but the compact and reasonable layout still afforded an excellent area advantage.

Lastly, in order to show that our proposed skew calibration method could optimize the circuit area and power consumption performance, we also performed back-end synthesis for several traditional skew calibration expressions through the 28 nm technology. The authors of [12] presented the method using x_j × x_j−1, the authors of [13] presented the method using |x_j − x_j−1|, and the authors of [19] presented the method using e_jd_j−1 + e_j−1d_j. The performance comparison of these four different approaches to skew information extraction is shown in

Table 2. The performance of different skew extraction formulas.

Skew Extraction Formula	Proposed	|xj − xj−1|	xj × xj−1	ejdj−1 + ej−1dj
Sensitivity per 1% skew	0.193	0.034	0.007	0.089
Area (μm2)	695	2850	5236	1128
Power (mW)	0.126	0.446	0.867	0.163

. As can be seen from Table 2, using the proposed |e_j − e_j−1| to extract skew, the area was the smallest and the power consumption was the lowest, at 695 μm² and 0.126 mW, respectively. Referring to the expression of sensitivity in Figure 6, we can see that the proposed method could obtain the highest skew extraction sensitivity. Therefore, using error-direction information e_j is of great significance to reduce the area and power consumption of the high-speed TI-ADC-based wireline receiver.

4. Conclusions

In this paper, we proposed a novel timing mismatch calibration method for TI-ADC. This novel calibration method implemented the autocorrelation principle combined with existing MM-CDR circuits. Using our proposed method, we can perform real-time skew calibration of the TI-ADC with little hardware overhead since we reuse the information in the MM-CDR. A 6 bit 32 GS/s 4 × 8 TI SAR ADC employing the proposed calibration method using 28 nm CMOS technology was presented. It exhibited an SNDR of 34.56 dB and an SFDR of 48.07 dB with a 15.84375 GHz input after skew calibration. The whole ADC-based receiver with the exception of the DSP and MM-CDR occupied an area of 0.34 mm × 0.8 mm, while the 32 GS/s 4 × 8 TI SAR ADC only occupied 0.0648 mm² and consumed 82.6 mW. By comparing different skew calibration methods, the maximum response sensitivity to skew deviations could be achieved with minimal area and power consumption advantages. Our calibration method provides a new inspiration for TI-ADC-based wireline receivers to eliminate multichannel ADC timing mismatch.