A Review of the Gate-All-Around Nanosheet FET Process Opportunities
Abstract
:1. Introduction
2. Integration of Gate-All-Around Nanosheet FETs
- Stacked nanosheet formation: a stack of SiGe and Si are epitaxially grown on the Si substrate; the thickness of each layer can be controlled with high precision.
- Fin reveal and STI: the devices are lithographically defined and shallow trench isolation is performed to isolate neighboring devices.
- Dummy gate formation: a poly silicon dummy gate is formed to enable downstream processing.
- Inner Spacer and Junction formation: n-type or p-type source/drain epitaxial layers are selectively formed on either sides of the exposed nanosheet ends [25].
- Replacement metal gate formation:
- Dummy gate pull: the dummy gate is etched out to reveal a cavity, at the bottom of which nanosheets are located,
- Sacrificial SiGe channel release: the SiGe channels in between the nanosheets are etched out to enable filling up with high-k metal gate,
- High-k Metal Gate (HKMG) formation: an interfacial oxide, a high-k dielectric layer, and the n-type or p-type work functions are selectively deposited.
3. Full Bottom Dielectric Isolation
3.1. Integration
3.2. Experiments
3.3. Results and Discussion
4. Channel Geometry Impact
4.1. Experiments
4.2. Results and Discussion
5. Enabling Multiple Threshold Voltages
5.1. Integration
Volumeless Multiple Threshold Voltages
5.2. Results and Discussions
6. Current Challenges
7. Future Outlook
8. On the Horizon
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
Abbreviations
GAA FETs | Gate-All-Around Field Effect Transistors |
BDI | Bottom Dielectric Isolation |
STI | Shallow Trench Isolation |
WFM | Work Function Metal |
HKMG | High-k Metal Gate |
SCE | Short Channel Effects |
RMG | Replacement Metal Gate |
PTS | Punch Through Stopper |
MOL | Middle of Line |
BEOL | Back End of Line |
S/D | Source/Drain |
DIBL | Drain Induced Barrier Lowering |
TEM | Transmission Electron Microscopy |
VTFET | Vertical Transport Field Effect Transistors |
PPA | Power, Performance, and Area |
BPR | Buried Power Rail |
BSPDN | Back-Side Power Delivery Network |
CPP | Contact Poly Pitch |
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Mukesh, S.; Zhang, J. A Review of the Gate-All-Around Nanosheet FET Process Opportunities. Electronics 2022, 11, 3589. https://doi.org/10.3390/electronics11213589
Mukesh S, Zhang J. A Review of the Gate-All-Around Nanosheet FET Process Opportunities. Electronics. 2022; 11(21):3589. https://doi.org/10.3390/electronics11213589
Chicago/Turabian StyleMukesh, Sagarika, and Jingyun Zhang. 2022. "A Review of the Gate-All-Around Nanosheet FET Process Opportunities" Electronics 11, no. 21: 3589. https://doi.org/10.3390/electronics11213589