A Low-Power, Fast-Transient Output-Capacitorless LDO with Transient Enhancement Unit and Current Booster

Abstract

With the wide application of advanced portable devices, output-capacitorless low dropout regulators (OCL-LDO) are receiving increasing attention. This paper presents a low quiescent current OCL-LDO with fast transient response. A transient enhancement unit (TEU) is proposed as the output voltage-spike detection circuit. It enhances the transient response by improving the slew-rate at the gate of the power transistor. In addition, a current booster (CB), which consists of a current subtractor and a non-linear current mirror, is designed to improve the slew-rate further. The current subtractor increases the transconductances of the differential-input transistors to obtain a large slewing current, while the non-linear current mirror further boosts the current with no extra quiescent current consumption. The simulated results show that the proposed OCL-LDO is capable of supplying 100 mA load current while consuming 10.3 μA quiescent current. It regulates the output at 1 V from a supply voltage ranging from 1.2 to 1.8 V. When the load current is stepped from 1 mA to 100 mA in 100 ns, the OCL-LDO has attained a settling time of 190 ns, and the output voltage undershoot and overshoot are controlled under 110 mV.

1. Introduction

Low dropout regulator (LDO) is an integral part of electronic systems. An external capacitor is widely used in the traditional LDO to stabilize the feedback loop and improve the transient response. Output-capacitorless low-dropout regulators (OCL-LDOs) have received much attention recently, due to the increasing demand for system-on-chip (SoC) [1,2,3,4]. Removal of the bulky off-chip capacitor saves the printed-circuit-board (PCB) space [5]. However, the transient response performance of the OCL-LDO may be degraded without the microfarad output capacitor.

Typically, transient variations of OCL-LDOs depend on the slew-rate conditions at the gate of the power transistor and the closed-loop bandwidth [6,7,8,9]. Some compensation techniques, for example, DFC [10] and Q-reduction [11] can extend the loop bandwidth with a small on-chip capacitor, while they are both limited by the minimum load current. A tri-loop OCL-LDO based on the FVF (flipped voltage follower) structure in [12] is capable of achieving ultra-fast transient response due to the wide bandwidth, but the loop gain is insufficient. Thus, the fast transient OCL-LDO may suffer from the poor regulation. Usually, a wide unity-gain bandwidth means there will be a large quiescent current [13,14]. The OCL-LDO in [15] achieved both the wide bandwidth and the high DC gain by utilizing multiple feedback loops, at the expense of on-chip capacitance and quiescent current [16]. A fast-transient OCL-LDO using active-feedback and current-reuse feedforward compensation was presented in [17], but it also consumed a high quiescent current. Current efficiency, which refers to the ratio of load to input current, determines operational life in the world of portable electronics [18,19]. The ultralow-power OCL-LDO in portable devices can prolong the battery life at the sacrifice of transient performance [20]. The capability to drive the power transistor can be enhanced by utilizing a high slew-rate class-AB amplifier, which will result in an improved transient performance [21]. The slew-rate enhanced circuit can also improve the slew-rate at the gate of the power transistor during the transient response; however, it may be detrimental to the loop stability [22]. Therefore, the tradeoffs between stability issues, transient performance, and quiescent current consumption are still challenges for designers.

This paper presents a low-power, fast-transient response OCL-LDO with a high slew-rate class-AB error amplifier. Section 2 introduces the basic characteristics of the proposed TEU and CB. The loop stability and transistor-level design considerations are also discussed. In Section 3, the post-simulation results and discussion are presented. Finally, the conclusion is drawn.

2. Proposed LDO Topology

Figure 1 shows the conceptual schematic of the proposed fast transient OCL-LDO. The OCL-LDO consists of a high slew-rate error amplifier and a pass element M_pass. The capacitor C_P represents the gate parasitic capacitor of the power transistor. Gm cells, the proposed transient enhancement unit (TEU) and the current booster (CB) construct the high slew-rate error amplifier. The TEU and the CB consume a low quiescent current at steady state. The TEU senses the output variation and transfers it to a transient bias current of Gm cells during the load current transitions. Consequently, I_in+ decreases and I_in− increases rapidly. Then, I_in− will be boosted several times to quickly discharge C_p through the current booster. Thus, a fast transient response can be achieved. The circuit implements and considerations will be discussed in detail in the following subsections.

2.1. Transient Enhancement Unit (TEU)

The Gm cell presented in [24] is shown in the red dashed box in Figure 2a. I_B+ and I_B− are the constant tail current source and the four transistors have the same sizes (W/L). V_REF and V_OUT are the input voltage of the Gm cell. The output currents I_out− and I_out+ are not limited by the tail current source and have a quadratic dependence on (V_OUT−V_REF), where I_out− can be expressed as:

$${\mathrm{I}}_{\mathrm{OUT}-}=\frac{1}{2}{\mathsf{\mu }}_{\mathrm{p}}{\mathrm{C}}_{\mathrm{ox}}\frac{\mathrm{W}}{\mathrm{L}}{{(\mathrm{V}}_{\mathrm{OUT}}{-\mathrm{V}}_{\mathrm{REF}}+\sqrt{\frac{{2\mathrm{I}}_{\mathrm{B}}}{{\mathsf{\mu }}_{\mathrm{p}}{\mathrm{C}}_{\mathrm{ox}}\frac{\mathrm{W}}{\mathrm{L}}}})}^2$$

(1)

where ${\mathsf{\mu }}_{\mathrm{p}}$ is the mobility of carriers, ${\mathrm{C}}_{\mathrm{ox}}$ is the gate-oxide capacitance per unit area and I_B, which is the constant current source, is equal to I_B+ and I_B−. However, the slew-rate is still limited by the transconductance of the differential-input transistors. A large tail current I_B− can be used to boost the transconductance of the differential-input transistors, but the quiescent current is also increased.

The proposed TEU acts as an output voltage detector [25,26], as shown in the pink box in Figure 2a. It consumes no additional quiescent current and provides a large slewing current during the transient response. Figure 2b shows the operational principle comparison of the two structures in Figure 2a. When the load current steps down, Cf senses the output positive voltage spike (V_OUT-V_REF) so that the gate voltage of M_2A goes down and the gate voltage of M_2B goes up. Then, I_B− rises while V_REF is a constant, which will lead to the voltage drop of V_L. As the source voltage of M_L2 (V_OUT) increases and the gate voltage of M_L2 (V_L) decreases, the voltage difference between its source and gate is much higher than it is in the red box in Figure 2a, resulting in a higher I_out−. At the same time, the increase of V_OUT contributes to a much more significant increase in V_H than it is in the red box in Figure 2a, due to the decrease of I_B+. Thus, I_out+ in the green dashed box is much lower than it is in the red dashed box in Figure 2a. The bias current of M_fA and M_fB is I_B. M_2A and M_2B are both biased in the subthreshold region in this work, and the total transient current in M_L1 can be expressed as:

$${\mathrm{I}}_{\mathrm{B}-}{=\mathrm{I}}_{\mathrm{B}}{+\mathrm{k}*\mathrm{I}}_{\mathrm{S}0}{\left(\frac{\mathrm{W}}{\mathrm{L}}\right)}_{\mathrm{M}2\mathrm{B}}{\mathrm{e}}^{\frac{{\mathrm{V}}_{\mathrm{OUT}}{-\mathrm{V}}_{\mathrm{REF}}}{{\mathrm{nV}}_{\mathrm{T}}}}{(1-\mathrm{e}}^{\frac{{\mathrm{V}}_{\mathrm{DS}2}}{{\mathrm{V}}_{\mathrm{T}}}}{\left)\right(1+\mathsf{\lambda }}_{\mathrm{sub}}{\mathrm{V}}_{\mathrm{DS}2})$$

(2)

where k is a constant, V_DS2 is the drain-source voltage of M_2B. I_S0, n, and λ_sub are the process-related parameters.

It can be seen that I_B- is equal to I_B at steady state, i.e., V_OUT-V_REF = 0. When V_OUT varies during the transient response, I_B− will change quickly. As a result, the slewing current I_OUT− is boosted and can be expressed as:

$${\mathrm{I}}_{\mathrm{OUT}-}=\frac{1}{2}{\mathsf{\mu }}_{\mathrm{p}}{\mathrm{C}}_{\mathrm{ox}}\frac{\mathrm{W}}{\mathrm{L}}{{(\mathrm{V}}_{\mathrm{OUT}}{-\mathrm{V}}_{\mathrm{REF}}+\sqrt{\frac{{2\mathrm{I}}_{\mathrm{B}-}}{{\mathsf{\mu }}_{\mathrm{p}}{\mathrm{C}}_{\mathrm{ox}}\frac{\mathrm{W}}{\mathrm{L}}}})}^2$$

(3)

Based on Equations (1)–(3), the proposed TEU achieves a higher I_out− or I_out− during the output current transitions, while no extra quiescent current is generated, as shown in Figure 3. Assuming M_H1, M_H2, M_L1, and M_L2 have the same sizes, and V_OUT = V_REF when operating at a steady state, the output current of Gm cells is equal to I_B, with or without TEU structure. The transient output current in the proposed TEU structure is higher than that in the classical structure, with the same output voltage variation (V_OUT-V_REF).

2.2. Current Booster

Current mirrors are widely used in Class-AB OTA topologies [27]. Figure 4a illustrates the classical current mirror structure. M₁ and M2 are both in the saturation region, and the ratio of the output current I_out1 to the input current I_in1 is equal to the scale factor A.

The nonlinear current mirror structure is applied to maintain a low quiescent current and boost the output current when I_in increases. Figure 4b shows that the nonlinear current mirror is implemented by adding transistor M₃. The bias voltage V_B is set to ensure that the transistor M₁ operates near the ohmic region, i.e., V_DS is slightly higher than V_DS,sat. V_x will decrease when I_in increases due to the fixed bias voltage V_B. Hence, the drain-source voltage of M₁ is lower than its V_DS,sat, which will drive it to the ohmic region. The current boosting is realized as long as M₂ is in the saturation region. Because the V_DS is low, the drain-source voltage of M₁ can be approximately expressed as:

$${\mathrm{V}}_{\mathrm{DS}1}{=\mathrm{V}}_{\mathrm{B}}{-\mathrm{V}}_{\mathrm{GS}3}{=\mathrm{V}}_{\mathrm{B}}-(\sqrt{\frac{{2\mathrm{I}}_{\mathrm{in}}}{{\mathrm{u}}_{\mathrm{n}}{\mathrm{C}}_{\mathrm{ox}}{\left(\frac{\mathrm{W}}{\mathrm{L}}\right)}_{\mathrm{M}3}}}{+\mathrm{V}}_{\mathrm{THN}})$$

(4)

where u_n and C_ox are the process-related parameters and V_THN is the threshold voltage of M₃. V_DS1 decreases as I_in rising. The output current I_out2 can be expressed as:

$${\mathrm{I}}_{\mathrm{out}2}=\frac{{\mathrm{AI}}_{\mathrm{in}}^2}{{2\mathrm{u}}_{\mathrm{n}}{\mathrm{C}}_{\mathrm{ox}}{\left(\frac{\mathrm{W}}{\mathrm{L}}\right)}_{\mathrm{M}1}{\mathrm{V}}_{\mathrm{DS}1}^2}$$

(5)

where A is the scale factor. I_out2 is larger than the output current I_out1 of the traditional current mirror structure in Figure 4a.

Figure 5 shows the simulated dc responses of the traditional current mirror and the nonlinear current mirror at A = 2. If the bias voltage V_B is biased properly to make M₁ near the ohmic region, the output current will boost as I_in increases, even with a small scale factor.

2.3. Circuit Implementation

The transistor-level schematic of the proposed OCL-LDO is shown in Figure 6. A unity-gain buffer is applied between the voltage reference V_ref and the input of the OCL-LDO core, because many voltage references cannot provide the output current. The tail current in the transistor M_B9 is set to 200 nA as the buffer does not require a high slew-rate. In this design, the bias current I_B is set to 500 nA. A current subtractor [28] is introduced in the current booster to enhance the transconductance of the Gm cells. The size of M_H1 (M_L1) is twice as large as M_H2/M_H3 (M_L2/M_L3) to set the bias point of the current booster. For a differential-input voltage ΔV_in, the output current in M₁₁ is 1.5gmΔV_in so that the transconductance of the Gm cell is enhanced by 1.5 times. The larger transconductance of the Gm cell contributes to the larger bandwidth and the higher slewing current at the gate of the power transistor, which can improve the performance of the transient response. The transistors M_2A and M_2B of the TEU, which are operating in the subthreshold region, can optimize the bandwidth, and this will be explained in the following part. The ratios of M12 to M11 and M7 to M6 are set to 4/1 to further improve the slew-rate. A miller capacitor C_c is added between the gate of the power transistor M_pass and V_out to guarantee stability under full load conditions. Thus, this OCL-LDO is stable under full load conditions, and the maximum load capacitor C_L is 100 pF. The size of the power transistor M_pass is 8000 um/0.18 um, so that it will operate in the ohmic region under the heavy load condition and in the subthreshold region under the light load condition.

2.4. Stability Analysis

A loop transfer function is derived to evaluate the effect of the proposed transient enhancement unit on the loop stability. Figure 7 shows a small signal block diagram representing the structure in Figure 6. Hence, g_mH and g_mL are the transconductances of two Gm cells. g_mp, g_m2, and g_mf represent the transconductances of the power transistor M_pass, M_2A/M_2B, and M_fA, respectively. The small-signal impedance at the output of the error amplifier and V_out are denoted as R_o1 and R_L (~1/g_m), respectively. For the proposed OCL-LDO, it is reasonable to assume R_o1 >> R_L. The lumped parasitic capacitances at the gate of the power transistor and the output V_out are modeled as C_g and C_L, respectively. Typically, C_g consists of the gate-source parasitic capacitor (C_gs) and the equivalent capacitor because of the miller effect of the gate-drain capacitor (C_gd). R_of and C_of are the small-signal output impedance and the lump parasitic capacitance at the gate of transistor M_2A/M_2B, respectively. The loop transfer function can be derived and simplified based on the assumption that C_L, C_g, and C_f are much larger than C_of.

The loop gain transfer function of the proposed OCL-LDO is:

$$\mathrm{T}\left(\mathrm{s}\right)=\frac{{\mathrm{V}}_{\mathrm{out}}\left(\mathrm{s}\right)}{{\mathrm{V}}_{\mathrm{fb}}\left(\mathrm{s}\right)}=\frac{{-\mathrm{T}}_{\mathrm{DC}}·\mathrm{N}\left(\mathrm{s}\right)}{\mathrm{D}\left(\mathrm{s}\right)}$$

(6)

where T_DC is the DC loop gain and N(s) is related to the frequency, they can be expressed as:

$${\mathrm{T}}_{\mathrm{DC}}{=(\mathrm{g}}_{\mathrm{mH}}{+\mathrm{g}}_{\mathrm{mL}}{)\mathrm{R}}_{\mathrm{o}1}{\mathrm{g}}_{\mathrm{mp}}{\mathrm{R}}_{\mathrm{L}}$$

(7)

$$\mathrm{N}\left(\mathrm{s}\right)=(1-\mathrm{s}\frac{{\mathrm{C}}_{\mathrm{c}}}{{\mathrm{g}}_{\mathrm{mp}}}{\left)\right(1+\mathrm{sR}}_{\mathrm{f}}{\mathrm{C}}_{\mathrm{f}}\left)\right(1+\mathrm{s}\frac{\left({\mathrm{g}}_{\mathrm{mH}}{+\mathrm{g}}_{\mathrm{mL}}{+2\mathrm{g}}_{\mathrm{m}2}\right){\mathrm{R}}_{\mathrm{f}}{\mathrm{C}}_{\mathrm{f}}}{{\mathrm{g}}_{\mathrm{mH}}{+\mathrm{g}}_{\mathrm{mL}}}\left)\right(1+\mathrm{s}\frac{{\mathrm{C}}_{\mathrm{of}}}{{\mathrm{g}}_{\mathrm{mf}}})$$

(8)

The denominator D(s) is:

$$\mathrm{D}\left(\mathrm{s}\right)=\left({1+\mathrm{sR}}_{\mathrm{f}}{\mathrm{C}}_{\mathrm{f}}\right)\left(1+\mathrm{s}\frac{{\mathrm{C}}_{\mathrm{f}}}{{\mathrm{g}}_{\mathrm{mf}}}\right)\left({1+\mathrm{sR}}_{\mathrm{f}}{\mathrm{C}}_{\mathrm{of}}\right)\left\{{1+\mathrm{sR}}_{\mathrm{o}1}{[\mathrm{C}}_{\mathrm{g}}{+(1+\mathrm{g}}_{\mathrm{mp}}{\mathrm{R}}_{\mathrm{L}}{)\mathrm{C}}_{\mathrm{c}}]\right\}[1+\mathrm{s}\frac{{\mathrm{R}}_{\mathrm{L}}\left({\mathrm{C}}_{\mathrm{c}}{\mathrm{C}}_{\mathrm{g}}{+\mathrm{C}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{c}}{+\mathrm{C}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{g}}\right)}{{\mathrm{C}}_{\mathrm{g}}+\left({1+\mathrm{g}}_{\mathrm{mp}}{\mathrm{R}}_{\mathrm{L}}\right){\mathrm{C}}_{\mathrm{c}}}]$$

(9)

From Equations (6)–(9), it is clear that the loop transfer function of the OCL-LDO can be simplified to the classical two-stage amplifier with miller compensation by setting C_f to 0. Equations (8) and (9) imply that four zeros and five poles exist in the whole negative feedback loop. No complex pole exists in the system, and locations of poles and zeros are summarized in

Table 1. Zeros and poles summary.

Zeros	Poles
${\mathrm{z}}_1=+\frac{{\mathrm{g}}_{\mathrm{mp}}}{{\mathrm{C}}_{\mathrm{c}}}$	${\mathrm{p}}_1=-\frac{1}{{\mathrm{R}}_{\mathrm{o}1}{[\mathrm{C}}_{\mathrm{g}}{+(1+\mathrm{g}}_{\mathrm{mp}}{\mathrm{R}}_{\mathrm{L}}{)\mathrm{C}}_{\mathrm{c}}]}$
${\mathrm{z}}_2=-\frac{{\mathrm{g}}_{\mathrm{mH}}{+\mathrm{g}}_{\mathrm{mL}}}{\left({\mathrm{g}}_{\mathrm{mH}}{+\mathrm{g}}_{\mathrm{mL}}{+2\mathrm{g}}_{\mathrm{m}2}\right){\mathrm{R}}_{\mathrm{f}}{\mathrm{C}}_{\mathrm{f}}}$	${\mathrm{p}}_2=-\frac{{\mathrm{C}}_{\mathrm{g}}+\left({1+\mathrm{g}}_{\mathrm{mp}}{\mathrm{R}}_{\mathrm{L}}\right){\mathrm{C}}_{\mathrm{c}}}{{\mathrm{R}}_{\mathrm{L}}\left({\mathrm{C}}_{\mathrm{c}}{\mathrm{C}}_{\mathrm{g}}{+\mathrm{C}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{c}}{+\mathrm{C}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{g}}\right)}$
${\mathrm{z}}_3=-\frac{{\mathrm{g}}_{\mathrm{mf}}}{{\mathrm{C}}_{\mathrm{of}}}$	${\mathrm{p}}_3=-\frac{1}{{\mathrm{R}}_{\mathrm{f}}{\mathrm{C}}_{\mathrm{of}}}$
${\mathrm{z}}_4=-\frac{1}{{\mathrm{R}}_{\mathrm{f}}{\mathrm{C}}_{\mathrm{f}}}$	${\mathrm{p}}_4=-\frac{{\mathrm{g}}_{\mathrm{mf}}}{{\mathrm{C}}_{\mathrm{f}}}$
	${\mathrm{p}}_5=-\frac{1}{{\mathrm{R}}_{\mathrm{f}}{\mathrm{C}}_{\mathrm{f}}}$

.

From Table 1, z₄ and p₅ will cancel each other so that the loop transfer function can be rewritten as:

$$\mathrm{T}\left(\mathrm{s}\right)=\frac{{-\mathrm{T}}_{\mathrm{DC}}(1+\frac{\mathrm{s}}{{\mathrm{z}}_1}\left)\right(1-\frac{\mathrm{s}}{{\mathrm{z}}_2}\left)\right(1-\frac{\mathrm{s}}{{\mathrm{z}}_3})}{(1-\frac{\mathrm{s}}{{\mathrm{p}}_1}\left)\right(1-\frac{\mathrm{s}}{{\mathrm{p}}_2}\left)\right(1-\frac{\mathrm{s}}{{\mathrm{p}}_3}\left)\right(1-\frac{\mathrm{s}}{{\mathrm{p}}_4})}$$

(10)

The dominant pole p₁ and the pole at V_out are established by the effect of Miller capacitor C_c. In addition, z₁ is a right-half-plane (RHP) zero caused by the feedforward small-signal current through the miller capacitor. From Table 1, the locations of the additional poles (p₃, p₄) and zeros (z₂, z₃) introduced by the proposed transient enhancement unit will not be affected by different load conditions. As p₁ and p₂ vary with the output current, the loop stability should be studied for different load conditions.

Under light load conditions, g_mp is relatively small, and g_mpR_L is inversely proportional to $\sqrt{{\mathrm{I}}_{\mathrm{load}}}$. The dominant pole is p₁, which is at a low frequency. A larger C_L indicates that the non-dominant pole p₂ is also at a low frequency. As a result, the frequencies of the p₁ and p₂ are much lower than those of p₃, p₄, and z₃. When the load current is zero and the load capacitor (C_L) is maximum, p₂ will be close to z₂. Thus, the loop acts as a single-pole system. The unity-gain frequency (UGF) can be approximately expressed as:

$$\mathrm{UGF}=\frac{{(\mathrm{g}}_{\mathrm{mH}}{+\mathrm{g}}_{\mathrm{mL}}{)\mathrm{g}}_{\mathrm{mp}}{\mathrm{R}}_{\mathrm{L}}}{{[\mathrm{C}}_{\mathrm{g}}{+(1+\mathrm{g}}_{\mathrm{mp}}{\mathrm{R}}_{\mathrm{L}}{)\mathrm{C}}_{\mathrm{c}}]}$$

(11)

Under medium to heavy load conditions, g_mp becomes quite large due to the large size of M_pass. p₂ moves to a much higher frequency than z₂. There are two poles (p₁, p₂) and one zero (z₂) existing within the UGF. Thus, the stability can be guaranteed by setting the value of R_fC_f. Because of the quite small parasitic capacitor C_of, (several fF), z₃ and p₃ can be assumed to locate at high frequencies and then be ignored. In this case, the UGF is extended due to z₂, and it can be expressed as:

$${\mathrm{UGF}}^{’}=\mathrm{UGF}\frac{{\mathrm{p}}_2}{{\mathrm{z}}_2}=\frac{\left({\mathrm{g}}_{\mathrm{mH}}{+\mathrm{g}}_{\mathrm{mL}}{+2\mathrm{g}}_{\mathrm{m}2}\right){\mathrm{g}}_{\mathrm{mp}}{\mathrm{R}}_{\mathrm{f}}{\mathrm{C}}_{\mathrm{f}}}{\left({\mathrm{C}}_{\mathrm{c}}{\mathrm{C}}_{\mathrm{g}}{+\mathrm{C}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{c}}{+\mathrm{C}}_{\mathrm{L}}{\mathrm{C}}_{\mathrm{g}}\right)}$$

(12)

Equation (12) indicates that p₂ moves to a high frequency as the load current increases, resulting in an increased bandwidth. A higher loop bandwidth means a faster transient response. In other words, the transient enhancement unit acts as a high-pass filter with the dominant pole 1/R_fC_f and determines the loop stability at high frequencies.

Based on the discussion above, the proposed transient enhancement unit introduces an additional LHP zero and extends the bandwidth. Large R_f and C_f contribute to a fast transient response; however, they may be detrimental to the loop stability. In this design, we set R_f = 200 kΩ and C_f = 1.25 pF to guarantee the loop stability under full load conditions. Figure 8a depicts the simulated loop gain of the proposed OCL-LDO for the load capacitance of 100 pF under different load currents (from 0 mA to 100 mA). It can be seen that the proposed OCL-LDO is stable for all load conditions. Process corner and temperature simulations are also implemented to prove the feasibility of the proposed OCL-LDO. As shown in Figure 8b, for different process corners and temperatures (ff −40 °C, ss 125 °C and tt 25 °C), all phase margins of the proposed OCL-LDO are above 35°, under the full range of load currents. Figure 9 demonstrates the Monte Carlo simulation results of the phase margin of the OCL-LDO with C_L = 100 pF when (a) I_load = 10 μA or (b) I_load = 100 mA. Monte Carlo analysis can predict the deviation caused by process and mismatch in the actual circuit. The mean phase margin is 41.5° under light load conditions with a standard deviation of 9.06. Under heavy load conditions, the mean phase margin is 114° with a standard deviation of 5.78. Thus, these prove that the stability of the proposed OCL-LDO can be achieved. The worst stability case occurs when the load current is lowest and the load capacitor is highest.

3. Simulation Results and Discussions

The proposed OCL-LDO is designed and simulated in a 0.18 μm CMOS process. The layout is exhibited in Figure 10, and the whole layout area is approximately 120 × 127 μm. The post-simulation results are shown as follows.

The input voltage range of the proposed OCL-LDO is designed from 1.2 to 1.8 V. The LDO is capable of delivering a current of 100 mA with a dropout voltage of 0.2 V. It is stable when output capacitor values range from 0 to 100 pF. In addition, the OCL-LDO consumes small quiescent current of 10.3 μA and the current efficiency can reach 99.99%. The load regulation is simulated for V_in = 1.2 V, V_in = 1.5 V, and V_in = 1.8 V when V_OUT = 1 V with a 100 pF output capacitor. The line regulation is simulated for different load currents (from 1 μA to 100 mA) when V_OUT = 1 V. As shown in Figure 11a,b, the load regulation and line regulation are 34 μV/mA and 2.74 mV/V, respectively.

The power supply rejection (PSR) was simulated by adding a sinusoidal signal to a dc input voltage of 1.2 V and observing the output [26]. Figure 12 depicts the PSR of the OCL-LDO under different load currents when V_IN = 1.2 V and V_out = 1.0 V.

The load transient response was simulated when the load current is switching from 1 mA to 100 mA, with the rise/fall time of 100 ns, without an output capacitor. As depicted in Figure 13, the maximum output voltage overshoot and undershoot are both less than 110 mV when ${\mathrm{V}}_{\mathrm{o}}$ is 1.0 V. The output voltage variations were about ±10%. The small transient variation under massive load-step is obtained, based on the proposed high-slew rate error amplifier with TEU and CB. Besides, the recovering time is around 190 ns. The large phase margin allows the LDO to achieve the well-behaved settling characteristic.

The line transient response is simulated at I_load = 50 mA with a 100 pF output capacitor. It can assess the impact of the varying input voltage on the output voltage. As shown in Figure 14, when the input voltage changes from 1.2 to 1.8 V with 100 ns rise/fall time, the variation of the output voltage is less than 50 mV.

Table 2. Performance summary and comparison with state-of-the-art OCL-LDOs.

	[6]	[14]	[16]	[17]	[18]	[19]	[20]	This Work
Year	2013	2014	2017	2018	2020	2021	2021	2021
Technology (nm)	350	65	180	130	65	130	180	180
Chip Area (mm2)	0.04	0.0133	0.033	0.0252	0.01	0.029	0.103	0.01524
Input Voltage (V)	1.2–1.5	0.75–1.2	1.8	1.4–2.7	1.05–1.2	1.2	1.297–3.3	1.2–1.8
Output Voltage (V)	1.0–1.3	0.55	1.6	1.2–2.5	0.9	1	1.2	1
Maximum Output Current (mA)	100	50	100	50	20	50	50	100
Quiescent Current (μA)	1.2–14	15.9–487	71–101	65.8	65	95	8.6	10.3
Current Efficiency (%)	99.99	99.03	99.93	99.87	99.68	99.81	99.99	99.99
Load Regulation (mV/mA)	-	0.18	N/A	0.048	-	0.009	0.006	0.034
Line Regulation (mV/V)	-	4	131	1.23	-	5	0.065	2.74
On-chip Capacitor (pF)	0	4.1	12.7	2.6	1.4	10	6.1	7.5
Output Capacitor (pF)	0–100	470–10000	100	0–100	0–100	0–2000	0–50	0–100
Settling Time (μs)	2.7	0.25	0.2	0.69	0.3	0.2	3.6	0.19
FOM (ns)	0.0324	0.0795	0.202	0.90804	0.975	0.38	0.310	0.01957

illustrates the performance comparison with some reported OCL-LDOs, which indicates the performance improvement in the proposed OCL-LDO. The figure of merit ${\mathrm{FOM}=\mathrm{T}}_{\mathrm{settle}}{ \times \mathrm{I}}_{\mathrm{Q}}{/\mathrm{I}}_{\mathrm{MAX}}$ [29] is introduced to compare the transient response of different LDOs, in which ${\mathrm{T}}_{\mathrm{settle}}$, ${\mathrm{I}}_{\mathrm{Q}}$, and ${\mathrm{I}}_{\mathrm{MAX}}$ represent the settling time, the quiescent current, and the maximum load current step, respectively. A smaller FOM means a superior transient performance of the LDO [30]. From Table 2, it can be seen that the proposed LDO achieves a fast transient response and a low quiescent current.

4. Conclusions

In this paper, a fast-transient low-power OCL-LDO has been presented. It can achieve full range stability from 0 to 100 mA load current with a minimum dropout voltage of 200 mV. Furthermore, with the proposed transient enhancement unit and the current booster, a high slew rate can be obtained while consuming a low quiescent current, resulting in fast transient response. The OCL-LDO is implemented in a 0.18 μm CMOS process. The post-layout simulation results show that the undershoot and overshoot are less than 110 mV, and the settling time is shortened to 190 ns even with a large load transient (from 0 to 100 mA). In addition, the proposed design can achieve a 0.01957 ns FoM, which has been significantly improved compared with the previous relevant research.