A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

Abstract

This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm².

1. Introduction

The successive approximation register (SAR) analog-to-digital converter (ADC) is very popular because it can achieve low power and high performance at 100 MS/s with 10 to 13 bits [1,2,3,4,5,6,7,8,9,10]. With the feature sizes of CMOS devices scaled down, the power supply voltage becomes lower and lower, which is not conducive to analog circuits such as high-performance operational amplifiers as the low power supply voltage limits the output swing and gain of the amplifier. However, there are very few analog circuits in a SAR ADC. The SAR ADC is mainly composed of the dynamic comparator, the DAC capacitor array and the digital control logic, which is compatible with advanced CMOS processes.

For an N-bit SAR ADC, the conventional binary-weighted DAC array requires 2^N unit capacitors. The number of unit capacitors increases exponentially with N and they occupy a large area, causing large interconnection parasitism. In addition, the mismatch between the LSB capacitor and MSB capacitor also becomes larger. These adverse factors affect the speed, power dissipation and accuracy of an ADC. A DAC based on a bridge-capacitor array can greatly reduce the number of unit capacitors, which is beneficial to its speed and power. However, the bridge capacitor can cause parasitic capacitance in a DAC, which affects the harmonic distortion and signal-to-noise ratio (SNR). Moreover, the bridge capacitor is not an integer, which is not conducive for matching the layout. An integer bridge capacitor was introduced in [11] to reduce mismatch with other unit capacitors. However, there was still parasitic capacitance in this integer bridge capacitor. Some calibration methods were proposed to compensate for the parasitic capacitance of the bridge capacitor. Histogram-based ratio-mismatch calibration for the bridge DAC is proposed in [12], which required a complex digital circuit and took much time to converge. The uniform quantization theory-based linearity calibration was introduced in [13], which needed an input signal to satisfy the prerogative of quantization theory. The weighting of the capacitors in an MSB array of a bridge DAC was calibrated by the successive approximation method in [14]. However, the error of weighting in the capacitors in an LSB array affects the result of the calibration. Although dynamic element matching (DEM) [15] can reduce the mismatch between unit capacitors and improve linearity, it can not improve the SNR.

With the continuous improvement of the ADC sampling rate, the setting issue of a DAC capacitor array becomes serious, which can result in an incorrect comparison because the reference voltage does not recovered to its initial value before the comparator starts comparing. In order to achieve a settling error within 0.5 LSB, the driving switches should be designed with a stronger driving ability, which consumes more power. Moreover, larger driving switches introduce more parasitic capacitance, which reduces the speed of the ADC. The redundancy can alleviate the settling error of a DAC [16,17,18,19,20,21,22,23,24,25,26,27,28]. The non-binary redundancy [29] needs a complex digital control circuit and an extra an ROM. Moreover, non-binary redundancy makes the floorplan of the layout of a DAC capacitor array difficult, which degrades the matching of the unit capacitors. When the DAC settling error is within the redundancy range, the wrong comparison can be corrected by the binary-scaled-error method [30]. However, introduced capacitors will reduce the quantization range. The capacitors in an MSB array and LSB array of a bridge DAC capacitor array are split respectively [31,32] and the redundancy can be introduced. However, there is no redundancy for the MSB capacitor in an LSB array, which still produces the settling error.

This paper proposes the differential non-linearity calibration method to compensate for the linearity that is degraded by the parasitic capacitance of the bridge capacitor in a DAC capacitor array. Moreover, in order to alleviate DAC settling error and reduce the power, a hybrid redundancy scheme is proposed.

The rest of this article is organized as follows. Section 2 describes the overall architecture of the proposed SAR ADC. The proposed differential non-linearity calibration method and the hybrid redundancy scheme are presented in Section 3. The circuit implementation of the key building blocks is presented in Section 4. Measurement results are presented in Section 5. Finally, Section 6 concludes the paper.

2. SAR ADC Overall Architecture

The overall architecture of the proposed SAR ADC is presented in Figure 1. The bridge DAC capacitor array consists of an 8-bit MSB array and a 4-bit LSB array, which can reduce the number of unit capacitors. The MSB arrays are the M-bit DAC capacitor array and the LSB arrays are the L-bit DAC capacitor array. When M > N, the influence of the parasitic capacitance in the LSB arrays on the linearity of the SAR ADC will be reduced [33]. As a result, we chose M = 8 and L = 4. An integer bridge capacitor Ca was adopted, which was conducive to matching the layout. Successive approximation register (SAR) logic was used to generate and control the signals Dp<15:0> and Dn<15:0>, which could control switches S_p0–S_p14 and S_n0–S_n14 according to the OUTp and OUTn of the comparator output. Digital error correction (DEC) could convert the original 16-bit digital codes to 12-bit binary codes. A calibration capacitor array was used to compensate for the linearity, which was degraded by the parasitic capacitance of the bridge capacitor Ca. The calibration circuit and logic provided the calibration clock CLKcali for the dynamic comparator CMP and the thermometer code thc<14:0> for the calibration capacitor array. The clock driver generated the sampling clock CLK and calibration clock CLK_cali_logic.

3. The Proposed Differential Non-Linearity Calibration Method and Hybrid Redundancy Scheme

3.1. Analysis of Parasitic Capacitance in the Bridge DAC Capacitor Array

Although a bridge DAC capacitor array can reduce the number of unit capacitors, the parasitic capacitance of the bridge capacitor influences the linearity of the SAR ADC. Figure 2 shows a 12-bit bridge DAC capacitor array with parasitic capacitance C_p1 and C_p2. The capacitance C_p2 is composed of the parasitic capacitance from the top plate to the ground of capacitors C4 to C11 and Ca. The capacitance C_p1 is composed of the parasitic capacitance from the top plate to the ground of capacitors C0 to C3 and the parasitic capacitance from the bottom plate to the ground of the capacitor Ca.

In order to reduce the charge injection, bottom-plate sampling was adopted. The purple capacitor C4 was put into the MSB array and it only participated in the sampling process, it did not participate in the quantization process. Only the MSB array samples input the signal Vin, which could reduce input load capacitance. During the sampling period switches S1, S2 and S3 were on. The top plates and bottom plates of capacitors C11 to C4 in the MSB array were connected to Vcm and the input signal Vin, respectively. The top plates and bottom plates of capacitors C0 to C3 were connected to Vcm and the ground, respectively. The charge Q_X at the node X could be expressed as follows:

$${\mathrm{Q}}_{\mathrm{X}}=128{\mathrm{C}}_{\mathrm{u}}{(\mathrm{V}}_{\mathrm{cm}}-{\mathrm{V}}_{\mathrm{in}})+{\mathrm{V}}_{\mathrm{cm}}{\mathrm{C}}_{\mathrm{P}2}$$

(1)

The charge Q_Y at the node Y could be expressed as follows:

$${\mathrm{Q}}_{\mathrm{Y}}=(15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{dum}}){\mathrm{V}}_{\mathrm{cm}}$$

(2)

In the quantization process, it was assumed that M unit capacitors were connected to Vref in the MSB array and N unit capacitors were connected to V_ref in the LSB array. The voltage of the nodes X and Y were V_X and V_Y, respectively. At this time, the charge Q_X at the node X could be expressed as follows:

$${\mathrm{Q}}_{\mathrm{X}}=({\mathrm{V}}_{\mathrm{X}}-{\mathrm{V}}_{\mathrm{ref}}){\mathrm{MC}}_{\mathrm{u}}+(128{\mathrm{C}}_{\mathrm{u}}-{\mathrm{MC}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}2}){\mathrm{V}}_{\mathrm{X}}+({\mathrm{V}}_{\mathrm{X}}-{\mathrm{V}}_{\mathrm{Y}}){\mathrm{C}}_{\mathrm{a}}$$

(3)

The charge Q_Y at the node Y could be expressed as follows:

$${\mathrm{Q}}_{\mathrm{Y}}=({\mathrm{V}}_{\mathrm{Y}}-{\mathrm{V}}_{\mathrm{ref}}){\mathrm{NC}}_{\mathrm{u}}+(15{\mathrm{C}}_{\mathrm{u}}-{\mathrm{NC}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{dum}}){\mathrm{V}}_{\mathrm{Y}}+({\mathrm{V}}_{\mathrm{Y}}-{\mathrm{V}}_{\mathrm{X}}){\mathrm{C}}_{\mathrm{a}}$$

(4)

In the process of charge distribution, the charges Q_X and Q_Y at the nodes X and Y, respectively, remained unchanged. As a result, Equations (5) and (6) could be obtained.

$$128{\mathrm{C}}_{\mathrm{u}}({\mathrm{V}}_{\mathrm{cm}}-{\mathrm{V}}_{\mathrm{ref}})+{\mathrm{V}}_{\mathrm{cm}}{\mathrm{C}}_{\mathrm{p}2}=({\mathrm{V}}_{\mathrm{X}}-{\mathrm{V}}_{\mathrm{ref}}){\mathrm{MC}}_{\mathrm{u}}+(128{\mathrm{C}}_{\mathrm{u}}-{\mathrm{MC}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}2}){\mathrm{V}}_{\mathrm{X}}+({\mathrm{V}}_{\mathrm{X}}-{\mathrm{V}}_{\mathrm{Y}}){\mathrm{C}}_{\mathrm{a}}$$

(5)

$$(15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{dum}}+{\mathrm{aV}}_{\mathrm{cm}})=({\mathrm{V}}_{\mathrm{Y}}-{\mathrm{V}}_{\mathrm{ref}}){\mathrm{NC}}_{\mathrm{u}}+(15{\mathrm{C}}_{\mathrm{u}}-{\mathrm{NC}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{dum}}){\mathrm{V}}_{\mathrm{Y}}+({\mathrm{V}}_{\mathrm{Y}}-{\mathrm{V}}_{\mathrm{X}}){\mathrm{C}}_{\mathrm{a}}$$

(6)

Combining Equations (5) and (6), the voltage V_X at the node X is shown as:

$${\mathrm{V}}_{\mathrm{X}}=\mathrm{L}\left[\frac{{\mathrm{V}}_{\mathrm{ref}}}{2^{12}}(2^5\mathrm{M}+\frac{2^5{\mathrm{NC}}_{\mathrm{a}}}{15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{dum}}+{\mathrm{C}}_{\mathrm{a}}})-{\mathrm{V}}_{\mathrm{in}}\right]+{\mathrm{V}}_{\mathrm{cm}}$$

(7)

$$\begin{array}{l}\mathrm{L}=\frac{128{\mathrm{C}}_{\mathrm{u}}(15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{dum}}+{\mathrm{C}}_{\mathrm{a}})}{(15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{dum}}+{\mathrm{C}}_{\mathrm{a}})(128{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}2})+(15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{dum}}){\mathrm{C}}_{\mathrm{a}}}\\ \end{array}$$

(8)

As can be seen from Equations (7) and (8), the parasitic capacitor C_p2 only appeared on the denominator and did not affect the linearity of the ADC. However, the parasitic capacitor Cp1 appeared on both the numerator and denominator, which affected the linearity of the ADC.

In Equation (7), assuming that C_p1 = 0, C_a= 3 C_u and C_dum = 30 C_u, Equation (9) could be obtained. In Equation (10), b = 2⁵ M + 2 N. In this case, the DAC capacitor array had correct scaling. However, the parasitic capacitor C_p1 could not be ignored. In Equation (7), if the capacitor C_dum was programmable, the influence of the capacitor C_p1 on the linearity could have adjusted the capacitor C_dum.

$${\mathrm{V}}_{\mathrm{X}}=\mathrm{L}\left[\frac{\mathrm{Vref}}{2^{12}}(2^5\mathrm{M}+2\mathrm{N})-{\mathrm{V}}_{\mathrm{in}}\right]+{\mathrm{V}}_{\mathrm{cm}}$$

(9)

$$=\mathrm{L}\left[\frac{\mathrm{Vref}}{2^{12}}b-{\mathrm{V}}_{\mathrm{in}}\right]+{\mathrm{V}}_{\mathrm{cm}}$$

(10)

3.2. The Proposed Differential Non-Linearity Calibration Method

In order to keep the correct scaling of the DAC capacitor array, the sum of the weighting of all capacitors in the LSB array should have been equal to the weighting of the lowest bit in the MSB array. Figure 3 shows the DAC capacitor array during calibration. When CLK was high, switches S0 and S1 were on. The bottom plates and top plates of the capacitors C4 to C11 in the MSB array were connected to the ground and Vcm, respectively. The bottom plates and top plates of capacitors C0 to C3 were connected to Vref and Vcm, respectively. When CLK was low, switches S0 and S1 were off. The bottom plates of capacitors C0 to C3 were connected to the ground in the LSB array. The bottom plates of capacitors C6 to C11 and C4 were still connected to the ground and the bottom plate of capacitor C5 was connected to Vref. The charges Q_X and Q_Y of the nodes X and Y, respectively, were unchanged during (a) and (b) in Figure 3. As a result, Equations (11) and (12) could be obtained.

$$(128{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}2}){\mathrm{V}}_{\mathrm{cm}}=(127{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{P}2}){\mathrm{V}}_{\mathrm{X}}+({\mathrm{V}}_{\mathrm{X}}-{\mathrm{V}}_{\mathrm{ref}}){\mathrm{C}}_{\mathrm{u}}+({\mathrm{V}}_{\mathrm{X}}-{\mathrm{V}}_{\mathrm{Y}}){\mathrm{C}}_{\mathrm{a}}$$

(11)

$$15{\mathrm{C}}_{\mathrm{u}}({\mathrm{V}}_{\mathrm{cm}}{-\mathrm{V}}_{\mathrm{ref}})+({\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{dum}}){\mathrm{V}}_{\mathrm{cm}}=(15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{dum}}+{\mathrm{C}}_{\mathrm{p}1}){\mathrm{V}}_{\mathrm{Y}}+({\mathrm{V}}_{\mathrm{Y}}-{\mathrm{V}}_{\mathrm{X}}){\mathrm{C}}_{\mathrm{a}}$$

(12)

Combining Equations (11) and (12), the voltage V_X at the node X is shown as:

$${\mathrm{V}}_{\mathrm{X}}=\frac{{\mathrm{V}}_{\mathrm{cm}}[(128{\mathrm{C}}_u+{\mathrm{C}}_{\mathrm{p}2})(15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{dum}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{a}})+{\mathrm{C}}_{\mathrm{a}}(15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{dum}})]+{\mathrm{V}}_{\mathrm{ref}}{\mathrm{C}}_{\mathrm{u}}[15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{dum}}+{\mathrm{C}}_{\mathrm{p}1}-14{\mathrm{C}}_{\mathrm{a}}]}{(128{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{p}2})(15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{dum}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{a}})+{\mathrm{C}}_{\mathrm{a}}(15{\mathrm{C}}_{\mathrm{u}}+{\mathrm{C}}_{\mathrm{dum}}+{\mathrm{C}}_{\mathrm{p}1}+{\mathrm{C}}_{\mathrm{a}})}$$

(13)

When the sum of all the weighting of the capacitors in the LSB array was equal to the weighting of the capacitor C5 in the MSB array, the voltage V_X at the node X was equal to Vcm in Figure 3b. In Equation (13), Vx = Vcm and Vref = 2V cm, the programmable capacitor C_dum is shown as:

$${\mathrm{C}}_{\mathrm{dum}}=14{\mathrm{C}}_{\mathrm{a}}-15{\mathrm{C}}_{\mathrm{u}}-{\mathrm{C}}_{\mathrm{p}1}$$

(14)

The voltage V_X at the node X varied with the capacitor C_dum. When the value of the capacitor C_dum was appropriate, the voltage V_X = V_cm at the node X. Therefore, the capacitor C_dum could have been adjusted according to whether the voltage V_X at the node X was equal to Vcm.

The proposed differential non-linearity calibration method is shown in Figure 4. The initial value of the capacitor C_dum was smaller than that in Equation (14) in Figure 4. The first step of the proposed differential non-linearity calibration method was to set the initial voltage value of the MSB array and the LSB array. In Figure 4a, CLK = 1 and switches S0 to S3 were on. In the upper capacitor array, the bottom plates of capacitors C6 to C11 and C0 to C4 were connected to the ground, and the bottom plate of capacitor C5 was connected to Vref. In the lower capacitor array, the bottom plates of capacitors C4 to C11 were connected to the ground, and the bottom plates of capacitors C0 to C3 were connected to Vref. The second step of the calibration was the charge redistribution. In Figure 4b, CLK = 0 and switches S0 to S3 were off. In the upper capacitor array, the bottom plates of capacitors C4 to C11 were connected to the ground, and the bottom plates of capacitors C0 to C3 were connected to Vref. In the lower capacitor array, the bottom plates of capacitors C6 to C11 and C0 to C4 were connected to the ground, and the bottom plates of capacitor C5 was connected to Vref. The value of the capacitor C_dum was smaller than the ideal value. Therefore, the voltage V_X at the node X was smaller than Vcm and the voltage V_M at the node M was larger than V_cm in Figure 4b according to Equation (13). The voltage V_X increased and voltage V_M decreased as the capacitance value of the capacitor C_dum increased.

The programmable capacitor C_dum is shown in Figure 5 and was composed of the fixed capacitor C_fixed and the adjustable capacitor C_adjust. In Figure 5, the capacitance value of the capacitor C_fixed= 26 Cu. The capacitor C_adjust was composed of eight cells. Each cell consisted of two unit capacitors Cu and two switches. When S0 was on and S1 was off, two unit capacitors Cu were connected in series and the capacitance value of the cell was 0.5 Cu. When S0 and S1 were on, the capacitance value of the cell was Cu. As a result, the capacitance value of capacitors C_adjust and C_dum ranged from 0.5 Cu to 8 Cu and from 26.5 Cu to 34 Cu, respectively.

The capacitance value of C_adjust needed to change continuously in steps of 0.5 Cu. As a result, the switches S0 to S14 could be controlled by the 15-bit thermometer code. The calibration circuit of the non-linearity is shown in Figure 6. CLKcali is the calibration clock for the comparator. The binary-to-thermometer converter converts 4-bit binary codes b<0:3> to 15-bit thermometer codes thc<0:14>, which were used to control switches S0 to S14 of capacitor C_dum in the LSB array. The comparator compared voltages V_M and V_X at nodes M and X, respectively. When the voltage V_X >V_M, the cali_control_cell block generated cal_finish to stop the 4-bit counter counting and stored thc<0:14> into the D-type flip flops. At this point, the calibration was complete.

3.3. The Proposed Hybrid Redundancy Method

Figure 7a shows the concept of the conventional binary search algorithm. There was a 4-bit case. V_ref is the reference voltage. V_in is the input signal. Firstly, V_in was sampled on the top plates of the capacitor arrays. After that, the comparator started the first comparison. According to the first comparison, the voltage difference of the two DACs added or subtracted 1/2 V_ref. The conversion repeated until the last bit was decided. In order to obtain correct digital output codes, the DAC settling error had to be less than 1/2 LSB. If a wrong decision was produced before the last comparison, even if the remaining decisions were correct, the voltage difference between the input signal and reference voltage in the last cycle was larger than LSB, which degraded the performance of the SAR ADC.

Figure 7b shows the example of the binary-scaled error compensation algorithm [30], there was also a 4-bit case. A compensative capacitor was inserted in the DAC capacitor array. Therefore, it needed 5-bit cycles to finish the conversion in this 4-bit example. After the first comparison, the number of possible quantization levels was reduced from 16 to 8. Hence, the effective input range of the binary-scaled error compensation method was reduced by a factor of 2. In Figure 7b, a wrong decision was made in the second cycle. After the fourth cycle, the input range did not reduce but shifted to compensate for the error. If the decisions were correct from the third cycle to the fifth cycle, it was possible to obtain a correct digital output code. There were multiple digital codes representing the same input voltage because of extra compensative cycles; therefore, a certain range error could be tolerated. However, extra compensative capacitors increased the sampling capacitance and resulted in a smaller input range. Moreover, it was not suitable for the bridge capacitor array.

The methods in [30,31] were not suitable for the bridge structure. In order to adapt to the bridge structure, hybrid redundancy based on the bridge capacitor array was proposed. Figure 8 is the conventional bridge capacitor array of the 12-bit SAR ADC. There was no any redundancy in the bridge capacitor array. Therefore, it did not tolerate the DAC settling error.

In [31], the binary-scaled recombination method was used in the higher DAC and the lower DAC to tolerate the DAC settling error in Figure 9. The weighting of C6 was 32 LSBs, the sum of all weightings of capacitors in the lower DAC was 31 LSBs. The weighting of C6 was larger than the sum of the weightings of capacitors in the lower DAC. Therefore, there was no redundancy. If a wrong decision was made in the last comparison cycle inthe higher DAC, it would produce a wrong digital output code.

Figure 10 shows the proposed hybrid redundancy based on the bridge capacitor array. In the higher DAC, the binary-scaled recombination method was used. The MSB capacitor was split into two groups: 56 Cu and 8(2³)Cu. Next, 8(2³)Cu was split into 2(2¹)Cu, 2(2¹)Cu, 2(2¹)Cu, 1(2⁰)Cu and 1(2⁰)Cu, respectively. Those groups were added to other groups or inserted into the higher DAC. In the lower DAC, binary-scaled compensation was used. Capacitors C5 and C2 were inserted into the lower DAC to compensate for error. In order to keep the linearity of the DAC, capacitor C5 and C2 were split from capacitor C_dum; hence, the capacitance of capacitor C_dum was reduced from 30 Cu to 20 Cu. In Figure 10, the weighting of capacitor C7 was 32 LSBs, the sum of all weightings of the capacitors in the lower DAC was 51 LSBs. The weighting of C7 was smaller than the sum of all weightings of capacitors in the lower DAC. Therefore, there was redundancy. If a wrong decision was made in the last cycle in the higher DAC, it was possible to produce a correct digital output code. Moreover, the inserted capacitors were from capacitor C_dum, which neither increased the sampling capacitance nor reduced the input range.

Table 1. Comparison of redundant ranges with different redundant methods.

	Recombination [6]		Proposed Hybrid Method
	14 bit Cycles to Convert 13 bit		16 bit Cycles to Convert 13 bit
Number of bit Cycling	bit Weighting	Redundancy Range (LSB)	bit Weighting	Redundancy Range (LSB)
1	1792	512	1792	532
2	1024	256	1024	276
3	512	256	512	276
4	320	128	320	148
5	192	64	192	84
6	128	0	96	84
7	64	0	64	52
8	32	0	32	52
9	14	4	32	20
10	8	2	16	20
11	4	2	16	4
12	2	2	8	4
13	2	0	4	4
14	1	0	4	0
15			2	0
16			1	0

shows the comparison of redundant ranges with different redundant methods. In the 8th cycle (the last cycle of the higher DAC), the redundant range was 0 LSB in [32]. In the 10th cycle (the last cycle of the higher DAC), the redundant range was 20 LSBs. The weighting of the last cycle of the higher DAC was relatively large. If a wrong decision was made in this cycle, the performance of the ADC would degrade. The proposed hybrid redundancy could provide a certain range of redundancy to tolerate the DAC settling error in this cycle. There was no redundancy in the 6th to 8th cycles in the higher DAC in [32]. There was a certain range of redundancy for each cycle in the higher DAC in the proposed hybrid redundancy method. Moreover, the redundant range of each cycle in the proposed hybrid was lager than the redundant range in [32]. Therefore, the proposed hybrid redundancy was suitable for the bridge structure and the high-resolution ADC.

The digital output could be expressed as:

$$\begin{array}{cc}\hfill {\mathrm{D}}_{\mathrm{out}}=& 2^5(2^6-2^3){\mathrm{B}}_{15}+2^5\times 2^5{\mathrm{B}}_{14}+2^5\times 2^4{\mathrm{B}}_{13}+2^5(2^3+2){\mathrm{B}}_{12}+2^5(2^2+2){\mathrm{B}}_{11}+2^5(2+2^0){\mathrm{B}}_{10}\hfill \\ & +(2^5\times 2){\mathrm{B}}_9+(2^5\times 2^0){\mathrm{B}}_8+(2^5+2^0){\mathrm{B}}_7+2\times 2^3{\mathrm{B}}_6+({\mathrm{B}}_5-0.5)2\times 2^3+2\times 2^2{\mathrm{B}}_4+2\times 2{\mathrm{B}}_3\hfill \\ & +2\times 2({\mathrm{B}}_2-0.5)+2{\mathrm{B}}_1+{\mathrm{B}}_0\hfill \end{array}$$

(15)

$$\begin{array}{cc}\hfill {\mathrm{D}}_{\mathrm{out}}=& 2^{10}({\mathrm{B}}_{15}+{\mathrm{B}}_{14})+2^9({\mathrm{B}}_{15}+{\mathrm{B}}_{13})+2^8({\mathrm{B}}_{15}+{\mathrm{B}}_{12})+2^7{\mathrm{B}}_{11}+2^6({\mathrm{B}}_{12}+{\mathrm{B}}_{11}+{\mathrm{B}}_{10}+{\mathrm{B}}_9)\hfill \\ & +2^5({\mathrm{B}}_{10}+{\mathrm{B}}_8+{\mathrm{B}}_7)+2^4({\mathrm{B}}_6+{\mathrm{B}}_5)+2^3{\mathrm{B}}_4+2^2({\mathrm{B}}_3+{\mathrm{B}}_2)+2{\mathrm{B}}_1+{\mathrm{B}}_0-10\hfill \end{array}$$

(16)

Figure 11 illustrates the digital error correction logic, which converted the 16-bit redundant codes to 12-bit binary codes. The digital codes has an offset of 10, and the offset was moved by logic operations.

4. The Implementation of Key Building Blocks

4.1. Bootstrapped Switch

Bootstrapped switch [34] is shown in Figure 12. CLKs was the sampling clock. When CLKs = 0, transistors M7 and M8 discharged node A to the ground. Transistor M4 charged capacitor Cs to VDD. Transistors M9 and M10 were off. At this time, the bootstrapped switches were in the hold state. When CLKs = 1, transistors M1 and M8 were off and transistor M6 was on. The gate and source of transistor M10 were connected to the top plate and the bottom plate of capacitor Cs. Therefore, the gate-to-source voltage of transistor M10 was VDD. At this time, the bootstrapped switches were in the tracking state. When CLKs = 0, transistor M10 was off. However, the input signal Vin was fed through the output Vout by the parasitic capacitance Cds of transistor M10, which affected the spurious-free dynamic range (SFDR). Transistor M10-dum was the dummy transistor of M10, and the gate of transistor M10-dum was connected to the ground. The input signal Vip was the differential signal of the input signal Vin, which could cancel the feedthrough of Vin by the parasitic capacitance Cds of transistor M10-dum.

4.2. Dynamic Comparator

Figure 13 shows a dynamic three-stage comparator [35]. When CLks = 1 and CLKsn = 0, transistors M3 and M4 charged nodes A and B to VDD, transistors M5 and M6 discharge the nodes C and D to the ground and transistors M15 and M16 charged nodes E and D to VDD. Outputs OUTn and OUTp were VDD. Transistors M0, M9 and M10 were off. At this time, the comparator was in the reset state. When CLKs = 0 and CLKsn = 1, the dynamic comparator started comparing the differential input signals Vin and Vip. A three stage dynamic comparator had lower input noise, offset voltage and faster speed.

4.3. Asynchronous Dynamic Control Logic

Figure 14 shows asynchronous control logic, which was composed of 19 D-type flip flops (DFFs). For the DFFs, when Set = 0, output Q of the DFFs was VDD. When Reset = 0, output Q of the DFFs was ground. Valid represents the state of the comparator. When valid was high, the comparator was in the reset state. When valid was low, the comparator was comparing the input signals. Figure 15 shows the timing of the asynchronous control logic. The extra cycle A was used for charge redistribution because bottom-plate sampling was adopted.

Figure 16 shows the DAC control logic. OUTp and OUTn were outputs of the comparator. CLK<i> stands for one of CLK0 to CLK15 in Figure 15. When the ADC was sampling, the CLKs = 1 and CLK<i> = 0. At this time, transistor M1 was off and transistor M2 charged node A to VDD. Transistor M3 was off and transistor M4 discharged node B to the ground; therefore, Out<i> was ground and Out<i> was connected to the bottom plate of each capacitor in the differential DAC capacitor arrays. When CLKs = 1 and CLK<i> = 1, transistor M1 was on and transistor M2 was off. Transistors M5 and M6 were off. At this time, Out<i> changed with Outp or Outn. When Outp or Outn was VDD, Out<i> was still ground. When Outp or Outn was ground, transistor M3 charged node B to VDD and Out<i> was VDD.

4.4. Capacitor Array

The DAC capacitor array had a great impact on the performance of the SAR ADC. The mismatch of the unit capacitor could affect the SFDR and SNDR. Figure 17a shows the structure of the unit capacitor. The top plate was the middle and the bottom plates were on both sides. The unit capacitor was composed of metal3, metal4 and metal5: three layers of metal. Each metal capacitor was the interdigital capacitor. Figure 17b shows the floorplan the DAC capacitor array. The top plates of capacitors C_{i + 1},C_i and C_{i − 1} were connected together. Bottom plates S_{j + 1}, S_j and S_{j − 1} were connected to different control signals. In Figure 17b, only two unit capacitors were placed in each column. In the actual layout, four or eight unit capacitors could be placed in each column according to requirements. The active area of the unit capacitor was 2.045 um × 1.85 um. The value of the unit capacitor was 6fF.

4.5. Clock Driver

The clock driver could convert the differential sinusoidal signals into square waves, which could be used as the sampling clock. Figure 18 shows the clock driver. The capacitor C1 and resistor R1 and capacitor C2 and resistor R2 constituted high pass filters, respectively. Resistors R3 and R4 provided suitable static operating points for the differential input transistors M1 and M2. The resistors M5 and M6 formed the common mode feedback circuit, which could stabilize the output voltage of the first stage. Moreover, resistors M3 and M4 could provide appropriate bias voltage for transistors M3 and M4. The first stage was the differential amplifier, and the second stage converted differential signals to a single ended signal. The inverter converted the single ended signal into a square wave.

4.6. Post Simulation

Figure 19 shows the post simulation results of SNDR with temperature and corner when the input frequency was 49.96 MHz. As can be seen from Figure 19, SNDR also increased with the increase in temperature. When the temperature was 120 °C and corner was ff, SNDR reached a maximum of 65.03 dB. When the temperature was −40 °C and corner was ss, SNDR reached a minimum of 57.75 dB.

5. Measurement Results

The prototype was fabricated using 1P8M 28 nm CMOS technology. The chip photograph and proposed SAR ADC are as shown in Figure 20. The active area of the proposed SAR ADC was 303 um × 75 um.

Figure 21a shows the measured spectrum with inputs at 4.89 MHz when the proposed calibration method was off. The measured SFDR and SNDR were 79.5 dB and 58.16 dB, respectively. Figure 21b shows the measured spectrum when the proposed calibration method was on. The measured SFDR and SNDR were 82.7 dB and 61.46 dB, respectively. When proposed, the calibration method was on and the SFDR and SNDR were increased by 3.2 dB and 3.3 dB, respectively. Figure 22a shows the measured spectrum with inputs at 49.96 MHz when the proposed calibration method was off. The measured SFDR and SNDR were 77.5 dB and 56.3 dB, respectively. Figure 22b shows the measured spectrum when the proposed method was on. The measured SFDR and SNDR were 79.1 dB and 58.82 dB. respectively. When the proposed calibration method was on, the SFDR and SNDR were increased by 1.6 dB and 2.52 dB, respectively. Figure 23 shows the measured DNL and INL when the proposed calibration method was off. The peak DNL and INL were 1.40/−1.23 LSB and 1.43/−1.35 LSB, respectively. Figure 24 shows the measured DNL and INL when the proposed calibration method was on. The peak DNL and INL were 0.754/−0.56 LSB and 0.83/−0.85 LSB, respectively.

The proposed calibration method was helpful for improving static and dynamic performance.

The power consumption of the proposed SAR ADC was 0.86 mW. The proposed SAR ADC achieved a figure of merit (FOM) of 8.69 and 11.8 fJ/conversion step at low-frequency input and Nyquist input frequency, respectively.

Table 2. Performance summary and comparisions.

		This Work	[34]	[36]	[37]	[38]	[39]
Architecture		SAR	SAR	SAR	SAR	SAR	SAR
CMOS technology		28 nm	20 nm	65 nm	40 nm	40 nm	14
Resolution (bits)		12	10	11	12	12	12
Supply Voltage (V)		0.9	1	1.2	1	0.9	0.8
Sampling Rates (MS/s)		100	320	100	120	150	100
SNDR (dB)	@LF	61.46	57.1	60	60.33	61.7	61.29
	@Nyquist	58.82	50.9	58.8	58.1	56.2	58.34
SFDR (dB)	@LF	82.7	78.1	74	72.9	74.4	82.08
	@Nyquist	79.1	58.6	74.61	72	63.5	78.02
ENOB (bit)	@LF	9.95	9.2	9.67	9.72	9.95	9.89
	@Nyquist	9.51	8.16	9.51	9.35	9.0	9.40
Power (mW)		0.86	1.52	1.6	1.9	1.5	0.78
FOM (fJ/conv-step)	@LF	8.69	8.1	19.2	18.7	10.3	8.2
	@Nyquist	11.8	16.5	21.9	24.26	18.5	11.15
Area (mm2)		0.00227	0.0012	0.011	0.0128	0.04	0.112
DNL (LSB)		0.754/−0.56	0.41/−0.34	1.05/−0.842	0.96/−0.93	1.77/−0.91	—
INL (LSB)		0.83/−0.85	0.28/−0.43	1.28/−0.972	1.6/−1.08	2.95/−2.63	—

compares the proposed SAR ADC with other high-performance SAR ADCs [34,35,36,37,38,39]. The proposed SAR ADC reached the level of the research front. The FoM of the proposed SAR ADC at Nyquist was low among ADCs [34,35,36,37,38,39].

6. Conclusions

In this paper, a 12-bit, 100 MS/s SAR ADC with calibration is proposed. The differential non-linearity calibration method was proposed to compensate for the linearity, which was degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. The proposed SAR ADC consumed 0.86 mW. The ADC achieved an SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in FoMs of 8.69 and 11.8 fJ/conversion step, respectively. The FOM [40] is shown as Equation (17):

$$\mathrm{FOM}=\frac{\mathrm{Power}}{2^{\mathrm{ENOB}}\cdot \min \left\{{\mathrm{f}}_{\mathrm{s}},2\mathrm{ERBW}\right\}}$$

(17)

In Equation (17), sampling frequency was represented by fs, power consumption of the SAR ADC was presented by Power, effective resolution bandwidth was represented by ERBW and the effective number of bits of the ADC was represented by ENOB.