A Novel Buck Converter with Dual Loops Control Mechanism

Abstract

This paper presents a novel buck converter with dual-loop control technology, which does not need to detect the inductor current directly. The structure of the control loops is easy to implement, one loop controls the output voltage, and the other controls the switching frequency. With the dual loops control mechanism, the output voltage and switching frequency can be accurately controlled only by measuring the output and input voltage, without sensing the inductor current. The buck converter can generate an output voltage of 1.0–2.5 V when the input voltage and load current are 3.0–3.6 V and 100–500 mA, respectively. The design was verified by SIMPLIS. The simulation results show that the switching frequency variation is less than 1% at the output voltage of 1.0–2.5 V. The recovery time is less than 1.5 μs during the load change. The circuit can be fabricated by using the TSMC 0.35μm 2P4M CMOS processes. The control scheme, theoretical analysis and circuit implementation are presented in this paper.

1. Introduction

Nowadays, power converters are widely used in many applications, such as portable devices, consumer electronics, industrial electronics, and energy storage systems, to produce stable DC or AC power. Even the current hot topics, such as artificial intelligence (AI), wireless sensor networks (WSN), and the Internet of things (IoT), also need to use power converters [1,2,3]. In ultra-low power applications, power management is crucial. A review of charge pump topologies for the power management of IoT nodes is presented in [4]. The literature [4] surveys several solutions of linear charge pump topologies and presents the analysis and implementation of the power management circuit of IoT nodes. A. Ballo et al. [5] introduces the charge pump topology used for IoT power management in ultra-low power applications and provides design guidelines on how to obtain the most appropriate solution under the design specifications. Generally, the standby time of portable products is a critical user experience. Therefore, how to make efficient power conversion is very important.

The DC-DC power converters can be divided into switched inductor converters and switched capacitor (SC) converters [6]. The components of a switched inductor converter are mainly the inductor, switches and control circuits. On the contrary, the SC converter is composed of the capacitors, switches and control circuits. From the perspective of the application, the SC converter is mainly used in low-power applications, due to the capacity of capacitor, while the switched inductor converter has no such limitation, ranging from a fraction of a watt to a few hundred watts. The SC converter has its advantages in power density and power efficiency under specific conversion ratios. However, there will be voltage regulation problems under some voltage conversion ratios [7].

In contrast, the switched inductor converter is popular in power electronics because of its wide range of applications, high design flexibility, high reliability and low cost. This type of DC-DC converter includes Buck, Boost, Buck-Boost, Cuk and SEPIC converters, which are often used in various electronic products [8,9,10]. This paper focuses on the switched inductor DC-DC buck converter, analyzes the advantages/disadvantages of the existing control schemes and proposes the suggestion scheme finally.

In the existing control schemes of the buck converter, it can be roughly divided into two control modes: voltage mode control (VMC) [11] and current mode control (CMC) [12,13,14,15]. Figure 1 shows the structures of these control modes. From Figure 1, we can find that the difference between the two modes lies in the feedback path. Since the CMC has more of a feedback path than the VMC, the CMC should give a good performance in regard to the transient response and the voltage regulation. Therefore, the CMC technology is widely used in power conversion technology.

Similar to the VMC buck converter, the converter structure based on the charge pumps has been proposed in [16]. The charge-pump-based converter [16] is very suitable in a boost topology. The main advantage of the [16] is that the converter can be fully integrated into silicon. Therefore, the literature [16] provides a good solution for ultra-low power applications. On the other side, similar to the CMC buck converter, Ballo et al. [17] proposed a novel scheme to improve charge transfer switches in linear charge pumps. The proposed converter in [17] belongs to the SC type.

In the switched inductor-based converters, there are many types of the CMC, including peak current mode (PCM), average current mode (ACM), constant on/off time, and adaptive on time (AOT) [18,19,20,21,22,23,24,25,26,27,28,29]. The feature of the CMC is that it needs to directly or indirectly sense the information of inductor current. Therefore, many works of the literature discuss how to sense the inductor current. These works in the literature are summarized and analyzed in [30].

This paper presents a no-inductor-current-sensor buck converter, which adopts dual loops control mechanism. At the same time, the proposed converter has the feature of a constant switching frequency.

The organizational structure of the paper is as follows: Section 2 presents proposed control topology and circuit realization. Section 3 introduces the theoretical analysis. Section 4 shows the SIMPLIS simulation results. Finally, conclusions are given in Section 5.

2. Proposed Control Topology and Circuit Realization

2.1. Proposed Control Topology

Figure 2 shows the proposed control topology. It uses the dual controllers to regulate the output voltage and the switching frequency. The “proposed adaptive T_OFF controller” keeps the switching frequency constant, and the “proposed adaptive T_ON controller” regulates the output voltage. This topology does not require a current sensor to detect the inductor current actually. The states of switches S₁ and S₂ are non-overlapping and complementary.

The subfunction blocks in Figure 2 are described as follows:

(A)

Constant Frequency Mechanism:

The work of this module is mainly used to detect the switching frequency of the system and generate a control voltage to send to the “proposed adaptive T_OFF controller” module. The control signal can adjust T_OFF to make the switching frequency constant.

(B)

Proposed adaptive T_OFF controller:

The work of this module is mainly to regulate T_OFF. This module controls the T_OFF by the signal of the “constant frequency mechanism”.

(C)

Proposed adaptive T_ON controller:

The work of this module is mainly to regulate T_ON. This module function is similar to the “proposed adaptive T_OFF controller”. This module controls the T_ON by the output signal of the EA.

(D)

EA (Error Amplifier)

The work of the EA is mainly to regulate V_FB to V_REF, that is, the V_FB is equal to the V_REF. Because the relationship between V_o and V_FB is a resistor division in Figure 3, the V_o value can be decided by setting V_REF.

(E)

DRIVER:

The work of the DRIVER is mainly to generate sufficient driving capability to drive the switches S₁ and S₂.

The advantages and disadvantages, as compared with the conventional schemes are listed below:

• Advantages

  (A)

  The scheme does not need to design a complex sensing circuit to sense the inductor current at any time. Compared with the scheme of using the current sensor [2], the proposed scheme is easy to implement and suitable for mass production.

  (B)

  The whole control circuit does not require special semiconductor devices, and there is no special matching issue in layout.

  (C)

  By the “constant frequency mechanism” module, the proposed scheme can make the switching frequency constant, which greatly reduces the difficulty in solving EMI issue. Moreover, the “constant frequency mechanism” is easy to implement, instead of PLL [31].

• Disadvantages

  (A)

  In contrast to SC converter, the scheme cannot be fully integrated into silicon.

2.2. Circuit Realization and Operating Principle

The implementation of the proposed converter is shown in Figure 3. From Figure 3, the realization of the controllers is effortless and suitable for PMIC. In addition, the “constant frequency mechanism” module is realized by referring [31]. For different applications, V_O can be designed to the required value by adjusting the V_REF in Figure 3. Furthermore, the switching frequency of the converter can also be adjusted by V_REF2. Therefore, such a scheme is very flexible in the design. The operation of the converter in Figure 3 can be listed as follows:

• The switch S₁ turns ON, and the switch S₂ turns OFF. In this state, the inductor is in the charging phase. The ON time of S₁ is labeled as T_ON. The T_ON is determined by the “proposed adaptive T_ON controller” module. When S₁ is ON, the V_ramp begins to rise toward the V_CMP. Once the V_ramp reaches the V_CMP, the S₁ is turned OFF, and the S₂ is turned ON.
• The switch S₁ turns OFF, and the switch S₂ turns ON. In this state, the inductor is in the discharging phase. The OFF time of S₁ is labeled as T_OFF. The T_OFF is determined by the “proposed adaptive T_OFF controller” module.
• The “constant frequency mechanism” works to detect the switching frequency. The V_EA1 controls the “proposed adaptive T_OFF controller” to decide T_OFF [31].
• In the steady state, the V_FB and the V_freq are almost equal to the V_REF and the V_REF2, respectively. In other words, the V_CMP and the V_EA1 will eventually converge to their stable voltages. The key waveforms of the converter are drawn in Figure 4.

3. Theoretical Analysis

3.1. Mathematical Model

As in [30,31], to verify the system’s stability, a mathematical model must be built. Since the converter can be regarded as an analog/digital hybrid system, it is not easy to establish a mathematical model accurately. Much relevant research about modeling is discussed in [32,33,34,35]. Ridley et al. [35] is the most popular reference in the literature. The purpose of mathematical modeling is to help obtain design parameters and increase the reliability of the designed circuit.

By referring to [35], the open-loop transfer function of the converter can be expressed as Equation (1). In Equation (2), the G_P(s) is the transfer function of the buck converter. The transfer function of the “EA” module is represented as A(s), composed of the transconductance, gm, and the compensation network. Figure 5 illustrates these relationships.

Figure 5 is derived from Figure 3. In order to measure the open-loop response, the line labeled V_CMP in Figure 3 must be broken. In Figure 5, the “constant frequency mechanism” and the “proposed adaptive T_OFF controller” modules can be mapped to Figure 3. The “proposed adaptive T_ON controller” of Figure 5 is divided into three parts: (a) comparator, (b) digital logic, and (c) T_ON ramp generator, which can also be mapped to Figure 3.

$$T\left(s\right)=\frac{V_o\left(s\right)}{V_i\left(s\right)}=G_P\left(s\right)·A\left(s\right)$$

(1)

$$G_P\left(s\right)=\frac{V_{FB}\left(s\right)}{V_i\left(s\right)}=\frac{1}{K_i}·\frac{1}{1+\frac{s}{Q·\omega }+\frac{s^2}{{\omega }^2}}·\frac{R_{LOAD}\left(R_{ESR}{C}_{o}s+1\right)}{\left(R_{LOAD}+R_{ESR}\right)C_{o}s+1}$$

(2)

$$A\left(s\right)=\frac{V_o\left(s\right)}{V_{FB}\left(s\right)}=g_m·R_o·\frac{\left(1+\frac{s}{w_z}\right)}{\left(1+\frac{s}{w_p}\right)}$$

(3)

where $K_i$ is the gain of the T_ON ramp generator, $\mathsf{\omega }=\raisebox{1ex}{$\pi $}\!\left/ \!\raisebox{-1ex}{$T_{on}$}\right., Q=\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$\pi $}\right.$, $w_z=\frac{1}{R_3·C_1}$ and $w_p=\frac{1}{R_o·C_1}$

From Equations (1)–(3), it can be seen that the values of the K_i, R_O, R₃ and C₁ will affect the performance of the converter. Generally, the zero w_z of the A(s) is designed to be equal to the output pole of the buck converter, as shown in Equation (4). Considering the stability, the pole w_p location of the A(s) is designed to be let the system stable. Chou et al. [30,31] introduced the detailed design procedure for this type of the converter and verified it by using MathCAD and SIMPLIS.

$$w_z=\frac{1}{\left(R_{LOAD}+R_{ESR}\right)C_o}\approx \frac{1}{R_{LOAD}·C_o},f_z=\frac{w_z}{2\pi }$$

(4)

Briefly, the C₁, R_O and R₃ are the key design parameters which mainly affect the frequency compensation. In Figure 3, if the external components are confirmed, the C_o, R_ESR, R_LOAD and L can be the fixed values. The designer must carefully select the remaining components, especially C₁, R_O and R₃.

3.2. Component Selection

Based on the design process in [30,31], we determined the design parameters in the converter (listed in

Table 1. Design parameters.

Component	Value	Unit
RLOAD	3.6	Ω
Co	10	μF
L	4.7	μH
RESR	5	mΩ
Ro	1	MΩ
R3	180	kΩ
C1	200	pF

).

4. Simulation Results

4.1. SIMPLIS Schematic

The SIMPLIS schematic of the proposed converter was built and is shown in Figure 6. For well mapping to Figure 3, the SIMPLIS schematic is grouped by the function module, and annotated on it. For example, the “Constant Frequency Mechanism”, “Proposed Adaptive T_ON Controller”, “Proposed Adaptive T_OFF Controller,” and “DRIVER” modules are all clearly illustrated and annotated in Figure 6.

4.2. Transient Performance

Figure 7 shows the load transient response of the proposed converter. Similar to [30,31], the load current is changed between 0.1 and 0.5 A. The input/output voltages are set to 3.3 V/1.8 V. The recovery time is defined as when the load changes, and the output voltage recovers to within 1% of 1.8 V.

In Figure 7, the step-up and step-down recovery times of the load current transition are 1.5 μs and 0.9 μs, respectively. Therefore, the recovery time of the proposed converter is less than 1.5 μs. In addition, the specifications of the overshoot and undershoot voltage are measured as 16 mV and 12 mV, respectively, both within the range of 16 mV.

The converter can work under the V_in of 3.6 V–3.0 V, and the output voltage is 1.0 V–2.5 V. Figure 8 shows that the maximum ripple voltage is 2.7 mV when the V_in is 3.6 V, the V_o is 2.5 V and load current is 500 mA.

4.3. Load Regulation

The load regulation follows Equation (5). This specification indicates the output regulation capability when the load changes. In application, the load regulation should be as small as possible. Similar to [30,31], the simulation conditions are set as follows: The input/output voltages are 3.3 V/1.8 V. The load current varies from 0.5 A to 0.1 A. As shown in Figure 9, the load regulation is 0.04% through Equation (5).

$$\mathrm{Load} \mathrm{Regulation} =\frac{V_{o@0.1A load current}-V_{o@0.5A load current}}{V_{o@0.5A load current}}·100\%$$

(5)

where $V_{o@0.5A load current}$ is the voltage at the 0.5 A load current, and $V_{o@0.1A load current}$ is the 0.1 A load current.

4.4. Line Regulation

The line regulation follows Equation (6). This specification indicates the output regulation capability when the supply voltage changes. In application, the line regulation should be as small as possible. In the simulation, the supply voltage ranges from 3.0 V to 3.6 V. However, through Equation (6), we can see that the value of this specification is close to 0. Obviously, this specification cannot be presented in the system-level simulation. In general, the real situation may be worse than the simulation.

$$\mathrm{Line} \mathrm{Regulation}=\frac{\mathsf{\Delta }{V}_o}{\mathsf{\Delta }{V}_{in}}·100\%$$

(6)

where ΔV_in is the variation of the input voltage, and ΔV_o is the variation of the output voltage.

4.5. Switching Frequency Regulation

By the constant frequency mechanism, the adaptive T_OFF controller makes the switching frequency constant. The work of the constant switching frequency is summarized as follows: (Figure 3)

(A)

Conversion step:

It converts the information of switching frequency into an analog voltage, V_freq, as shown in Figure 3.

(B)

Regulation step:

It uses the error amplifier (EA) to regulate the V_freq to the designed value, V_REF2. The output voltage of the error amplifier will decide the T_OFF, that is, the switching frequency.

The Figure 10 shows the switching frequency of the different output voltages. From the simulation results in Figure 10, the switching frequency can maintain about the frequency of 1 MHz under different output voltages.

4.6. Performance List

The performance of the novel buck converter is summarized in

Table 2. Performance summary.

Parameter	Conditions	Min.	Typ.	Max.	Unit
Input voltage		3.0		3.6	V
Output voltage		1.0		2.5	V
Output ripple	Vin = 3.6 V, Vo = 2.5 V			2.7	mV
Load current		100		500	mA
Inductor	DCR *: 30 mΩ		4.7		μH
Output capacitor	ESR: 5 mΩ		10		μF
Switching frequency	Vin = 3.0~3.6 V, Vo = 1.0~2.5 V		1		MHz
Recovery time (step-up)	Vo = 1.8 V Load current: 100 mA to 500 mA		1.5		μs
Recovery time (step-down)	Vo = 1.8 V Load current: 500 mA to 100 mA		0.9		μs
Overshoot voltage	Vin = 3.3 V, Vo = 1.8 V		16		mV
Undershoot voltage	Vin = 3.3 V, Vo = 1.8 V		12		mV

* DCR: the DC resistance of inductor.

. From the 100 mA load current to the 500 mA load current, the recovery time is less than 1.5 μs. Furthermore, the converter gives a good performance under a supply voltage of 3.0 V–3.6 V and an output voltage of 1.8 V. Finally, the performance comparisons with reported converters are listed in

Table 3. Performance comparisons with reported converters.

References	2018 [36]	2020 [37]	2021 [30]	2021 [31]	This Work
Results	simulation	simulation	simulation	simulation	simulation
Control scheme	AOT	AOT	AOT	AOT	dual loops
Process (μm)	0.35	0.18	0.35 **	0.18 **	0.35 **
Input voltage (V)	12	3.3–5.0	3.0–3.6	3.0–3.6	3.0–3.6
Output voltage (V)	1.2	1.8	1.0–2.5	1.0–2.5	1.0–2.5
Inductor (μH)	1	1.5	4.7	4.7	4.7
Output Capacitor (μF)	47	20	10	10	10
Switching Frequency (MHz)	1	1	1	1	1
Switching frequency variation (%)	N/A	N/A	N/A	<1%	<1%
Max. Load current (mA)	5000	2000	500	500	500
Load current step (mA)	4000	800	400	400	400
Undershoot/Overshoot (mV)	20/26	13/14	23/26	20/24	16/12
Recovery time (μs) (rise/fall)	<3	6/2	1.98/1.6	1.69/1.62	1.5/0.9

** This work is system level simulation with SIMPLIS.

.

5. Conclusions

In this paper, a novel buck converter with a dual-loop control mechanism is proposed. The converter adopts a novel method to generate the T_ON and T_OFF. The converter has three advantages. First, the control scheme does not need a current sensor, thus greatly reducing the circuit complexity, and it is suitable for mass production. Second, the proposed scheme can make the switching frequency constant, which greatly reduces the difficulty in solving EMI issue. Third, the whole circuit does not require special semiconductor devices to implement, and there is no special matching issue in layout. The scheme was verified by using SIMPLIS. The simulation results show that this control topology can still obtain a good performance, without realizing the inductor current sensor. Furthermore, the proposed buck converter can be implemented with TSMC 0.35 μm 2P4M CMOS processes.