Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

Abstract

In the automotive industry, system-on-chips are crucial for managing weak radio waves from space, known as satellite signals. Integer-N phase-locked loops have played a vital role in the operation of system-on-chips in recent history. Their clock frequencies are carefully designed to prevent electromagnetic interference. However, as global navigation satellite system becomes more prevalent, integer-N phase-locked loops face new challenges in generating clocks within the shrinking frequency bands due to large frequency steps determined using a reference clock. To address it, replacing integer-N phase-locked loops with fractional-N phase-locked loops is required. This topic has not been discussed extensively, but it is a practical issue that requires consideration due to its potential impact on development costs. This is why we developed an attachable fractional divider. Our developed divider can efficiently transform integer-N phase-locked loops into fractional-N phase-locked loops, achieving low jitter degradation of 0.35 ps_rms and a low fractional spur of −69.3 dBc. Thanks to its attachable design, it expedites time-to-market. Regarding mass production, ensuring immunity to process, voltage, and temperature variations is a significant concern. We introduce the circuit techniques employed in the developed fractional divider for immunity to process, voltage, and temperature variations. Subsequently, we provide a comprehensive set of measurement results. The frequency differences over process variations in fractional-N mode is 6.14 ppm. Power supply and temperature dependances are extremely small in spread-spectrum clocking mode. This article illustrates that the developed fractional divider enhances both time-to-market and product reliance.

1. Introduction

System-on-chips (SoCs) continue to increase in complexity year by year, resulting in diverse frequency clocks used within them. Within SoCs, phase-locked loops (PLLs) play a crucial role in generating these clocks, providing various circuit blocks by using one or a few reference clocks which are commonly used from around ten to a few tens of MHz. In the automotive industry, SoCs significantly contribute to the deployment of Advanced Driver Assistance Systems (ADAS). These specialized SoCs process an array of signals critical for location identification, road condition analysis, and more. One of them is a weak radio wave from space, known as satellite signal. Therefore, the location of each output frequency of PLLs is carefully designed to avoid electromagnetic interference (EMI) problems [1]. In the past, specific frequency bands were allocated for satellite signals, requiring careful design for frequency locations, yet it was relatively manageable. However, recently, the global navigation satellite system (GNSS) is becoming more prevalent, leading to the reduction in the available frequency bands for clocks (Figure 1). In contrast, integer-N PLLs (Int-N PLLs) have played a vital role in the operation of SoCs in recent history because of the fact that the automotive industry typically operates on longer product development cycles, often spanning several years. Int-N PLLs exist in many automotive ICs. For Int-N PLLs, their frequency control step is determined using their reference clocks, which are too coarse to avoid the limited bands as shown in Figure 1. There are some choices by which to address this issue. Changing reference frequency leads to requests for IC users to switch to a different oscillator, located outside the IC, to provide a clock to PLLs. That means a significant amount of time and financial investment are required. Another choice is to replace Int-N PLLs with fractional-N PLLs (Frac-N PLLs) like in [2,3,4,5,6,7,8,9,10,11,12,13,14,15,16], multiplying reference frequency with fractional value. Within this choice, we have a few options: acquiring Frac-N PLLs from a silicon IP developer or developing the necessary PLLs from scratch. For the first option, we need to spend cost and change many wires to connect provided PLLs. If required to change routing important signals such as input and output clocks, it would take time to design and have a substantial impact on your SoCs. Generally, the more changes that are made, the higher the risk of failure. With this option, it is inevitable to take a risk; if possible, we prefer to avoid it. For the second option, developing the necessary PLLs from scratch, we can minimize the change in routing signals connected the necessary PLLs, thereby reducing the risk. However, obviously, this requires a significant amount of time to create the necessary PLLs, resulting in increasing time-to-market. While Frac-N digital PLLs appear to be designed quickly due to their digital-rich structures, most of them need time-to-digital converters (TDCs) to make phase quantization noise small [2,3,4,5]. The TDC, a critical analog block, requires a significant amount of time to develop and needs calibration, increasing complexity. Another answer can be putting an existing fractional divider and an Int-N PLL together to make a Frac-N PLL. Some fractional dividers are reported. In [6], the need for an extra-coarse frequency control requires the use of two ∆∑ modulators, leading to an increase in complexity. In [7], two-step phase interpolation has been proposed to reduce ∆∑ quantization noise. However, one of phase interpolators (PIs) is put together with the phase detector, limiting its applicability to a broad range of PLL types. As a solution for these issues, we developed an attachable fractional divider [17,18]. The developed divider can transform Int-N PLLs into Frac-N PLLs with minimum effort. You can use existing Int-N PLLs, which you already have, to acquire Frac-N PLLs, thereby saving time and cost. Furthermore, its attachable design significantly minimizes the effort required to connect to each Int-PLL, resulting in reducing the risk of both failure and performance degradations. Most wires for input and output clocks do not need changes because existing Int-PLLs are recycled. Moreover, the developed divider has spread-spectrum clocking (SSC) capability, contributing to the reduction in EMI. In our previous work [17,18], we presented the concept of the developed divider, some circuit techniques, and initial measurement results. However, we were unable to delve into specific circuit techniques ensuring immunity to process, voltage, and temperature (PVT) variations or provide a comprehensive set of measurement results validating the efficacy of this immunity. In this article, we introduce them. Regarding mass production, ensuring immunity to PVT variations is a significant concern. Analog circuits are often the issue when it comes to achieving this immunity. In our developed circuit, the PI, operating like in [19,20,21], is a key analog circuit, determining the immunity to PVT variations. We focus in detail on the circuit design and techniques of the PI, as introduced in Section 3.

The rest of this article is organized as follows. In Section 2, we explain the architecture of the developed fractional divider and its design concerns lowering immunity to PVT variations. In Section 3, we describe the circuit design of the proposed phase interpolator. Measurement results and conclusion are presented in Section 4 and Section 5, respectively.

2. Architecture of the Fractional Divider and Design Concerns

Figure 2a shows a conceptual figure of transforming Int-N PLLs into Frac-N PLLs. The SoC has some circuit blocks using clocks from PLLs. PLLs receive a reference clock (F_REF) coming from outside the SoC. Clock wires of both F_REF and PLL outputs are used before transforming. Thanks to its attachable design, the developed divider, FDIV, can enable us to aim Frac-N PLLs with minimal changes to important wires such as input and output clocks, leading to the reduction in the failure risk. Figure 2b shows the block diagram of the transformed Frac-N PLL. The Int-N PLL has a commonly used structure that can be either ring or LC type. PLLs in SoCs typically have the mode to incorporate an external delay in the feedback loop to manage and control the phase relationship in the system, often called the external feedback mode. When transforming, we use this mode. The developed fractional divider has several input signals. Only one input signal is vital because it is a clock signal coming from the Int-N PLL. The remaining input signals, such as for fractional divisor and SSC setting, are control signals that do not require attention. FDIV’s output signal is FFB_FRAC that is a phase interpolated clock fed to the Int-N PLL as its feedback clock. To transform the Int-N PLL into a Frac-N PLL, attention is required only for routing two clock wires and putting FDIV in close to the Int-N PLL.

Figure 3 shows the details of the circuit implementation for FDIV. Two power supplies, AVDD (=1.8 V) and VDD (=0.8 V), are used to match the Int-N PLLs’ power structure. PLLs in SoCs often use a few power supplies to achieve connectivity and high performance at the same time. The level for input and output clocks is VDD, provided by many circuit blocks such as CPUs, memories, control logics, and so on. AVDD is dedicated to sensitive analog circuits, such as a phase-frequency detector (PFD), charge pumps (CPs), and a voltage-controlled oscillator (VCO), in the Int-N PLL to suppress noise coming from the power line. Thus, the inputs and output of FDIV are VDD and AVDD levels, respectively. F_VCO is the Int-N PLLs’ output clock that is used for operating clock for itself and creating EDG1_VDD and EDG2_VDD whose time difference of falling edges is one pulse F_VCO. SUMDIV is a ∆∑ modulated divisor signal, divided into three signals, INT_COARSE and INT_FINE, and FRAC. FDIV counts sets of eight pulses based on INT_COARSE, individual pulses based on INT_FINE, and then generates interpolated pulses based on FRAC.

Figure 4a shows the conceptual block diagram to count fractional pulses in the case the where the divisor is 43 + 19/32. It has a feedback loop to consider the previous fractional remainders (13/32, 26/32, and 7/32 in Figure 4b), and includes two dividers with divisors of 8 and 1, respectively, generating quotients and remainders. Signals in the second cluster of Figure 4b are described at each node. The quotient of the divider with the divisor of 8 is used as the output of the coarse path. The remainder of the divider with divisor of 8 is fed into the divider with a divisor of 1, generating both outputs of the fine path and fractional path. In Figure 4b, three clusters of pulses are described. Let us take a look at the leftmost cluster of the pulses. FDIV counts five sets of eight pulses, three pulses and generates 19/32 pulses. In the following cluster, FDIV counts five sets of eight pulses, three pulses as before, but generates 6/32 pulses. It is just because 13/32 pulses have already been generated in the previous cluster, resulting in 19/32 pulses in total in the second cluster. Likewise, FDIV counts fractional pulses. In actual operation, FDIV counts fractional pulses in 24-bit words by using a ∆∑ modulated divisor signal, SUMDIV, and 5-bit PI.

PI described in Figure 3 consists of blocks of level shifters and digitally controlled slope generators. Once PI receives EDG1_VDD and EDG2_VDD, it level shifts from the VDD to AVDD level. The time difference of EDG1_VDD and EDG2_VDD is 1/F_VCO which is a slight amount, such as 312.5 ps at F_VCO = 3200 MHz. If the slew rates and the propagation delay during level shifting are poor, that leads to the degradation of phase interpolation linearity, resulting in increasing EMI. Regarding mass production, ensuring good EMI suppression over PVT variations is crucial. To address this, we employ an inverter-based level shifter by using falling edge. The proposed level shifter can handle lower VDD level signals. Attention is required for the amount of node loads for level-shifted signals. Thus, we divide 5-bit PI into two, 3 bits for upper and 2 bits for lower, to reduce the number of MUXs connected to the sensitive nodes while keeping the required linearity performance. We employ CMOS-switch MUXs without any code-dependent impact on the loads of the sensitive nodes, ensuring balanced slew rates and propagation delays across different digital values and PVT variations. For analog operations during interpolation, we use digitally controlled current units, a capacitor to hold charge, and an inverter to generate the output edges. The interpolated time value is not affected by the absolute amount of current, capacitor, and the threshold voltage of the inverter, leading to high immunity to PVT variations [17,18]. The developed auto-region-keeping (ARK) technique [17,18] also contributes it. Furthermore, we consider the effects of the gate capacitor change during interpolation, resulting in the difference in waveform from ideal one. We discuss them in detail in the following section.

3. Circuit Design of the Phase Interpolator with Immunity to PVT Variations

Several PIs have been reported before such as in [8,9,10,22,23,24]. Some of them use multi-phase clocks for phase interpolation. Unlike them, our PI does not need multi-phase clocks for attachable or manageable design. In addition to that, it has high immunity to PVT variations, as mentioned earlier.

Figure 5 shows the conceptual schematics and waveforms to explain the phase-interpolating principle which includes three steps. The interpolator consists of capacitor C, current cells with switches (DAC), and inverter INV. The operation is similar to [21], but our PI does not need a T_VCO-width pulse, which is hard to generate as the frequency is higher. In the first step, all switches are off and the capacitor has been charged by connecting the node VCAP to AVDD during REFRESH. In the second step, whose period is T_VCO, current cells are selected according to the value of SEL_EDG1 to make the first slope the slew rate (SEL_EDG1 + 1) × I_b/C. In the third step, all current cells are used to make the second slope whose slew rate is 32 × I_b/C regardless of the value of SEL_EDG1. Once VCAP crosses V_{TH_INV}, the threshold voltage of INV, F_{FB_FRAC} increases. The time from the end of the T_VCO period to the positive edge of F_{FB_FRAC} is calculated as

$$T_{os}+\left(31-SE{L}_{EDG1}\right)\frac{T_{VCO}}{32}$$

(1)

where Tos is the time offset defined as

$$T_{os}\equiv \frac{C\left(AVDD-V_{TH\_INV}\right)}{32I_b}-T_{VCO}.$$

(2)

According to Equation (1), the timing of F_{FB_FRAC}’s positive edge can be controlled by LSB of T_VCO/32 that is not affected by PVT variations (DNL = −0.28/+0.29, INL = −0.94/+0.89 in F_VCO = 4 GHz). Tos can be considered as a constant delay in the feedback loop. In our design, at the maximum corner, Tos is 2.36 ns; this is small enough to keep the PLL stable. As a result, unlike [20], a calibration circuit is not needed.

Figure 6a shows the detailed circuit diagram of the level sifters for EDG1_VDD and EDG2_VDD. Figure 6b shows the waveforms of the level shifters when making AVDD signals which are fed into the slope generator.

The operation of each level shifter is divided into three stages. At the first stage, AVDD-level pulses are made from VDD-level pulses. To operate with lower VDD, falling edges of inputs are used to make rising edges of EDG1 and EDG2 whose voltage level is AVDD and the time difference between edges is T_VCO. High drivability for the node VM is needed to lower the skew between EDG1 and EDG2 which is related to the propagation delay of the level shifter. When the input signal is high, NMOS of the first stage drives the node VM and the drivability strongly depends on the level of VDD. On the other hand, when the input signal is low, MP1 determines the drivability for VM regardless of VDD voltage level. Using falling edges for the level shifter is a good way to handle the low-level input signal and obtain high drivability. However, the shoot-through current flows while waiting for the input falling edge. The period of the current is controlled using REFRESH and F_{FB_VCAP} to reduce power consumption. The peak current at the both ends is suppressed by using the degeneration resistor R_D to avoid unexpected bad effects like IR-drop via a shared power line. R_D2 in the third inverter is used for the same reason. To get high drivability and acceptable shoot-through current at the same time, the PMOS size and the NMOS size of the first stage are larger and smaller in terms of aspect ratio. Similarly, the aspect ratios of the NMOS in the second stage and the PMOS in the third stage are large to obtain a high slew ratio for edges that determine the skew performance. This inverter-based level shifter can perform better in terms of propagation delay and an ability to handle low-voltage input compared to cross-coupled level shifters (

Table 1. Comparison of level shifters.

Level shifter topology	Cross-coupled	Inverter-based
Current consumption
Propagation delay
Low voltage input

). The simulated skew between EDG1 and EDG2 is −5.18 ps/+5.79 ps over PVT variations using a Monte Carlo simulation. The maximum propagation delay of the level shifter is 291 ps.

Figure 7a shows the detailed circuit diagram of the slope generator. It consists of a switch to charge the node VCAP, DACs (DAC_A and DAC_B), and a capacitor. Figure 7b shows the timing diagram. Close-up views of VCAP’s waveform are shown on the bottom.

The slope of VCAP is generated by discharging the capacitor C with DACs. The first slope is digitally controlled according to the 10-bit signal SEL_EDG1 fed into each MUX to control switches (SW1–SW11). The slew ratio of the second slope is a fixed value determined by using all the current cells whose amount is 32I_b in total. We use two DACs to make the 5-bit slope generator. DAC_A is designed for lower 2-bit with I_b-current cells. DAC_B is designed for upper 3-bit with 4I_b-current cells. If we use 32 I_b-current cells, it seems we can obtain better linearity. However, the load capacitors of EDG1 and EDG2 increase because thirty-two MUXs are required. That degrades the slew ratio performance of the rising edges on the nodes, resulting in degradation of linearity. In our design, eleven MUXs are used and the load on the nodes is small enough to meet our linearity criteria. REFRESH controls the switch to charge the capacitor C. After charging, all switches connected to VCAP are OFF. At that time, VCAP is a high impedance node whose voltage is AVDD and the circuit is waiting for the rising edges of EDG1. The principle of phase interpolation is already mentioned above. In this section, let us see an operation example for two periods of 1/F_REF in which the values of SEL_EDG1 are 0 and 5 for the first period and the second period, respectively. SEL_EDG1 is calculated based on the control signal SUMDIV and updated at the falling edge of REFRESH as shown in Figure 7b. The value of SEL_EDG1 determines the number of switches that are ON during the first slope. As shown in Figure 7a, select the pin of one of the MUXs in DAC_A as AVDD. That means EDG1 is selected and SW0 is always ON during the first slope. When SEL_EDG1 is 0, SW0 is ON and the others are OFF during the first slope. When SEL_EDG1 is 5, SW0, SW1, and SW4 are ON and the others are OFF during the first slope. As a result, interpolated time periods of 31/32 × T_VCO and 26/32 × T_VCO are obtained.

Figure 8a shows the detailed circuit of the MUX used in each DAC block. It consists of switches and inverters. We use this circuit to make the load capacitors of EDG1 and EDG2 equal regardless of the value of SEL_EDG1.

Before we explain the advantage of our MUX, let us introduce an example of using a MUX with NANDs shown in Figure 8b. In this case, three NANDs are used. One of the NANDs receives the signal EDG1 and the control signal SEL_EDG1 which is 1-bit logic signal fed into each MUX. Another receives the signal EDG2 and the control signal $\overline{{\mathrm{S}\mathrm{E}\mathrm{L}}_{\mathrm{E}\mathrm{D}\mathrm{G}1}}$. Outputs of the two MUXs are connected to the other MUX whose input loads are matched. If this MUX is used for DACs, the load capacitances of EDG1 and EDG2 are changed in accordance with the value of the 10-bit control signal SEL_EDG1. Considering the EDG1′s load of a MUX shown in Figure 8b, there are two statuses with different levels of SEL_EDG1. When the slope generator is waiting the rising edge of EDG1 and SEL_EDG1 is high, the source voltage of the NMOS whose gate is EDG1 is GND. On the other hand, When SEL_EDG1 is low, the node VM in Figure 8b is floating so the voltage is not necessarily GND. This difference in the NMOS bias conditions leads to the difference in the gate capacitors’ amount that causes the control-value-dependent load. For example, when the value of the 10-bit control signal SEL_EDG1 is 4, two MUXs are in the first load status while awaiting the rising edge of EDG1 and the other MUXs are in the second load status. However, when the value of the 10-bit control signal SEL_EDG1 is 7, five MUXs are in the first load status. For the node EDG2, this occurs as well. This control-value-dependent load changes the slew ratios of EDG1 and EDG2 that leads to linearity degradation of the phase interpolator. To avoid it, we use the MUX described in Figure 8a. Switches (CMOS switches) are used instead of NAND gates. The MUX has the main signal path and dummy path. EDG1 is connected to two switches. One of them is in the dummy path whose switches are controlled using inverted control signals for the main signal path. In Figure 8a, when the slope generator is awaiting the rising edge of EDG1 and SEL_EDG1 is high, the main load on EDG1 is the inverter in the main signal path. When SEL_EDG1 is low, the main load on EDG1 is the inverter in the dummy path. We use identical inverters that connected to switches so the load on EDG1 does not change according to the control signal. For the node EDG2, it works in the same manner.

Figure 9b,c shows current cells used in DAC_A and DAC_B. The dummy path is connected to AVDD via an always-on PMOS. Each current cell has a dummy current path to keep M_B in saturation while SW is low. This is very important to avoid degradation of the phase interpolation linearity. The amount of I_b is from 3.9 μA to 7.4 μA over PVT variations using Monte Carlo simulation. Without a dummy path, this amount of current is not enough to charge the parasitic capacitor at the drain of M_B immediately. I_b is for a current unit in DAC_A. Additionally, 4 × I_b in total is for a current unit in DAC_B. An identical circuit is used for each current units for good matching performance. Figure 9a shows the bias generator for the current cells. A high-performance bias generator is not required because of high immunity to PVT variations as shown in Equation (2). We do not need a complicated circuit or start-up circuit for the bias generator. In this design, a simple bias generator is used. It consists of diode-connected MOSs and a resistor.

Figure 10a shows the circuit diagram to explain the operation to make the second slope on VCAP in detail. A MUX, a bias generator, and a DAC are described in it. This occurs when making the second slope in Figure 10b by discharging C on VCAP using the current I_VCAP. Note that all current DAC cells are described as one DAC cell so 32 × I_b flows in M_B. Gate capacitors (C_gs and C_gd) of M_SW and M_BC are shown around them. In Figure 10b, current flowing on the wires in DAC is blue and current fed onto the wires in DAC via gate capacitors is red. After the first slope, the voltage of VCAP goes down with all DAC cells to generate the second slope. The second slope of VCAP can be divided into three parts below: (1) M_SW and M_BC are in saturation; (2) M_SW is in triode; M_BC is in saturation; (3) M_SW and M_BC are in triode. The lower VCAP goes down, the lower its slew ratio gets. When VCAP has relatively high voltage, M_SW and M_BC are in the saturation region (part (1)), so the red currents are negligible because C_gd is small and the voltage of Cgs is constant.

At that time, I_VCAP is almost the same as 32 × Ib. And then, M_SW turns into a triode region due to its small VDS (part (2)). The Cgd of M_SW gets bigger and the voltage of the gate capacitors of M_SW changes, resulting in the current via the capacitors (I_SW1 and I_SW2). On the other hand, M_BC is still in saturation, so I_VCAP is calculated as 32 × I_b − I_SW1 − I_SW2. That is why the slew ratio in part (2) is lower compared to part (1). In the next part, M_BC also turns into a triode region. The current vi gate capacitors (I_BC1 and I_BC2) flow into the main path of DAC. This current is some part of I_BC which is supposed to be fed to the diode-connected NMOS in the bias generator. When M_BC is in the triode region, the current of the diode-connected NMOS to make V_BC is I_BC − I_BC1 − I_BC2 (I’_BC). This current decrease leads to a voltage change in V_BC. When we design the size of M_BC and the amount of I_BC, we should consider it. I_VCAP is calculated as 32 × I_b − I_SW1 − I_SW2 − I_BC1 − I_BC2 in the same manner as above. Despite various slew ratios in the second slope, the phase interpolator can work neatly because the slew ratio change points are determined by the voltage of VCAP. Note that VCAP stops going down to keep M_B in the saturation region using ARK technique after making an interpolated edge.

4. Measurement Results

In this section, we provide a comprehensive set of measurement results in addition to the ones in [17,18]. You will gain insight into the immunity of our developed fractional divider to PVT variations. In our SoC chip, there are five Frac-N PLLs and each has SSC capability. Each Frac-N PLL has been created by recycling an existing Int-N PLL and attaching the developed factional divider. During measurement, we can easily control its operation modes including integer-N, fractional-N, and SSCG.

Figure 11 shows the measured output spectrum, and the fractional spur is −69.3 dBc. This suppressed spur indicates that the resolution of the phase interpolation is high enough and the developed PI operates precisely as designed. Figure 12 shows the measured output phase noise, when the PLL is operating in fractional mode and integer mode, measured at F_VCO/64 using a 30 MHz reference. The integrated RMS jitter values of the fractional and integer mode are 5.99 ps_rms and 5.64 ps_rms, respectively. Only 0.35 ps_rms of integrated RMS jitter degradation is achieved. That means the divider has a minor impact on jitter and is suitable for a wide range of products.

Figure 13 shows the measured frequency differences over process variations between ideal output frequencies and measured frequencies in the fractional mode. Three samples for each process corner are measured using typical voltage supplies (AVDD = 1.8 V and VDD = 0.8 V). For instance, SF means that NMOSs in the sample are in slow condition and PMOSs are in fast condition. As you can see, the fractional divisor dependence is small. This signifies that we can control the output frequency using finely tuned steps, which minimizes EMI within the limited available frequency bands. Furthermore, the developed divider has high immunity to process variations. The characteristics deteriorate with higher F_VCO and F_REF. Nevertheless, the frequency difference is 19.64 kHz in an SS condition which is 6.14 ppm.

The measured frequency time trend and its output spectrum in the SSC mode are shown in Figure 14. Modulation depth is calculated from center frequency and the amplitude that is obtained by using dashed lines indicating up/down slopes. The modulation frequency, depth, and profile are 20 kHz, 6%_P-P, and triangle, respectively. An 18.7 dB EMI reduction is measured. We provide comprehensive measurement results in terms of modulation depth going forward that enhance product reliance.

Figure 15 shows the measurement results of modulation depth at different process corners in terms of MOSs. Three samples for each process corner are measured with typical voltage supplies in room temperature. The SSC modulation profile is a triangle center spread. The center frequencies are 1600 MHz and 3200 MHz with two conditions of modulation frequency: 20 kHz and 62.5 kHz. The reference frequency is 10 MHz. Modulation depth settings are 1%_P-P and 6%_P-P. The measurement results show that the process dependance of the modulation depth is almost nothing.

The measured temperature dependance of modulation depth is shown in

Table 2. The measured temperature dependance of modulation depth.

Temperature [°C]	Modulation Depth [%P-P]
	SF Sample	FS Sample
−40	5.94	5.94
27	5.95	5.95
125	5.96	5.96

with two worse samples with typical voltage supplies. The modulation frequency, depth, and profile are 62.5 kHz, 6%_P-P, and triangle, respectively. The center frequency and reference frequency are 1600 MHz and 10 MHz, respectively. As you can see, the temperature dependances are extremely small.

The summary of PVT dependencies for modulation depth is presented in

Table 3. Summary of PVT dependencies for modulation depth.

Items	Conditions	MIN	MAX	Unit
Process	TT, SS, FF, SF, FS	5.944	6.005	%P-P
Voltage	0.61 V–0.75 V	5.990	5.993	%P-P
Temperature	−40 °C–125 °C	5.946	5.961	%P-P

with a modulation setting of 6%_P-P. As you can see, the performance remains unaffected by PVT variations. The maximum deviation from the setting is only 0.056 pt, occurring under the SF process condition. Each performance of the modulation depth over PVT variations is the same difference, but we have confirmed that the degradation slightly increases in the case of higher modulation frequency.

The measured VDD supply dependance of modulation depth is shown in Figure 16a. The modulation frequency, depth, and profile are 16.13 kHz, 6%_P-P, and triangle, respectively. The center frequency and reference frequency are 1280 MHz and 20 MHz, respectively. The level of AVDD supply is a typical value. Thanks to the inverter-based level shifter, phase interpolation can work neatly at 0.61 V, which is 0.19 V lower than typical voltage of VDD. Figure 16b shows measured frequency waveforms at various VDD levels.

According to Figure 15 and Figure 16, the developed fractional divider has high immunity to temperature and voltage supply. This performance is important because users’ reliance on our products’ quality during temperature and voltage drift is crucial.

A performance summary and comparison with prior work are given in

Table 4. Performance summary and comparison with prior work.

	PLL with The Proposed Divider	[15] JSSC 2021	[16] JSSC 2023	[11] SSCL 2020	[12] TMTT 2020	[13] ISSCC 2022	[14] ISSCC 2022	[21] Electronics 2023
Technology [nm]	12	14	12	65	55	65	22	110
Mode	Frac-N/ SSCG	Frac-N	Frac-N	Frac-N	Frac-N/ SSCG	Frac-N	Frac-N	Frac-N
Fractional Spur [dBc]	−69.3	<−72	−45.6	−69	-	−64	−51	<−69
Integrated RMS jitter [ps]	5.64 (Int-N) 5.99 (Frac-N)	0.08	4.66	0.503	0.63 (ssc off)	0.188	0.64 (Int-N) 0.83 (Frac-N)	0.86 (Frac-N)
Modulation Depth [%P-P]	0–6	-	-	-	0.5	-	-	-
Modulation Frequency Range [kHz]	20–60	-	-	-	31.5	-	-	-
PLL Power [mW]	3.2	14.2	3.91	6.9	46.5	15.67	1.09	20.3
PLL Area [mm2]	0.0242	0.31	0.063	0.24	0.092	0.139	0.12	1.49
VCO Frequency/ (Range) [MHz]	4200 (1280–4200)	6200 (5000–7000)	2400.6	3537.1 (3200–3800)	5000	5200 (4400–5400)	2300 (2000–2480)	2500 (2200–2800)
VCO Type	Ring	LC	Ring	LC	Ring	Ring	LC	LC

. The PLL with the FDIV is fabricated in a 12 nm FinFET CMOS process and its area is 0.0242 mm². At 4.2 GHz in fractional mode, the power consumption is 3.2 mW, where the analog and digital parts consume 2.47 mW (measured) from 1.8 V supply and 0.73 mW (simulated) from 0.8 V supply, respectively. Only 0.35 ps_rms of integrated RMS jitter degradation is achieved at 4.2 GHz. Additionally, 24-bit frequency adjustment steps and SSC capability help in avoiding EMI. Die micrographs of the SoC and the PLLs are shown in Figure 17.

5. Conclusions

The attachable fractional divider transforming an Int-N PLL into a Frac-N PLL and its circuit techniques are described in this article. The circuit is fabricated in a 12 nm FinFET CMOS process. The attachable fractional divider can improve time-to-market because complicated wiring is not required and it can be available for various types of Int-N PLLs. The linearity performance of the 5-bit PI is DNL = −0.28/+0.29, INL = −0.94/+0.89 in F_VCO = 4 GHz over PVT variations using a Monte Carlo simulation. Circuit techniques such as interpolation with high immunity to PVT variations, the level shifter design for acceptance of low VDD, and region-keeping are explained. They can help us use the divider for many products. We provide a comprehensive set of measurement results with transformed Frac-N PLL. In fractional mode, the frequency difference is only 19.64 kHz at F_VCO = 3200 MHz in an SS condition which is 6.14 ppm. According to the comprehensive measurement in terms of modulation depth in SSC mode, the transformed PLL has high immunity to PVT variations. The developed attachable fractional divider enhances both time-to-market and product reliance.