Analytical Delay Modeling for a Sub-Threshold Cell Circuit with the Inverse Gaussian Distribution Function

Abstract

Considering that power consumption (PC) is an extremely important indicator in digital circuit design, lower PC has always been our pursuit. PC and power supply voltage are positively correlated, and in this case, we must reduce the operating voltage of the circuit. However, as the voltage continues to decrease, various secondary effects and process variations become increasingly influential, making the delay distribution and its statistical characteristics more difficult to predict. In this paper, an inverse Gaussian distribution is used to model the propagation delay. Taking into account the local process variation, the multi-input delay analytical expression is derived according to the sub-threshold current formula to accurately predict the distribution and statistical characteristics of the delay, and the delay is obtained by calculation instead of Monte Carlo simulation, which greatly reduces the simulation time. The accuracy of the delay expression and delay distribution have been tested under 22 nm FDSOI technology and good results were obtained with operating voltages from 0.20 V to 0.30 V, in which the mean error of the delay is approx. 1.5%, the variance error is approx. 4.3%, and the error of the cumulative distribution function is approx. 2%.

1. Introduction

With transistor sizes continuing to shrink and the need to reduce power consumption, complementary metal–oxide semiconductor (CMOS) circuits under sub-threshold logic are becoming increasingly used [1,2]. Since power consumption and operating voltage are positively correlated, the sub-threshold region provides better energy efficiency compared to the near-threshold region and super-threshold region [3]. However, as the operating voltage decreases, various secondary effects and process variations become increasingly influential. The primary sources of process variations that affect device performance are random dopant fluctuations (RDFs) and channel length variation [3], in which the RDFs mainly cause the variations in the threshold voltage for transistors, and the channel length variation affects the electrical properties, increasing the threshold voltage for short channel devices. Moreover, there are many other variations, including mobility fluctuation, channel width variation, oxide charge variation, and so on. In the sub-threshold region, the propagation delay is much larger than that in other regions due to process variations [4], and its prediction faces great challenges. Under normal voltages, the delay of the cell circuits follows the Gaussian distribution, as shown in Figure 1a. However, the delay has a nonlinear relationship with the variation in the sub-threshold region, resulting in the delay distribution being difficult to predict, as shown in Figure 1b.

At present, the authoritative method is to use Monte Carlo (MC) SPICE simulation to obtain the propagation delay; however, this method requires a lot of time in each state, so it is necessary to find a suitable method to accurately and quickly predict the gate delay and its distribution. For this, some scholars have undertaken extensive research in this field. The paper [5] presented an error-aware model for arithmetic and logic circuits that accurately estimated the propagation delay of output bits in a digital module, but its operation was time-consuming. In [3], Abu-Rahma studied the effect of random fluctuation variation on the gate delay variation and derived a simple and scalable statistical model to efficiently estimate delay variation at conventional and ultra-threshold voltages. Caltech derived a delay model suitable for the near-threshold region (NTV), and obtained good results [6]. In [7], the authors derived a new simplified drain current model to clarify the relationship between supply voltage (near threshold) and delay, and analyzed its statistical characteristics with a logarithmic distribution; however, the error was unacceptable (13%). In [8], a statistical timing model for a CMOS inverter was proposed in the NTV region under process variation considering fast and slow input, which was derived analytically with a novel segmented step approximation method to overcome the integral issue of the drain current equation for ramp input. In 2019, Southeast University established a statistical model of near-threshold drain current and gate delay based on a logarithmic skew normal (LSN) distribution by using moment matching technology, and the prediction sensitivity error of gate delay was less than 8% [9]. The studies [10,11,12] used machine learning methods to model the delay and obtained good results; nevertheless, this still required a large data set, and it did not physically explain the relationship between the delay and various parameters.

This paper first proposes a probability density function suitable for the delay distribution in the sub-threshold region, i.e., the inverse Gaussian distribution, and indicates the required modeling parameters, see Section 2. Then, according to the classic sub-threshold current expression, the transition time variable is introduced, which is divided into two parts: fast input and slow input, and the equation is constructed by Kirchhoff’s law. Following this, the analytical expression of the mean delay and variance in the case of multiple inputs is derived, as detailed in Section 3. Section 4 verifies the derived expression and predicts the delay distribution and related error calculations with the calculation results. Section 5 summarizes all the study.

2. Statistical Distribution Model of Delay

The inverse Gaussian distribution (IGD) is a commonly used distribution in statistics [13] with its density function given in Equation (1):

$$f\left(x,\mu ,\lambda \right)={\left[\frac{\lambda }{2\pi x^3}\right]}^{1/2}exp\left(\frac{-\lambda {(x-\mu )}^2}{2{\mu }^{2}x}\right);x>0, \mu >0, \lambda >0$$

(1)

where x is the independent variable, $\lambda$ represents the shape coefficient, and $\mu$ represents the expectation of the function. It has been confirmed that the characteristics of the inverse Gaussian distribution function and delay distribution are very similar [14,15], and both the super-threshold region and the delay distribution of the sub-threshold region can be fitted very well. Figure 1a,b shows the results of fitting with the inverse Gaussian distribution under 0.6 V and 0.2 V, respectively, and Figure 2a,b is their corresponding cumulative distribution function curves (CDF). It can be found that the graph coincidence is very high, so this paper uses the IGD probability density function to predict the delay distribution curve, and the parameters of the function ($\mu$, $\lambda$) will be modeled with delay in the following section. In this article, the delay is represented by $Td$, and the correspondences are as follows:

$$\mu \left(Td\right)=\mu ; {\sigma }^2\left(Td\right)=\frac{{\mu }^3}{\lambda }$$

(2)

3. Delay Modeling

In this article, we consider variations in the threshold voltage as the main factor affecting the propagation delay, and the influence of other process variations can be translated into effective variations of the threshold voltage [3]. Therefore, the current selected in this article is a classic current expression containing the threshold voltage.

Drain–source current in the sub-threshold region for NMOS and PMOS [16] can be expressed as

$$I_n=I_{0n}·e^{\frac{Vin\left(t\right)-Vthn-Vthb}{m_n{V}_T}}·e^{\frac{{\lambda }_{n}Vds}{m_n{V}_T}}·\left(1-e^{-\frac{Vds}{V_T}}\right)$$

(3)

$$I_p=I_{0p}·e^{\frac{\left(\left|Vin\left(t\right)\right|-\left|Vthp\right|-\left|Vthb\right|\right)}{m_p{V}_T}}·e^{\frac{{\lambda }_p\left|Vds\right|}{m_p{V}_T}}\left(1-e^{-\frac{\left|Vds\right|}{V_T}}\right)$$

(4)

where $I_{0n}={\mu }_n{C}_{ox}\frac{W_n}{L_n}\left(m_n-1\right)V_T^2$; $I_{0p}={\mu }_p{C}_{ox}\frac{W_p}{l_p}\left(m_p-1\right)V_T^2$, with the subscripts n and p here referring to NMOS and PMOS, respectively; $\mu$ is carrier mobility; $C_{ox}$ is gate oxide capacitance; $\frac{W}{L}$ is the width to length ratio; $m$ is sub-threshold slope; $V_T$ is thermal voltage; $\lambda$ represents the drain-induced barrier lowering (DIBL) effect coefficient; $Vth$ represents the threshold voltage at zero bias; and $Vthb$ is the increment of the threshold voltage caused by the body effect.

For inverters, taking the falling propagation delay ($Td$) as an example, it can be defined as the difference between the moment t at which the output voltage drops to $Vdd/2$ and the time at which the operating voltage rises to $Vdd/2$, shown as

$$Td=t-\frac{\tau }{2}$$

(5)

where τ is the input transition time. At this time, it is necessary to consider the changes of the input voltage waveform and the output voltage waveform. Figure 3 depicts the input waveform (I) and the output waveform (II, III) curves. According to the size of the input transition time, it can be divided into fast input and slow input [17]. When the delay is greater than half of the input transition time, time t0, or when the output voltage drops to $Vdd/2$ after the input transition time τ, we consider this to be a case of fast input, as shown in Figure 3II, and vice versa in Figure 3III.

According to Figure 3, the input voltage can be expressed as

$$Vin\left(t\right)=\left\{\begin{array}{cc}Vdd\frac{t}{\tau },\hfill & 0\le t\le \tau \\ Vdd,\hfill & t>\tau \end{array}\right.$$

(6)

The current can be re-expressed as [18]

$$I_{d0}={\mu }_n{C}_{ox}\frac{W_n}{L_n}\left(m_n-1\right)V_T^2·e^{\frac{\frac{t}{\tau }Vdd-Vthb-Vthn}{m_n{V}_T}}·e^{\frac{{\lambda }_{n}Vds}{m_n{V}_T}}\left(1-e^{-\frac{Vds}{V_T}}\right) t<\tau$$

(7)

$$I_{d1}={\mu }_n{C}_{ox}\frac{W_n}{L_n}\left(m_n-1\right)V_T^2·e^{\frac{Vdd-\left|Vthb\right|-\left|Vthn\right|}{m_n{V}_T}}·e^{\frac{{\lambda }_{n}Vds}{m_n{V}_T}}\left(1-e^{-\frac{Vds}{V_T}}\right) t>\tau$$

(8)

Next, we will derive the analytical expressions of the output voltage waveform and propagation delay for different situations.

3.1. Output Voltage Calculation

3.1.1. 0 ≤ t ≤ τ

According to Kirchhoff’s current law (KCL) [19] at $Vout\left(t\right)$:

$$C_{tot}\frac{dVout\left(t\right)}{dt}=-I_{d0}$$

(9)

where $C_{tot}$ is the sum of the load capacitance and the coupling capacitance.

In this case, $Vgs=Vin\left(t\right)=\frac{Vdd}{\tau }t$, $Vds=Vout\left(t\right)$, and these are substituted into Equation (7) and the equation is phase shifted:

$$\frac{dVout\left(t\right)}{e^{\frac{{\lambda }_{n}Vout\left(t\right)}{m_n{V}_T}}·\left(1-e^{-\frac{Vout\left(t\right)}{V_T}}\right)}=\frac{-I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}}{C_L}·e^{\frac{\frac{Vdd}{\tau }t}{m_n{V}_T}} dt$$

(10)

It is clear that this equation is unsolvable, so we have to use the approximation method to solve it. For inverters, an important point used to obtain the delay is when the output voltage drops to $Vdd/2$, and when $Vout\left(t\right)=Vdd/2$, $e^{-\frac{Vout\left(t\right)}{V_T}}$ is small enough to be ignored, as shown in Equation (11):

$$\frac{dVout\left(t\right)}{e^{\frac{{\lambda }_{n}Vout\left(t\right)}{m_n{V}_T}}}=\frac{-I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}}{C_{tot}}·e^{\frac{\frac{Vdd}{\tau }t}{m_n{V}_T}} dt$$

(11)

By integrating both sides of the above equation and substituting the initial condition $Vout\left(t\right)=Vdd \mathrm{when} t=0$, we can obtain the expression of $Vout\left(t\right)$ [18]:

$$Vout\left(t\right)=\frac{-m_n{V}_T}{{\lambda }_n}·ln\left(\frac{I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}{\lambda }_n\tau }{Vdd·C_{tot}}\left(e^{\frac{Vdd}{m_n{V}_T\tau }t}-1\right)+e^{-\frac{{\lambda }_{n}Vdd}{m_n{V}_T}}\right)$$

(12)

At the same time, we can obtain $Vout\left(\tau \right)$:

$$Vout\left(\tau \right)=\frac{-m_n{V}_T}{{\lambda }_n}·ln\left(\frac{I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}{\lambda }_n\tau }{Vdd·C_{tot}}\left(e^{\frac{Vdd}{m_n{V}_T\tau }\tau }-1\right)+e^{-\frac{{\lambda }_{n}Vdd}{m_n{V}_T}}\right) =\frac{-m_n{V}_T}{{\lambda }_n}·ln\left(\frac{I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}{\lambda }_n\tau }{Vdd·C_{tot}}\left(e^{\frac{Vdd}{m_n{V}_T}}-1\right)+e^{-\frac{{\lambda }_{n}Vdd}{m_n{V}_T}}\right)$$

(13)

3.1.2. t > τ

In this case, $dVin\left(t\right)=0,Vin=Vdd$; substituting these into Equation (8) and phase shifting, then integrating and substituting the initial condition $Vout\left(t\right)=Vout\left(\tau \right) \mathrm{when} t=\tau$, we can obtain the expression:

$$Vout\left(t\right)=\frac{-m_n{V}_T}{{\lambda }_n}·ln\left(\frac{I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}{\lambda }_n}{C_{tot}{m}_n{V}_T}{e}^{\frac{Vdd}{m_n{V}_T}}\left(t-\tau \right)+e^{-\frac{{\lambda }_{n}Vout\left(\tau \right)}{m_n{V}_T}}\right)$$

(14)

3.2. Analytical Expression for Delay

3.2.1. Fast Input

Fast input occurs in the case of $t>\tau$. By substituting Equation (14) into $Vout\left(t\right)=vdd/2$, we can obtain the time t0 at this time.

$$t0=\frac{C_{tot}{m}_n{V}_T}{I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}{\lambda }_n}{e}^{\frac{-Vdd}{m_n{V}_T}}\left(e^{-\frac{{\lambda }_{n}Vdd}{2m_n{V}_T}}-e^{-\frac{{\lambda }_{n}Vout\left(\tau \right)}{m_n{V}_T}}\right)+\tau$$

(15)

According to the definition of delay, we can find its expression as follows:

$$Td=t0-\frac{\tau }{2}=\frac{C_{tot}{m}_n{V}_T}{I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}{\lambda }_n}{e}^{\frac{-Vdd}{m_n{V}_T}}\left(e^{-\frac{{\lambda }_{n}Vdd}{2m_n{V}_T}}-e^{-\frac{{\lambda }_{n}Vout\left(\tau \right)}{m_n{V}_T}}\right)+\frac{\tau }{2}$$

(16)

In order to increase the applicability of this formula, we introduce a coefficient k0 of the number of samples in the MC simulation, which is performed later for MC verification; it can be simulated any number of times for verification. When the number of simulations is fixed, this coefficient is a constant, generally around 1. The new expression is

$$Td=k0·\frac{C_{tot}{m}_n{V}_T}{I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}{\lambda }_n}{e}^{\frac{-Vdd}{m_n{V}_T}}\left(e^{-\frac{{\lambda }_{n}Vdd}{2m_n{V}_T}}-e^{-\frac{{\lambda }_{n}Vout\left(\tau \right)}{m_n{V}_T}}\right)+\frac{\tau }{2}$$

(17)

In order to find the variance of the delay, we need to sort out the above expression and combine the same influencing factors. The result is as follows:

$$Td=k0·\frac{C_{tot}{m}_n{V}_T}{I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}{\lambda }_n}{e}^{\frac{-Vdd}{m_n{V}_T}}\left(e^{-\frac{{\lambda }_{n}Vdd}{2m_n{V}_T}}-e^{-\frac{{\lambda }_{n}Vdd}{m_n{V}_T}}\right)+\tau ·[\frac{1}{2}-k0·\frac{m_n{V}_T}{Vdd}·\left(1-e^{\frac{-Vdd}{m_n{V}_T}}\right)]$$

(18)

Therefore, the variance ${\sigma }^2\left(Td\right)$ can be written as

$${\sigma }^2\left(Td\right)=[\frac{k0·C_{tot}{m}_n{V}_T}{I_{0n}{\lambda }_n}{e}^{\frac{-Vdd}{m_n{V}_T}}\left(e^{-\frac{{\lambda }_{n}Vdd}{2m_n{V}_T}}-e^{-\frac{{\lambda }_{n}Vdd}{m_n{V}_T}}\right){]}^2·{\sigma }^2\left(e^{\frac{Vthb+Vthn}{m_n{V}_T}}\right)+{\left[\frac{1}{2}-\frac{k0·m_n{V}_T}{Vdd}·\left(1-e^{\frac{-Vdd}{m_n{V}_T}}\right)\right]}^2·{\sigma }^2\left(\tau \right)$$

(19)

In fact, for the cell circuit, the change in input transition time does not have a large effect on the variance of the delay. Changes in the process parameters can be represented by variance changes in the threshold voltage, so the second half of the above expression can be removed to reduce the amount of calculation.

$${\sigma }^2\left(Td\right)=[k0·\frac{C_{tot}{m}_n{V}_T}{I_{0n}{\lambda }_n}{e}^{\frac{-Vdd}{m_n{V}_T}}\left(e^{-\frac{{\lambda }_{n}Vdd}{2m_n{V}_T}}-e^{-\frac{{\lambda }_{n}Vdd}{m_n{V}_T}}\right){]}^2·{\sigma }^2(e^{\frac{Vthb+Vthn}{m_n{V}_T}})$$

(20)

3.2.2. Slow Input

Slow input occurs in the case of $0\le t\le \tau$. By substituting Equation (12) into $Vout\left(t\right)=Vdd/2$, we can obtain the time t1 at this time.

$$Td=t1-\frac{\tau }{2}=k0\frac{m_n{V}_T\tau }{Vdd}ln[\frac{Vdd·C_{tot}}{I_{0n}·e^{\frac{-Vthb-Vthn}{m_n{V}_T}}{\lambda }_n\tau }(e^{\frac{-{\lambda }_{n}Vdd}{2m_n{V}_T}}-e^{-\frac{{\lambda }_{n}Vdd}{m_n{V}_T}})+1]-\frac{\tau }{2}$$

(21)

Similarly, solving the variance requires ignoring the effect of the input transition time on the propagation delay variance, and separating the threshold voltage [17], then we can obtain the following equation:

$${\sigma }^2\left(Td\right)={\left(k0\frac{\tau }{Vdd}\right)}^2{\sigma }^2\left(Vthb+Vthn\right)$$

(22)

For more details, please see ‘Appendix B’.

4. Results and Discussion

Before verification, we must undertake preparation to obtain the values of various coefficients in the equations. First, when the temperature is certain, we need to calculate the value of the thermal voltage (KT/q). Then, we sweep Vgs and Vds, respectively, from DC simulation, and use the ratio method to calculate the value of m and λ. Next, we can obtain I0 by the least squares fitting method with the current data from DC. Finally, we can calculate k0 and the variance of the threshold voltage by a standard MC simulation. Although the MC simulation is used here, it is only performed once.

Table 1. Method of obtaining various parameters.

Parameters	Method of Extraction or Calculation
VT	VT = KT/q
Vth	DC simulation, with the command “Vth (*)”
m	DC simulation and ratio method
λ	DC simulation and ratio method
I0	DC simulation and least squares fitting method
k0	MC simulation, calculated by a standard MC delay value
σ2 (Vth)	MC simulation

shows the method of obtaining each coefficient.

In this article, the indicator used to calculate the mean and standard deviation of the delay is calculated as follows:

$${\displaystyle \sum }_1^n\frac{\left|y-y0\right|}{y0}$$

(23)

where y represents model prediction results, and y0 represents the simulation results with HSPICE.

For the distribution function, we generally use the difference between the piecewise integrals of the probability density function (PDF) to measure the error, and the cumulative distribution function (CDF) is the integral of the PDF; thus, the CDF can be used to calculate the indicator, shown as

$${\displaystyle \sum }_1^n\frac{\left|CD{F}_{model}-CD{F}_{MC}\right|}{CD{F}_{MC}}$$

(24)

where $CD{F}_{model}$ represents the CDF of the model prediction results; $CD{F}_{MC}$ is the CDF of the simulation results with HSPICE; and n refers to the n-segment integration of the PDF. According to the classic value [15], here we take n = 5.

4.1. Current Verification

Fully depleted SOI (FDSOI) MOSFETs are ideal for low-power applications due to their superior control of short-channel effects and flexibility of dynamic threshold voltage through the use of back-gate bias [20,21]. In this paper, the model is validated in 22 nm FDSOI technology. First, a DC simulation is performed to obtain the coefficients required for the current; here, we set $Vbs=0$. Additionally,

Table 2. Coefficients from DC.

Transistor	Vth (V)	λ	I0 (A)	M (mV/dec)	${\mathit{V}}_{\mathit{T}} \left(\mathbf{V}\right)$
NMOS	0.324	0.073	7.66 × 10−7	1.462	0.0257
PMOS	−0.325	0.093	7.11 × 10−7	1.504	0.0257

shows the corresponding coefficients at a temperature of T = 25 °C; $\frac{W_n}{L_n}=80 \mathrm{nm}/20 \mathrm{nm}; \frac{W_P}{L_P}=235 \mathrm{nm}/20 \mathrm{nm}$. This set of coefficients only needs to be obtained once, and is further used in subsequent delay calculations.

The nominal value of the DC under different voltages is simulated and compared with the current value calculated by the current formula; the results show a high accuracy, with the error being less than 1%. Figure 4a,b is the current curves of NMOS and PMOS transistors under different Vds and Vgs voltages.

The cell circuit in this paper uses an inverter, and its current is also verified with the above current formula and correlation coefficients. Figure 5a,b is the drain current curves of the inverter. It can be observed that it highly matches the standard current, indicating that a series of delay derivations using this current are feasible.

4.2. Delay Verification

Table 2 lists the coefficients required for the model. Before performing the delay verification, we must perform an MC simulation to obtain the k0 and variance ${\sigma }^2\left(Vthn\right)$.

In order to verify the accuracy of the proposed delay model and prediction method, the mean and standard deviation of the delay for an inverter with the process fluctuation parameter changes are simulated by SPICE using the 22 nm industrial design suite (the golden data are 10,000 samples of MC simulations), with results having a mean error of about 1.5% and a standard deviation error of about 4.3% in the sub-threshold region, indicating very high accuracy.

Figure 6a shows the prediction results of the delay under different voltages and different loads (Cl), and Figure 6b shows the prediction results of the standard deviation compared with MC simulation results.

4.2.1. Transition Time Verification

We also validated the delay modeling of fast and slow inputs under fast input condition. Figure 7a shows the delay prediction results under different load conditions with different input transition times, and Figure 7b shows its standard deviation results.

In order to verify the correctness of the model, we randomly generate some multi-input values, and then predict the result of propagation delay.

Table 3. Partial validation data under fast input condition.

			μ (s)			σ (s)
Vgs (V)	Cl (F)	τ (s)	μ (MC)	μ (Model)	μ (Error)	σ (MC)	σ (Model)	σ (Error)
0.205	4.94 × 10−16	1.79 × 10−11	2.36 × 10−9	2.39 × 10−9	1.53%	1.90 × 10−9	1.88 × 10−9	1.40%
0.231	8.50 × 10−17	3.17 × 10−11	5.65 × 10−10	5.94 × 10−10	5.21%	4.37 × 10−10	4.59 × 10−10	5.21%
0.299	6.53 × 10−16	6.11 × 10−11	3.28 × 10−10	3.20 × 10−10	2.21%	2.17 × 10−10	2.36 × 10−10	8.51%
0.203	2.17 × 10−16	6.40 × 10−12	1.55 × 10−9	1.58 × 10−9	1.80%	1.24 × 10−9	1.24 × 10−9	0.54%
0.229	5.02 × 10−16	1.90 × 10−12	1.33 × 10−9	1.37 × 10−9	3.29%	1.06 × 10−9	1.08 × 10−9	1.93%
0.202	5.10 × 10−17	6.55 × 10−11	1.02 × 10−9	1.05 × 10−9	2.94%	7.98 × 10−10	8.17 × 10−10	2.42%
0.197	3.31 × 10−16	1.02 × 10−10	2.29 × 10−9	2.27 × 10−9	0.80%	1.78 × 10−9	1.77 × 10−9	0.65%
0.253	6.33 × 10−16	4.65 × 10−10	1.09 × 10−9	1.05 × 10−9	3.85%	6.72 × 10−10	7.12 × 10−10	5.86%
0.221	6.97 × 10−16	5.83 × 10−10	2.28 × 10−9	2.25 × 10−9	1.60%	1.61 × 10−9	1.64 × 10−9	2.13%
0.187	5.25 × 10−16	1.89 × 10−10	3.85 × 10−9	3.81 × 10−9	0.90%	3.03 × 10−9	2.96 × 10−9	2.34%

shows part of the data. It can be seen that the error is acceptable for both the mean and standard deviation.

Additionally, Figure 8a,b shows the prediction results of mean and standard deviation in the case of the slow input condition.

Table 4. Partial validation data under slow input conditions.

			μ (s)			σ (s)
Vgs (V)	Cl (F)	τ (s)	μ (MC)	μ (Model)	μ (Error)	σ (MC)	σ (Model)	σ (Error)
0.245	9.78 × 10−16	8.68 × 10−8	9.32 × 10−9	9.43 × 10−9	1.23%	1.25 × 10−8	1.23 × 10−8	1.62%
0.270	9.39 × 10−16	7.46 × 10−8	6.22 × 10−9	6.36 × 10−9	2.25%	8.80 × 10−9	9.56 × 10−9	8.63%
0.299	1.01 × 10−15	4.00 × 10−8	5.52 × 10−9	5.48 × 10−9	0.73%	4.65 × 10−9	4.61 × 10−9	0.86%
0.293	8.42 × 10−16	4.27 × 10−8	5.11 × 10−9	5.08 × 10−9	0.72%	4.96 × 10−9	5.04 × 10−9	1.75%
0.279	5.68 × 10−16	4.98 × 10−8	3.78 × 10−9	3.62 × 10−9	4.23%	5.75 × 10−8	6.17 × 10−8	7.30%
0.290	2.01 × 10−15	5.00 × 10−8	1.08 × 10−8	1.06 × 10−8	1.85%	6.14 × 10−9	5.96 × 10−9	2.93%
0.261	5.12 × 10−16	3.79 × 10−8	5.24 × 10−9	5.15 × 10−9	1.61%	5.18 × 10−9	5.03 × 10−9	2.98%
0.223	5.30 × 10−16	2.47 × 10−8	7.57 × 10−9	7.49 × 10−9	1.04%	4.06 × 10−9	3.83 × 10−9	5.84%
0.24	6.81 × 10−16	3.45 × 10−8	8.28 × 10−9	8.04 × 10−9	2.95%	5.28 × 10−9	4.97 × 10−9	5.83%
0.287	7.00 × 10−16	4.06 × 10−8	4.73 × 10−9	4.67 × 10−9	1.31%	4.89 × 10−9	4.89 × 10−9	0.06%

shows the comparison of the partial prediction data and the MC simulation results, as well as related errors under slow input conditions.

4.2.2. Verification in Different Temperatures

All the above verification was performed at a temperature of 25 °C, though the formula we propose is also very accurate at other temperatures. When the temperature changes, we only need to reperform a DC simulation on the MOS transistor to obtain the coefficients, as well as a MC simulation to obtain ${\sigma }^2\left(Vthn\right)$ for different temperatures, and then update them.

Table 5. Coefficients at different temperatures for NMOS.

T (°C)	Vth (V)	λ	I0 (A)	m (mV/dec)	${\mathit{V}}_{\mathit{T}} \left(\mathbf{V}\right)$
−40	0.364	0.072	7.82 × 10−7	1.410	0.0200
0	0.340	0.072	7.82 × 10−7	1.435	0.0235
50	0.308	0.076	7.42 × 10−7	1.487	0.0278
100	0.273	0.088	6.87 × 10−7	1.567	0.0322
125	0.254	0.098	6.62 × 10−7	1.617	0.0343

lists the coefficients at different temperatures for NMOS. Finally, by substituting the coefficients in the expressions, we can obtain the results under different inputs.

In order to further verify the feasibility of our proposed model, we carried out corresponding experiments at different temperatures. Table 4 shows that the threshold voltage is 0.254 V at 125 °C, and this paper studies the delay model in the sub-threshold region, so the voltage selection in Figure 9 is lower than 0.25 V. It is obvious that the model results and the results of the SPICE MC simulation are highly matched.

Table 6. Average errors at different temperatures.

T (°C)	−40	0	50	100	125
μ (error)	0.75%	1.83%	2.30%	2.98%	3.18%
σ (error)	1.67%	3.12%	3.15%	4.24%	4.21%

lists the average errors at different temperatures, all within the acceptable range.

4.2.3. Verification for Different Transistor Sizes

In the verification above, the length of the transistor we choose was 20 nm. In fact, our model is suitable for different sizes. We also selected for sizes to verify their accuracy. Details of the four sizes are shown in

Table 7. Coefficients for NMOS in the case of different sizes.

Size	W (nm)	L (nm)	Vth (V)	λ	I0 (A)	m (mV/dec)	${\mathit{V}}_{\mathit{T}} \left(\mathbf{V}\right)$
Size 1	80	30	0.340	0.042	6.58 × 10−7	1.285	0.0257
Size 2	100	40	0.347	0.030	6.98 × 10−7	1.218	0.0257
Size 3	135	50	0.352	0.024	8.10 × 10−7	1.185	0.0257
Size 4	150	60	0.356	0.019	7.86 × 10−7	1.165	0.0257

.

The current data and related errors of each size are shown in Appendix A. More details please see

Table A1. Coefficients for NMOS in the case of different sizes.

Size	W (nm)	L (nm)	Vth (V)	λ	I0 (A)	m (mV/dec)	${\mathit{V}}_{\mathit{T}} \left(\mathbf{V}\right)$
Size 1	80	30	0.340	0.042	6.58 × 10−7	1.285	0.0257
Size 2	100	40	0.347	0.030	6.98 × 10−7	1.218	0.0257
Size 3	135	50	0.352	0.024	8.10 × 10−7	1.185	0.0257
Size 4	150	60	0.356	0.019	7.86 × 10−7	1.165	0.0257

,

Table A2. Size 1: Current data compared with simulation results.

	Current (A)				Current (A)
Sweep Vgs (V)	DC	Formula	Error	Sweep Vds (V)	DC	Formula	Error
0.10	6.648585 × 10−10	6.793776 × 10−10	2.18%	0.10	2.195759 × 10−7	2.195075 × 10−7	0.03%
0.11	9.053548 × 10−10	9.197036 × 10−10	1.58%	0.11	2.246291 × 10−7	2.238606 × 10−7	0.34%
0.12	1.232852 × 10−9	1.245044 × 10−9	0.99%	0.12	2.290826 × 10−7	2.278023 × 10−7	0.56%
0.13	1.678799 × 10−9	1.685471 × 10−9	0.40%	0.13	2.330990 × 10−7	2.314740 × 10−7	0.70%
0.14	2.285979 × 10−9	2.281697 × 10−9	0.19%	0.14	2.367952 × 10−7	2.349730 × 10−7	0.77%
0.15	3.112571 × 10−9	3.088834 × 10−9	0.76%	0.15	2.402559 × 10−7	2.383661 × 10−7	0.79%
0.16	4.237630 × 10−9	4.181492 × 10−9	1.32%	0.16	2.435429 × 10−7	2.416996 × 10−7	0.76%
0.17	5.768473 × 10−9	5.660671 × 10−9	1.87%	0.17	2.467016 × 10−7	2.450051 × 10−7	0.69%
0.18	7.850596 × 10−9	7.663102 × 10−9	2.39%	0.18	2.497656 × 10−7	2.483048 × 10−7	0.58%
0.19	1.068089 × 10−8	1.037388 × 10−8	2.87%	0.19	2.527602 × 10−7	2.516139 × 10−7	0.45%
0.20	1.452518 × 10−8	1.404358 × 10−8	3.32%	0.20	2.557046 × 10−7	2.549430 × 10−7	0.30%
0.21	1.974115 × 10−8	1.901142 × 10−8	3.70%	0.21	2.586135 × 10−7	2.582996 × 10−7	0.12%
0.22	2.680801 × 10−8	2.573661 × 10−8	4.00%	0.22	2.614981 × 10−7	2.616892 × 10−7	0.07%
0.23	3.636410 × 10−8	3.484079 × 10−8	4.19%	0.23	2.643674 × 10−7	2.651154 × 10−7	0.28%
0.24	4.925328 × 10−8	4.716552 × 10−8	4.24%	0.24	2.672284 × 10−7	2.685812 × 10−7	0.51%
0.25	6.658004 × 10−8	6.385006 × 10−8	4.10%	0.25	2.700866 × 10−7	2.720886 × 10−7	0.74%
0.26	8.977187 × 10−8	8.643666 × 10−8	3.72%	0.26	2.729465 × 10−7	2.756392 × 10−7	0.99%
0.27	1.206443 × 10−7	1.170131 × 10−7	3.01%	0.27	2.758119 × 10−7	2.792345 × 10−7	1.24%
0.28	1.614615 × 10−7	1.584059 × 10−7	1.89%	0.28	2.786857 × 10−7	2.828756 × 10−7	1.50%
0.29	2.149806 × 10−7	2.144411 × 10−7	0.25%	0.29	2.815705 × 10−7	2.865632 × 10−7	1.77%
0.30	2.844683 × 10−7	2.902984 × 10−7	2.05%	0.30	2.844683 × 10−7	2.902984 × 10−7	2.05%

,

Table A3. Size 2: Current data compared with simulation results.

	Current (A)				Current (A)
Sweep Vgs	DC	Formula	Error	Sweep Vds	DC	Formula	Error
0.10	3.447808 × 10−10	3.505929 × 10−10	1.69%	0.10	1.693521 × 10−7	1.685674 × 10−7	0.46%
0.11	4.766647 × 10−10	4.825496 × 10−10	1.23%	0.11	1.724931 × 10−7	1.713454 × 10−7	0.67%
0.12	6.590156 × 10−10	6.641723 × 10−10	0.78%	0.12	1.751957 × 10−7	1.737894 × 10−7	0.80%
0.13	9.111418 × 10−10	9.141543 × 10−10	0.33%	0.13	1.775811 × 10−7	1.760102 × 10−7	0.88%
0.14	1.259729 × 10−9	1.258225 × 10−9	0.12%	0.14	1.797351 × 10−7	1.780836 × 10−7	0.92%
0.15	1.741646 × 10−9	1.731797 × 10−9	0.57%	0.15	1.817190 × 10−7	1.800616 × 10−7	0.91%
0.16	2.407814 × 10−9	2.383613 × 10−9	1.01%	0.16	1.835767 × 10−7	1.819797 × 10−7	0.87%
0.17	3.328513 × 10−9	3.280761 × 10−9	1.43%	0.17	1.853401 × 10−7	1.838624 × 10−7	0.80%
0.18	4.600657 × 10−9	4.515578 × 10−9	1.85%	0.18	1.870328 × 10−7	1.857262 × 10−7	0.70%
0.19	6.357736 × 10−9	6.215158 × 10−9	2.24%	0.19	1.886720 × 10−7	1.875829 × 10−7	0.58%
0.20	8.783299 × 10−9	8.554427 × 10−9	2.61%	0.20	1.902708 × 10−7	1.894402 × 10−7	0.44%
0.21	1.212916 × 10−8	1.177415 × 10−8	2.93%	0.21	1.918392 × 10−7	1.913037 × 10−7	0.28%
0.22	1.673970 × 10−8	1.620573 × 10−8	3.19%	0.22	1.933846 × 10−7	1.931772 × 10−7	0.11%
0.23	2.308387 × 10−8	2.230526 × 10−8	3.37%	0.23	1.949129 × 10−7	1.950633 × 10−7	0.08%
0.24	3.179661 × 10−8	3.070054 × 10−8	3.45%	0.24	1.964288 × 10−7	1.969639 × 10−7	0.27%
0.25	4.373098 × 10−8	4.225565 × 10−8	3.37%	0.25	1.979359 × 10−7	1.988803 × 10−7	0.48%
0.26	6.002143 × 10−8	5.815989 × 10−8	3.10%	0.26	1.994370 × 10−7	2.008136 × 10−7	0.69%
0.27	8.215675 × 10−8	8.005019 × 10−8	2.56%	0.27	2.009346 × 10−7	2.027644 × 10−7	0.91%
0.28	1.120578 × 10−7	1.101796 × 10−7	1.68%	0.28	2.024305 × 10−7	2.047333 × 10−7	1.14%
0.29	1.521509 × 10−7	1.516491 × 10−7	0.33%	0.29	2.039263 × 10−7	2.067207 × 10−7	1.37%
0.30	2.054233 × 10−7	2.087270 × 10−7	1.61%	0.30	2.054233 × 10−7	2.087270 × 10−7	1.61%

,

Table A4. Size 3: Current data compared with simulation results.

	Current (A)				Current (A)
Sweep Vgs	DC	Formula	Error	Sweep Vds	DC	Formula	Error
0.10	2.600795 × 10−10	2.637755 × 10−10	1.42%	0.10	1.589399 × 10−7	1.578282 × 10−7	0.70%
0.11	3.625443 × 10−10	3.663475 × 10−10	1.05%	0.11	1.614898 × 10−7	1.601232 × 10−7	0.85%
0.12	5.053995 × 10−10	5.088057 × 10−10	0.67%	0.12	1.636417 × 10−7	1.620975 × 10−7	0.94%
0.13	7.045667 × 10−10	7.066603 × 10−10	0.30%	0.13	1.655069 × 10−7	1.638558 × 10−7	1.00%
0.14	9.822389 × 10−10	9.814528 × 10−10	0.08%	0.14	1.671636 × 10−7	1.654699 × 10−7	1.01%
0.15	1.369344 × 10−9	1.363101 × 10−9	0.46%	0.15	1.686669 × 10−7	1.669887 × 10−7	0.99%
0.16	1.908969 × 10−9	1.893158 × 10−9	0.83%	0.16	1.700564 × 10−7	1.684457 × 10−7	0.95%
0.17	2.661110 × 10−9	2.629334 × 10−9	1.19%	0.17	1.713604 × 10−7	1.698638 × 10−7	0.87%
0.18	3.709259 × 10−9	3.651778 × 10−9	1.55%	0.18	1.725996 × 10−7	1.712585 × 10−7	0.78%
0.19	5.169487 × 10−9	5.071812 × 10−9	1.89%	0.19	1.737895 × 10−7	1.726406 × 10−7	0.66%
0.20	7.202954 × 10−9	7.044042 × 10−9	2.21%	0.20	1.749414 × 10−7	1.740175 × 10−7	0.53%
0.21	1.003300 × 10−8	9.783194 × 10−9	2.49%	0.21	1.760639 × 10−7	1.753942 × 10−7	0.38%
0.22	1.396839 × 10−8	1.358750 × 10−8	2.73%	0.22	1.771637 × 10−7	1.767741 × 10−7	0.22%
0.23	1.943441 × 10−8	1.887114 × 10−8	2.90%	0.23	1.782457 × 10−7	1.781596 × 10−7	0.05%
0.24	2.701415 × 10−8	2.620939 × 10−8	2.98%	0.24	1.793139 × 10−7	1.795525 × 10−7	0.13%
0.25	3.750178 × 10−8	3.640120 × 10−8	2.93%	0.25	1.803715 × 10−7	1.809538 × 10−7	0.32%
0.26	5.196958 × 10−8	5.055620 × 10−8	2.72%	0.26	1.814209 × 10−7	1.823643 × 10−7	0.52%
0.27	7.184863 × 10−8	7.021553 × 10−8	2.27%	0.27	1.824642 × 10−7	1.837847 × 10−7	0.72%
0.28	9.902015 × 10−8	9.751960 × 10−8	1.52%	0.28	1.835028 × 10−7	1.852154 × 10−7	0.93%
0.29	1.359099 × 10−7	1.354412 × 10−7	0.34%	0.29	1.845383 × 10−7	1.866568 × 10−7	1.15%
0.30	1.855716 × 10−7	1.881089 × 10−7	1.37%	0.30	1.855716 × 10−7	1.881089 × 10−7	1.37%

and

Table A5. Size 4: Current data compared with simulation results.

	Current (A)				Current (A)
Sweep Vgs	DC	Formula	Error	Sweep Vds	DC	Formula	Error
0.10	1.840426 × 10−10	1.862541 × 10−10	1.20%	0.10	1.291076 × 10−7	1.279476 × 10−7	0.90%
0.11	2.578295 × 10−10	2.601388 × 10−10	0.90%	0.11	1.309655 × 10−7	1.296413 × 10−7	1.01%
0.12	3.612193 × 10−10	3.633325 × 10−10	0.59%	0.12	1.325076 × 10−7	1.310711 × 10−7	1.08%
0.13	5.060898 × 10−10	5.074618 × 10−10	0.27%	0.13	1.338230 × 10−7	1.323226 × 10−7	1.12%
0.14	7.090832 × 10−10	7.087654 × 10−10	0.04%	0.14	1.349737 × 10−7	1.334544 × 10−7	1.13%
0.15	9.935122 × 10−10	9.899235 × 10−10	0.36%	0.15	1.360035 × 10−7	1.345063 × 10−7	1.10%
0.16	1.392026 × 10−9	1.382613 × 10−9	0.68%	0.16	1.369433 × 10−7	1.355055 × 10−7	1.05%
0.17	1.950334 × 10−9	1.931078 × 10−9	0.99%	0.17	1.378154 × 10−7	1.364707 × 10−7	0.98%
0.18	2.732393 × 10−9	2.697113 × 10−9	1.29%	0.18	1.386360 × 10−7	1.374144 × 10−7	0.88%
0.19	3.827632 × 10−9	3.767022 × 10−9	1.58%	0.19	1.394172 × 10−7	1.383454 × 10−7	0.77%
0.20	5.360954 × 10−9	5.261352 × 10−9	1.86%	0.20	1.401677 × 10−7	1.392696 × 10−7	0.64%
0.21	7.506557 × 10−9	7.348462 × 10−9	2.11%	0.21	1.408941 × 10−7	1.401910 × 10−7	0.50%
0.22	1.050688 × 10−8	1.026350 × 10−8	2.32%	0.22	1.416017 × 10−7	1.411124 × 10−7	0.35%
0.23	1.469834 × 10−8	1.433490 × 10−8	2.47%	0.23	1.422943 × 10−7	1.420357 × 10−7	0.18%
0.24	2.054593 × 10−8	2.002137 × 10−8	2.55%	0.24	1.429750 × 10−7	1.429622 × 10−7	0.01%
0.25	2.868881 × 10−8	2.796360 × 10−8	2.53%	0.25	1.436461 × 10−7	1.438928 × 10−7	0.17%
0.26	3.999898 × 10−8	3.905640 × 10−8	2.36%	0.26	1.443096 × 10−7	1.448281 × 10−7	0.36%
0.27	5.565421 × 10−8	5.454957 × 10−8	1.98%	0.27	1.449670 × 10−7	1.457686 × 10−7	0.55%
0.28	7.722428 × 10−8	7.618868 × 10−8	1.34%	0.28	1.456195 × 10−7	1.467146 × 10−7	0.75%
0.29	1.067656 × 10−7	1.064118 × 10−7	0.33%	0.29	1.462681 × 10−7	1.476663 × 10−7	0.96%
0.30	1.469137 × 10−7	1.486239 × 10−7	1.16%	0.30	1.469137 × 10−7	1.486239 × 10−7	1.16%

. Additionally, Figure 10 shows the delay results compared with MC simulation results under different operating voltages.

Moreover, we tested a significant amount of data for each size, and

Table 8. Size 1: Partial validation data (T = 25 °C).

			μ (s)			σ (s)
Vgs (V)	Cl (F)	τ (s)	μ (MC)	μ (Model)	μ (Error)	σ (MC)	σ (Model)	σ (Error)
0.238	4.81 × 10−16	4.45 × 10−10	3.650440 × 10−9	3.676056 × 10−9	0.70%	2.551130 × 10−9	2.587672 × 10−9	1.43%
0.243	2.38 × 10−16	4.39 × 10−10	2.340220 × 10−9	2.334835 × 10−9	0.23%	1.588780 × 10−9	1.606478 × 10−9	1.11%
0.289	5.40 × 10−16	1.70 × 10−10	9.945210 × 10−10	9.927272 × 10−10	0.18%	6.561770 × 10−10	6.832115 × 10−10	4.12%
0.209	5.14 × 10−16	2.39 × 10−10	8.066620 × 10−9	8.056563 × 10−9	0.12%	5.891210 × 10−9	5.845090 × 10−9	0.78%
0.273	3.26 × 10−16	4.43 × 10−10	1.261890 × 10−9	1.257850 × 10−9	0.32%	7.702130 × 10−10	8.108863 × 10−10	5.28%
0.298	7.45 × 10−16	3.18 × 10−10	1.026480 × 10−9	1.004063 × 10−9	2.18%	6.163550 × 10−10	6.529836 × 10−10	5.94%
0.266	5.83 × 10−16	4.71 × 10−10	1.989130 × 10−9	2.004680 × 10−9	0.78%	1.299260 × 10−9	1.351936 × 10−9	4.05%
0.293	1.10 × 10−16	1.89 × 10−11	4.622390 × 10−10	4.425993 × 10−10	4.25%	3.147220 × 10−10	3.190541 × 10−10	1.38%
0.292	1.24 × 10−16	8.46 × 10−11	4.889020 × 10−10	4.911607 × 10−10	0.46%	3.284180 × 10−10	3.378408 × 10−10	2.87%
0.248	7.04 × 10−16	1.52 × 10−10	3.398730 × 10−9	3.459904 × 10−9	1.80%	2.432340 × 10−9	2.496145 × 10−9	2.62%

,

Table 9. Size 2: Partial validation data (T = 25 °C).

			μ (s)			σ (s)
Vgs (V)	Cl (F)	τ (s)	μ (MC)	μ (Model)	μ (Error)	σ (MC)	σ (Model)	σ (Error)
0.29	8.600 × 10−17	3.390 × 10−10	8.099090 × 10−10	7.998129 × 10−10	1.25%	3.882130 × 10−10	4.194068 × 10−10	8.04%
0.261	6.230 × 10−16	4.090 × 10−11	3.213440 × 10−9	3.233015 × 10−9	0.61%	1.961680 × 10−9	1.994106 × 10−9	1.65%
0.234	5.980 × 10−16	4.787 × 10−10	6.902490 × 10−9	6.962671 × 10−9	0.87%	4.153020 × 10−9	4.215779 × 10−9	1.51%
0.282	3.510 × 10−16	9.800 × 10−12	1.327440 × 10−9	1.300852 × 10−9	2.00%	7.941080 × 10−10	8.037207 × 10−10	1.21%
0.249	5.290 × 10−16	2.362 × 10−10	4.191040 × 10−9	4.217566 × 10−9	0.63%	2.521270 × 10−9	2.563139 × 10−9	1.66%
0.274	4.890 × 10−16	4.695 × 10−10	2.089330 × 10−9	2.094021 × 10−9	0.22%	1.159100 × 10−9	1.194233 × 10−9	3.03%
0.271	2.160 × 10−16	3.918 × 10−10	1.613750 × 10−9	1.613682 × 10−9	0.00%	8.894820 × 10−10	9.140999 × 10−10	2.77%
0.223	5.730 × 10−16	3.074 × 10−10	9.105560 × 10−9	9.160867 × 10−9	0.61%	5.574670 × 10−9	5.614147 × 10−9	0.71%
0.281	4.710 × 10−16	2.773 × 10−10	1.659610 × 10−9	1.641169 × 10−9	1.11%	9.290240 × 10−10	9.552446 × 10−10	2.82%
0.232	4.840 × 10−16	2.979 × 10−10	6.470420 × 10−9	6.498238 × 10−9	0.43%	3.939820 × 10−9	3.965225 × 10−9	0.64%

,

Table 10. Size3: Partial validation data (T = 25 °C).

			μ (s)			σ (s)
Vgs (V)	Cl (F)	τ (s)	μ (MC)	μ (Model)	μ (Error)	σ (MC)	σ (Model)	σ (Error)
0.214	2.71 × 10−16	1.67 × 10−10	1.016530 × 10−8	1.014256 × 10−8	0.22%	5.286070 × 10−9	5.198566 × 10−9	1.66%
0.244	4.19 × 10−16	2.71 × 10−10	5.089810 × 10−9	5.099005 × 10−9	0.18%	2.580310 × 10−9	2.578634 × 10−9	0.06%
0.278	5.62 × 10−16	3.14 × 10−10	2.261600 × 10−9	2.222832 × 10−9	1.71%	1.069950 × 10−9	1.085720 × 10−9	1.47%
0.28	7.01 × 10−16	1.25 × 10−10	2.332220 × 10−9	2.284576 × 10−9	2.04%	1.137260 × 10−9	1.153580 × 10−9	1.43%
0.262	7.68 × 10−16	6.21 × 10−11	4.060420 × 10−9	4.054113 × 10−9	0.16%	2.084980 × 10−9	2.077758 × 10−9	0.35%
0.232	6.82 × 10−16	2.94 × 10−10	9.182170 × 10−9	9.185360 × 10−9	0.03%	4.690660 × 10−9	4.681673 × 10−9	0.19%
0.256	9.89 × 10−16	2.12 × 10−10	5.728750 × 10−9	5.712757 × 10−9	0.28%	2.879840 × 10−9	2.905023 × 10−9	0.87%
0.267	6.46 × 10−16	4.15 × 10−10	3.328950 × 10−9	3.299695 × 10−9	0.88%	1.598810 × 10−9	1.622513 × 10−9	1.48%
0.271	2.16 × 10−16	3.92 × 10−10	1.902670 × 10−9	1.912940 × 10−9	0.54%	8.971570 × 10−10	9.117871 × 10−10	1.63%
0.252	1.97 × 10−16	3.04 × 10−10	3.124600 × 10−9	3.133580 × 10−9	0.29%	1.555950 × 10−9	1.559070 × 10−9	0.20%

and

Table 11. Size4: Partial validation data (T = 25 °C).

			μ (s)			σ (s)
Vgs (V)	Cl (F)	τ (s)	μ (MC)	μ (Model)	μ (Error)	σ (MC)	σ (Model)	σ (Error)
0.294	6.71 × 10−16	1.49 × 10−10	2.054960 × 10−9	1.983820 × 10−9	3.46%	9.274530 × 10−10	9.209276 × 10−10	0.70%
0.276	9.05 × 10−16	2.18 × 10−10	4.056030 × 10−9	4.028091 × 10−9	0.69%	1.882430 × 10−9	1.885995 × 10−9	0.19%
0.236	7.28 × 10−16	2.54 × 10−10	1.155630 × 10−8	1.163491 × 10−8	0.68%	5.442750 × 10−9	5.516690 × 10−9	1.36%
0.206	1.82 × 10−16	7.06 × 10−11	1.661170 × 10−8	1.636127 × 10−8	1.51%	7.951180 × 10−9	7.806130 × 10−9	1.82%
0.259	3.63 × 10−16	7.78 × 10−11	4.246820 × 10−9	4.232936 × 10−9	0.33%	1.996720 × 10−9	2.008986 × 10−9	0.61%
0.228	2.10 × 10−16	2.51 × 10−10	9.044010 × 10−9	8.975501 × 10−9	0.76%	4.288210 × 10−9	4.247207 × 10−9	0.96%
0.237	3.64 × 10−16	3.49 × 10−10	8.247390 × 10−9	8.240120 × 10−9	0.09%	3.871480 × 10−9	3.878882 × 10−9	0.19%
0.285	4.47 × 10−16	2.89 × 10−10	2.243840 × 10−9	2.193539 × 10−9	2.24%	9.737410 × 10−10	9.963785 × 10−10	2.32%
0.216	5.37 × 10−16	3.79 × 10−10	1.786640 × 10−8	1.793034 × 10−8	0.36%	8.495440 × 10−9	8.506323 × 10−9	0.13%
0.26	8.36 × 10−16	1.87 × 10−10	6.156130 × 10−9	6.168514 × 10−9	0.20%	2.832280 × 10−9	2.914898 × 10−9	2.92%

show the partial data and corresponding errors. The average error of each size is less than 5%.

4.2.4. Verification of Different Gates

The above results were verified with an inverter and achieved a high degree of accuracy. In fact, the model derived in this article is also applicable to other cell circuits. Here, we select the NAND2 gate ($\frac{W_n}{L_n}=80 \mathrm{nm}/20 \mathrm{nm}; \frac{W_P}{L_P}=110 \mathrm{nm}/20 \mathrm{nm}$) and NOR2 gate ($\frac{W_n}{L_n}=80 \mathrm{nm}/20 \mathrm{nm}; \frac{W_P}{L_P}=310\mathrm{nm}/20\mathrm{nm}$). Similarly, we first operate a DC for each transistor and the coefficients are shown in

Table 12. Coefficients from DC (T = 25 °C).

Gate	Transistor	Vth (V)	λ	I0 (A)	m (mV/dec)	${\mathit{V}}_{\mathit{T}} \left(\mathbf{V}\right)$
NAND2	NMOS	0.324	0.073	7.66 × 10−7	1.462	0.0257
	PMOS	−0.325	0.089	3.49 × 10−7	1.451	0.0257
NOR2	NMOS	0.324	0.073	7.66 × 10−7	1.462	0.0257
	PMOS	−0.325	0.094	9.90 × 10−7	1.517	0.0257

. Then, we verify the delay at different operating voltages, and Figure 11a,b shows the prediction results of the mean and standard deviation, respectively.

From Figure 11, we can clearly see that the delay prediction results for each gate are very close to the MC simulation results. Additionally, the corresponding errors for each gate are shown in

Table 13. Average errors of NAND2 and NOR2 gates.

Gate	µ (Error)	σ (Error)
NAND2	2.73%	1.59%
NOR2	2.29%	2.08%

.

4.2.5. Verification Considering the Body Effect

In the above validation, we set $Vbs=0$. In fact, the effect of the body effect on propagation delay is also modeled in this paper. It mainly affects the threshold voltage, and in Equation (7), $Vthb$ is the increase in the threshold voltage caused by the body effect.

Considering $Vbs$, we verify the delay for an inverter in the case of $\left|Vbs\right|>0$, and

Table 14. Coefficients at different $\left|Vbs\right|$ for NMOS (T = 25 °C).

|Vbs| (V)	Vth (V)	λ	I0 (A)	m (mV/dec)	$${\mathit{V}}_{\mathit{T}} \left(\mathbf{V}\right)$$
0.05	0.327	0.073	7.72 × 10−7	1.453	0.0257
0.10	0.330	0.073	7.78 × 10−7	1.449	0.0257
0.15	0.333	0.074	7.84 × 10−7	1.444	0.0257

shows the coefficients obtained by DC simulations for NMOS.

Additionally, the Figure 12a,b show the prediction results of the propagation delay compared with MC simulations under different voltages, and the error of the mean and standard deviation is about 1.4% and 3.2%, respectively.

4.2.6. Verification under Different Technologies

The above results were verified under 22 nm technology and achieved a high degree of accuracy. To further prove the universality of our model, we also validated it under another two technologies: 28 nm CMOS and 40 nm CMOS technologies. For an inverter, the size we selected is as follows: $\frac{W_n}{L_n}=100 \mathrm{nm}/30 \mathrm{nm}, \frac{W_P}{L_P}=200 \mathrm{nm}/30 \mathrm{nm}$ for 28 nm technology, and $\frac{W_n}{L_n}=120 \mathrm{nm}/40 \mathrm{nm}, \frac{W_P}{L_P}=240 \mathrm{nm}/40 \mathrm{nm}$ for 40 nm technology. The verification process is the same as that in the 22 nm technology.

The

Table 15. Coefficients under different technologies for NMOS.

Technology	Vth (V)	λ	I0 (A)	m (mV/dec)	${\mathit{V}}_{\mathit{T}} \left(\mathbf{V}\right)$
28 nm	0.374	0.149	5.98 × 10−7	1.665	0.0257
40 nm	0.597	0.121	1.32 × 10−6	1.472	0.0257

displays the corresponding parameters for each technology.

Additionally, for multi-inputs, we predicted the propagation delay and the standard deviation for each technology; all the average errors are less than 4%. Additionally,

Table 16. Partial data under 28 nm technology (T = 25 °C, Vbs = 0).

			μ (s)			σ (s)
Vgs (V)	Cl (F)	τ (s)	μ (MC)	μ (Model)	μ (Error)	σ (MC)	σ (Model)	σ (Error)
0.278	9.00 × 10−17	1.71 × 10−10	6.944630 × 10−10	6.838224 × 10−10	1.53%	7.639800 × 10−10	7.839069 × 10−10	2.61%
0.268	2.96 × 10−16	1.40 × 10−10	1.284680 × 10−9	1.290465 × 10−9	0.45%	1.553410 × 10−9	1.535944 × 10−9	1.12%
0.259	3.84 × 10−16	1.87 × 10−10	1.804810 × 10−9	1.814650 × 10−9	0.55%	2.250080 × 10−9	2.164636 × 10−9	3.80%
0.291	2.43 × 10−16	5.34 × 10−11	6.980870 × 10−10	6.957877 × 10−10	0.33%	7.894610 × 10−10	8.330983 × 10−10	5.53%
0.267	1.57 × 10−16	2.32 × 10−10	1.039950 × 10−9	1.025904 × 10−9	1.35%	1.197940 × 10−9	1.186417 × 10−9	0.96%
0.219	4.27 × 10−16	4.36 × 10−10	4.820740 × 10−9	4.777483 × 10−9	0.90%	6.705030 × 10−9	6.754427 × 10−9	0.74%
0.222	5.09 × 10−16	2.55 × 10−10	4.944960 × 10−9	4.977635 × 10−9	0.66%	6.937650 × 10−9	7.081979 × 10−9	2.08%
0.214	3.01 × 10−16	1.47 × 10−10	4.370640 × 10−9	4.309342 × 10−9	1.40%	6.254060 × 10−9	6.151486 × 10−9	1.64%
0.209	7.12 × 10−16	2.46 × 10−10	8.417960 × 10−9	8.246344 × 10−9	2.04%	1.224990 × 10−8	1.178208 × 10−8	3.82%
0.206	8.52 × 10−16	1.59 × 10−10	1.030070 × 10−8	1.001988 × 10−8	2.73%	1.516540 × 10−8	1.434644 × 10−8	5.40%

and

Table 17. Partial data under 28 nm technology (T = 25 °C, Vbs = 0).

			μ (s)			σ (s)
Vgs (V)	Cl (F)	τ (s)	μ (MC)	μ (Model)	μ (Error)	σ (MC)	σ (Model)	σ (Error)
0.292	9.92 × 10−16	2.14 × 10−10	7.646140 × 10−7	7.651751 × 10−7	0.07%	1.805700 × 10−6	1.796862 × 10−6	0.49%
0.263	7.97 × 10−16	2.48 × 10−10	1.357800 × 10−6	1.365124 × 10−6	0.54%	3.193240 × 10−6	3.205779 × 10−6	0.39%
0.274	3.32 × 10−16	4.08 × 10−11	6.337930 × 10−7	6.328385 × 10−7	0.15%	1.490450 × 10−6	1.486129 × 10−6	0.29%
0.256	4.94 × 10−16	3.78 × 10−10	1.209320 × 10−6	1.213141 × 10−6	0.32%	2.839030 × 10−6	2.848861 × 10−6	0.35%
0.27	4.46 × 10−16	7.50 × 10−12	8.085170 × 10−7	8.090342 × 10−7	0.06%	1.901590 × 10−6	1.899907 × 10−6	0.09%
0.298	7.93 × 10−16	4.56 × 10−11	5.643700 × 10−7	5.629425 × 10−7	0.25%	1.333000 × 10−6	1.321983 × 10−6	0.83%
0.28	8.43 × 10−16	3.75 × 10−10	9.226660 × 10−7	9.252843 × 10−7	0.28%	2.174680 × 10−6	2.172834 × 10−6	0.08%
0.256	1.22 × 10−16	1.30 × 10−10	7.046400 × 10−7	7.069365 × 10−7	0.33%	1.640960 × 10−6	1.660133 × 10−6	1.17%
0.297	1.49 × 10−16	4.05 × 10−10	2.673090 × 10−7	2.651178 × 10−7	0.82%	6.295670 × 10−7	6.224933 × 10−7	1.12%
0.278	5.20 × 10−16	2.60 × 10−10	7.199620 × 10−7	7.197352 × 10−7	0.03%	1.695590 × 10−6	1.690154 × 10−6	0.32%

show the partial data compared to the MC results.

4.2.7. Comparison with Other Studies

The propagation delay model proposed in this paper has a high accuracy under the 22 nm FDSOI process, and we compared the other two models [4,18] under the same process. Model [4] provided a very complete model that took temperature into account, but it ignored the influence of DIBL effect, which may make the results inaccurate under different technologies. The model [18] did not simplify Kirchhoff’s law, so the Laplace transform and some complex calculations were used in the calculation. Additionally, models [4,18] did not further derive the variance of the delay. The results of the comparison with them are shown in

Table 18. Propagation delay at different voltages (T = 25 °C, Cl = 0.5 fF, τ = 1 × 10⁻¹¹ s, Vbs = 0).

Vgs (V)	MC	Model [4] (s)	Error	Model [18] (s)	Error	Model (s)	Error
0.20	2.68 × 10−9	1.12 × 10−9	48.18%	2.72 × 10−9	1.48%	2.66 × 10−9	0.85%
0.21	2.10 × 10−9	9.46 × 10−10	44.08%	2.15 × 10−9	2.45%	2.11 × 10−9	0.09%
0.22	1.65 × 10−9	7.93 × 10−10	39.95%	1.70 × 10−9	3.23%	1.67 × 10−9	0.85%
0.23	1.30 × 10−9	6.62 × 10−10	35.74%	1.35 × 10−9	3.81%	1.31 × 10−9	1.41%
0.24	1.02 × 10−9	5.50 × 10−10	31.48%	1.06 × 10−9	4.16%	1.04 × 10−9	1.75%
0.25	7.99 × 10−10	4.55 × 10−10	26.93%	8.34 × 10−10	4.40%	8.15 × 10−10	1.97%
0.26	6.29 × 10−10	3.75 × 10−10	22.27%	6.56 × 10−10	4.31%	6.40 × 10−10	1.88%
0.27	4.96 × 10−10	3.08 × 10−10	17.77%	5.15 × 10−10	3.72%	5.03 × 10−10	1.29%
0.28	3.93 × 10−10	2.52 × 10−10	13.36%	4.04 × 10−10	2.69%	3.94 × 10−10	0.27%
0.29	3.13 × 10−10	2.05 × 10−10	9.08%	3.16 × 10−10	1.14%	3.09 × 10−10	1.25%
0.30	2.50 × 10−10	1.66 × 10−10	5.01%	2.48 × 10−10	0.90%	2.42 × 10−10	3.26%

.

It is clear that our proposed propagation delay model has a higher accuracy, with the error being only 1.35% in this set of data.

4.3. Delay Distribution Verification

In this section, the delay modeling and inverse Gaussian distribution are combined to predict the distribution characteristics of the delay through analytical expressions, eliminating the need for redundant fitting work. Figure 13 and Figure 14 below are the probability density function and cumulative distribution function of the delay distribution at an operating voltage of 0.25 V, 0.27 V, and 0.3 V in Figure 13a–c respectively, from which we can clearly observe the probability density function curve of the model prediction; the fitting curve and the MC simulation results are close to each other, and the error of the CDF is about 2%.

4.4. Speed of the Model

The following Figure 15 shows the curve of the calculation time with the amount of data. For the acquisition of delays, the time is the same for each set of SPICE MC simulation data. As the amount of data increases, the time required increases linearly. The proposed model only needs to perform a DC simulation at the beginning, ($t_{DC}=1.310 \mathrm{s}$), and then an MC simulation ($t_{MC}=242.624 \mathrm{s}$). Then it calculates the corresponding coefficients ($t_{coefficient}=6.513 \mathrm{s}$), and the delay under different inputs can be predicted through the model calculation, with each set of calculation results lasting 0.386 s ($t_{calculation}$). The specific time consumption of the model is calculated as Equation (25), where n represents the amount of delay data.

$$t_{model}=1·t_{DC}+1·t_{MC}+1·t_{coefficient}+n·t_{calculation}=250.447 s+n·0.386 s$$

(25)

Although an MC simulation is performed during the preparation process to obtain some coefficients, it is only undertaken once, and the coefficients will not be reacquired when the input changes. Therefore, as the amount of data increases, the time required for model calculation grows relatively slower compared to the SPICE MC simulation.

5. Conclusions

In this paper, we propose a distribution curve function that accurately predicts the delay of sub-threshold circuits with a high accuracy. The curve of this function is extremely similar to the delay distribution of the circuit. We then derive the key parameters of this function, namely, the mean and variance of the propagation delay, which are derived from the sub-threshold current formula and input–output waveform curves. The results are in good agreement with the SPICE MC simulation from the 22 nm Industrial Design Suite, where the error of the mean and standard deviation for the inverter are 1.5% and 4.3%, respectively. We also verified it with other cell circuits, such as NOR2 gate and NAND2 gate, with all obtaining good results. The derived model parameters are substituted into the inverse Gaussian distribution function, finding that the result is very close to the distribution of Monte Carlo simulations, with the maximum error of the CDF being approximately 2%. In addition, our model is also applicable to other technologies. We have verified the model using 28 nm CMOS and 40 nm CMOS technologies, and the results match the MC simulation results very well. The proposed method only requires performing a DC simulation, to obtain the coefficient of the NMOS and PMOS transistors, and a MC simulation of the circuit under a certain process; no other simulations are required, which greatly reduces the simulation time.

The prediction method can quickly calculate the statistical parameters of delay for cell circuits in the sub-threshold region, which accelerates the statistical characterization and is very helpful for further evaluating device-level optimization on low-power circuits and architectures. Additionally, based on the study, we will continue to explore the path delay variation of the circuits in the future.