Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

Abstract

The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 µm² chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

1. Introduction

In the last decades, radio frequency identification (RFID) technology has turned out to be a discipline of predominant attention for wireless communication system. RFID technology integrates portable wireless devices in order to detect both the nature and the precise location of physical objects or persons [1,2]. The RIFD reader contributes to transmitting the information and energy into the RFID tag where the tag is responsible for providing feedback to the RFID reader for any kind of inquiry [3]. The fundamental concern of this system is to protect the data privacy of the consumer. With the advancement of modern technology, personal data privacy faces different kinds of threat. The privacy of a consumer can be stolen or scanned without approval or even learning. The medical information of patients can be revealed and anybody can be a victim of clandestine tracking by vendors [4,5]. In response to these issues, a lot of research has been done aimed at the prevention of unauthorized access to RFID tags. To improve the security system in active RFID tags most of them use a shift register for storing a key or data [6,7]. The shift register is integrated into a modulator/demodulator in cryptographic RFID tag. Figure 1 and Figure 2 describe the integration of a shift register in a cryptographic RFID tag precisely. The shift register is used in a modulator/demodulator to shift one bit at the rising edge of the clock in one shift action. The four-bit shift register loads data in it through the four-bit parallel input, and shifts it out through the serial output. Therefore, designing an efficient shift register has become a more demanding goal in current RFID security system.

In order to design an efficient shift register, few crucial performance parameters must be taken into consideration, such as power dissipation, area, delay, and leakage [8,9].

In the sub-threshold region the transistor can work properly at a gate source voltage lower than the threshold voltage of the transistor (V_gs < V_th):

I_leakage α e^{(Vgs − Vt)/Vth} ,

(1)

where V_t is the thermal potential. It is clear from Equation (1) that the leakage current is exponential proportional to the threshold voltage. The problem is that as the device threshold decreases as the leakage current increases, which leads to increasing the static power consumption.

P_static = I_leakage × VDD.

(2)

Equation (2) shows that the static power is directly proportional to the multiple of the leakage current and the voltage source. As the circuit spends more time in the ideal (standby) mode, it is practical to reduce the leakage current to minimize the static power, which represents the dominant part of the total power consumption. Multi-threshold CMOS (MTCMOS) technology is one of the most effective techniques to reduce the leakage current during standby mode. Implementing C-element switch activity and leakage current is reduced in the proposed deign.

One of the important storage elements that is used in the shift register chip is a flip-flop (FF) [10,11]. To design a low power and high-performance shift register, attention must be given in designing high-performance FFs [12]. In the current trend of CMOS technology, low power consumption is considered as the most important factor, especially for handheld applications and portable devices. The clock system power consumption is estimated as the half of the overall system power [13,14,15]. Therefore, the FFs contribute a substantial percentage of the chip area and power consumption in the whole system [16,17]. Pulsed flip-flops (P-FF) and master-slave are the two groups of the flip-flops. In this article, a new pulsed hybrid flip-flop utilizing C-elements is presented. A C-element is the fundamental stage of FF design architectures. Implementing a C-element, the additional switch activity is reduced and data activity is improved compared to other designs. Single-ended conditional capturing energy recovery (SCCER) flip-flop are considered as one of the important designs that implies the pulsed type as shown in Figure 3 [18]. The output feedback which is connected to the transistor N3 is used to achieve the conditional capturing. The speed performance of the design is low due to four transistors which are connected in series to make up the discharging path. Absel et al. [19] have proposed a dual dynamic node flip-flop (DDFF) where two separate dynamic nodes, namely, the driving pull-up and pull-down, are comprised as shown in Figure 4. At the front end stage of the scheme, an unconditional shutoff mechanism is realized. The DDFF has two functions, evaluation and precharge, which totally depend on the state of the CLK. The evaluation phase happens when the CLK is high and the precharge occurs when the CLK is low. The drawback of this design is that it is not comfortable with applications which require low power operation.

2. Methodology

A low-power CMOS shift register has been introduced to meet the current demand for low power and low-cost devices. It is significant to select an accurate library and CMOS process in order to design an application-oriented device. The technology expresses the model parameters associated with the devices that are used in the schematic. It also provides the ground rules to design the layout of the schematic circuit. The proposed D flip-flop and the shift register is designed with Mentor Graphics software (Silterra, Penang, Malaysia) and simulated by an electronic design automation (EDA) tool. All components are integrated and simulated in a 130 nm CMOS process.

2.1. Proposed FF Design

The proposed flip-flop is designed utilizing a C-element consisting of two inputs and one output. However, it has two output modes. When both inputs for the C-elements are similar, the output will be inverted from the inputs. The C-element preserves the prior value when the inputs are not similar [20]. The schematic diagram of the proposed flip-flop is presented in Figure 5. The active front end stage and the static output are implemented in the circuit and, consequently, this design known as hybrid pulsed flip-flop. This design constitutes three parts: (1) a simple C-element made up from four transistors, i.e., M3–6; (2) sampling circuit having five transistors, i.e., transistors M1, M2, M7–9; and (3) a keeper, i.e., M12–16. DB and node X are considered a complementary input data to the C-element.

At first, when the rising edge of the clock arrives and the input data is low, the transistor (M2) comes on and the transistor (M1) will turn on for a short period of time because of the signal of CLKB remains high (transparency window). Thus, the transistors (M1 and M2) are on during this short period of time. When the data transition from ‘1’ to ‘0’ occurs, DB becomes 1 and the M1 and M2 transistors will move from DB to node X. At this moment, X will be precharged to turn on the transistors M5 and M6 and the node Q is pulled down. When CLKB is low, the transparency window shuts down. Meanwhile, if the input data is high or there is an occurrence of transition from ‘0’ to ‘1’, DB turns low. As stated before, transistors M1 and M2 are turned on temporarily when the rising edge of the clock arrives and this will drive node X to pull down through this path. When the inputs of the C-element are low, the output of the C-element will be high, node Q becomes 1, and this will bring QB low. In fact, at inverter I1, VDD with transistor M7 are placed in series with a pull-down network in order to execute an adequate delay for this stage. The designed FF contains a total number of 16 transistors which makes it a compact design. Moreover, there is no occurrence of transitions in the interior nodes at every clock cycle except if D implores output charges; thus, the power consumption is also reduced. The technique used in this design known as a ‘conditional transition’.

2.2. Proposed Shift Register Design

The shift register is composed of flip-flops in the group. The flip-flops are connected to each other in such a way that the output of a one flip-flop works as the input for another flip-flop. All of the flip-flops are operated with a common clock and are set or reset simultaneously. A register lets every flip-flop set free, for keeping the information of its nearby neighbor. Figure 6 represents the movement of basic data in the shift register.

The storing capacity in a register is the whole quantity of bits (zero or one) from digital data that may be held. Every flip-flop within a shift register is considered as one bit of storing capacity. The proposed FF integrating shift register can be used for low-power devices and high-speed real-time applications. In this article, the PIPO and SISO shift registers are designed by employing the proposed flip-flop with a supply voltage of 1.2 V in 130 nm CMOS technology. A schematic of four-bit parallel in/parallel out and four4-bit series in/series out shift registers are illustrated in Figure 7 and Figure 8.

3. Results and Discussion

3.1. Flip-Flop

The proposed FF circuit is designed with a reduced number (the modified circuit consists of 16 transistors while the original was 17 transistors) of transistors compared to the conventional circuit in [21]. The modified circuit has also been designed modifying the size of the Positive channel Metal-Oxide Semiconductor (PMOS) and Negative channel Metal-Oxide Semiconductor (NMOS). Figure 9 and Figure 10 describe the C-element output result and current profile, respectively. FFs were designed with the 130 nm CMOS process with a 1.2 V supply voltage. Figure 11 show the simulated waveforms of delay output of the proposed FF. The simulation results confirm that the proposed FF has a low power dissipation of 7.5499 nW and minimum delay compared to the original circuit and other FF designs. Figure 12 shows the layout design of the proposed FF circuit.

The performance comparison between the proposed FF circuit and other existing circuits in terms of CMOS process, the number of transistors used, supply voltage, power consumption, and minimum delay are summarized in

Table 1. Performance summary of flip-flops compared with other designs.

FF Designs	Proposed FF	SCCER [18]	DDFF [19]
Technology (CMOS)	130 nm	250 nm	90 nm
Number of transistors	16	17	18
Supply voltage	1.2 V	2.5 V	1.2 V
Total power	7.5499 nw	83.88 µw	205.42 µw
Minimum delay	102.78 ps	285.9 ps	166 ps

for a quick comparison.

From Table 1, it was determined that the efficiency of the FF can be assessed by calculating its number of transistors, power dissipation, and the delay of the FF. A minimum delay of 102.78 ps and the lowest power dissipation of 7.5499 nW are achieved implementing a conditional transition technique along with four clocked transistors. The power consumption in the proposed FF is significantly lower compared to other designs. Moreover, the proposed FF is designed by integrating fewer transistors among its counterparts in order to avoid circuit complexity.

3.2. PIPO and SISO Shift Registers

For PIPO shift registers all data bits, including inputs and outputs, perform parallel operations. The interconnected flip-flops are activated by a global clock. In Figure 7, D1, D2, D3, and D4 represent the parallel inputs and the QB1, QB2, QB3, and QB4 represent the parallel outputs. When the register clock is enabled, all input data (D1–D4) appears at the respective output (Q1–Q4) simultaneously. This kind of shift register is used as a temporary storage device or acts as a time delay device. The variation of the clock pulses’ frequency specifies the amount of the time delay. In addition, there are no interconnections in this kind of register between the individual FFs where no serial shifting of data is required. SISO shift registers receive one bit of data at a time in a single line, consecutively. It generates the kept data in the serial form on its output as well. Figure 13 and Figure 14 describe the simulation results for PIPO and SISO shift registers by using 130 nm CMOS technology with a 1.2 V power supply. The PIPO and SISO shift register are implemented integrating the proposed new flip flop and it is found that the performance of the shift register in the case of power dissipation and speed is improved and better compared to other existing designs.

This kind of the shift register is used as a temporary storage device or time delay device. The amount of time delay in that device is verified by the frequency of the clock pulse. Moreover, on that device, no interconnection between the individual flip-flop is required since no serial shifting data are needed. The designed PIPO shift register consumes 30.199 nW and the SISO shift register consumes 22.707 nW.

Table 2. Performance comparison among different parallel in-parallel out (PIPO) shift registers.

Shift Registers	Proposed PIPO	PIPO Using OBSC and RTPG FF [22]	PIPO Using EPTL FF [23]	PIPO USING D-FF [24]
Technology (CMOS)	130 nm	90 nm	50 nm	16 nm
Number of transistors	64	-	68	-
Supply voltage	1.2 V	1 V	-	0.7 V
Total power	30.1997 nw	52.997 µw	5.51 µw	748 µw
Minimum delay	102.78 ps	105 ps	-	1013.5 ps

and

Table 3. Performance comparison among different serial in–serial out (SISO) shift registers.

Shift Registers	Proposed SISO	SISO [22]	SISO [24]
Technology (CMOS)	130 nm	90 nm	250 nm
Number of transistors	64	-	-
Supply voltage	1.2 V	1 V	0.7 V
Total power	22.7071 nw	79.442 µw	658 µw

show the performance comparison among various designs of shift registers.

From the tables, it can be noted that the performance of shift registers can be evaluated by the power dissipation and the delay. The FFs are the basic storage elements widely used in all types of shift registers. FFs contribute as a chief part of the total chip area and power consumption to the entire system. The designer tends to choose a simple circuit architecture (fewer clocked transistors and smaller area) for the purpose of easy integration on a compact die. However, to meet the current goal of low power, high-performance CMOS devices for a wide range of application, like RFID and frequency synthesizers, designing a compact, efficient shift register is still challenging. Therefore, the proposed PIPO and SISO shift registers integrating a new flip-flop design with an implicit pulse-triggered structure is better than other designs in terms of speed performance and power dissipation. Figure 15 and Figure 16 show the layout of the designed PIPO and SISO shift registers, respectively, which covers a 5.5 µm × 4 µm chip area.

4. Conclusions

In this article, low-power, compact, four-bit PIPO and SISO shift registers integrating an implicit pulse-triggered flip-flop are presented addressing privacy issues in RFID technology. The proposed FF is designed implementing four clocked transistors which reduced the power dissipation. In addition, the proposed circuit is designed utilizing a minimum number of transistors compared to its counterparts. The C-element is utilized for two input signals through the input data and the common node of two series transistors. Hence, the accurate output value is achieved. The proposed FF achieved significant low-power consumption of 7.54 nW and a minimum delay of 102.78 ps, while PIPO and SISO shift registers achieved low-power consumption of 30.199 and 22.7071 nW, respectively. The proposed FF, PIPO, and SISO shift registers are designed and simulated in 130 nm CMOS technology with a 1.2 V power supply.