3.1. Worst-Case Selected Location
As reported in previous studies, with finite interconnection resistance, the voltage and current delivered to the selected cell would differ depending on the location [
19,
20]. To evaluate the impact of the selected location on the readout current, the LRS/HRS read operations are performed across the whole crossbar array. For each cell operation, the selected device is in LRS or HRS, whereas the rest of the array is initialized with a random data pattern with an equal distribution for the LRS and HRS. The sensing current of reading LRS or HRS is calculated and illustrated in
Figure 3a,b, respectively. One can clearly observe that the LRS sensing current (
, normalized by
,
) and HRS sensing current (
, normalized by
,
) are degraded in approaching the top-right corner, which is the furthest corner from the WL and BL voltage sources. During read operations, both the interconnection resistances and parasitic sneak paths would degrade the current delivered to cells further away from voltage sources. Since the array is uniformly distributed with the LRS and HRS, it is reasonable to consider that the data pattern has an equivalent impact on each cell across the whole crossbar array. Therefore, the sensing current variations are predominantly influenced by the interconnection resistances instead of parasitic sneak paths. The worst affected cell is that the selected cell located at the furthest corner from the WL and BL voltage sources. In this case, the current decay caused by the interconnection resistances is the largest, and all current between the selected WL and grounded WLs/BLs would effectively bypass the selected cell and choose shorter pathways throughout the array instead of injecting into the selected BL. In addition, to some extent, the interconnection resistances could help to make the very corner near the WL and BL voltage sources isolated from parasitic sneak paths in the rest of the array, while also making the worst affected corner less accessible.
On the other hand, the sensing margin ((
) normalized by
) of each bit is also degraded toward the furthest corner, as shown in
Figure 3c. For the purpose of illustration, the average sensing current evolution along the topmost WL is simulated over 50 samples of random data pattern initializations, as shown in
Figure 3d. Both
and
decrease with respect to the bit position. Compared to
,
decreases more rapidly, causing the sensing margin of each bit also degrading with respect to the bit position. This is because that the
is more sensitive to the current damping effect of the interconnection resistance. For a simple explanation, as shown in
Figure 4, one may consider a series circuit consisting of one fixed resistor, the selected memory cell, whose resistance equals to LRS or HRS, and another variable resistor, the equivalent parasitic resistance connected in series with the selected memory cell in this case. These two serially connected resistors form a voltage divider. When a fixed voltage (
) is biased to the serially connected resistors, the current flowing through the circuit can be derived from the voltage drop across the memory cell. Assuming that the memory cell is in the HRS, almost all the bias is transferred to the memory cell due to the much higher resistance of the HRS compared with the series parasitic resistance. Even though the serially connected parasitic resistance increases as the selected cell locates further away from voltage sources, the decrease in the voltage drop across the selected cell is almost negligible, thus causing the current flowing through the circuit to decrease more slowly compared with that when the selected cell is in the LRS.
From the simulation results above, it can be concluded that the worst-case selected locations corresponding to the minimum
and maximum
occur at the furthest and closest corner from the WL and BL voltage sources, respectively. However, this would make the evaluation of the worst-case data patterns too complicated for the worst-selected cell of reading LRS and HRS occurring at two different locations. Particularly, a novel self-adjusting reference circuit utilizing the locality principle has been proposed for the passive RRAM crossbar array read operation, which can help to relieve the requirement of a constant reference scheme [
20]. In this case, the cell with a worst-degraded read margin will be a limiting factor for the peripheral sensing circuit design. Therefore, it is reasonable for us to define the cell located at the furthest corner from the power lines as the worst-case selected cell for read operation. This is also consistent with the practice in previous studies. In the following, the selected location is fixed to this bit cell.
3.2. Worst-Case Data Pattern
To evaluate the impact of data patterns on the sensing current, the whole crossbar array is divided into three regions, i.e., word-complement cells (
), bit-complement cells (
), and the rest of the array (
), as shown in different colors in
Figure 1a. In most previous studies, cells in the same region are assumed to share the same resistance state, but they can be different from those in other regions. With this assumption, it is conceivable that eight extreme data patterns can be acquired, as shown in
Figure 5. In this section, a data-dependent sensing current evaluation is performed with respect to the probability of LRS within the
(
),
(
), and
(
), respectively. The data probability of these three regions are individually controlled. According to the eight-extreme-data-pattern categories, each region (i.e.,
) is investigated with the other two regions either in HRS or LRS (i.e.,
0 or 1), as shown in
Figure 5b. For each individual region, the data pattern is randomly generated for a given probability with an uniform distribution throughout the whole region. In this case, the LRS and HRS are randomly assigned and uiformly distributed in the individual region. Therefore, it is reasonable for us to assume that this statistical approximation can approximately reflect the average trend of the effect of data patterns on the sensing current. It is noted that such a statistical approximation approach has also been employed to estimate the array performance in the previous studies [
14,
21].
First, we investigated the dependence of
and
on the data probability of each region (i.e.,
) while keeping the remaining two regions in HRS (i.e.,
), as shown in
Figure 6. With
and
increasing, the sensing current is significantly degraded, while
has almost negligible effects, slightly enhancing the sensing current. This result can be explained by the sneak paths involved during the read operation. The sneak paths are significantly affected by data patterns [
21].
Figure 7 is the approximate model of the crossbar array to elucidate the roles of different regions in shaping the sneak paths. As shown in
Figure 7a, a large number
of complement cells are connected in parallel with the selected cell at the selected WL and BL, respectively; thus, the parasitic sneak paths are predominantly determined by
and
. Since all the unselected lines are grounded, as
and
increase, the current flowing along the selected WL and BL would be effectively shunted.
Ideally, the current flowing through the cells in
is supposed to be zero due to the symmetric bias on their WL and BL terminals. However, due to the non-zero interconnection resistance, the unselected WLs and BLs cannot be assumed to be sufficiently well grounded throughout their entire lengths, thus resulting in above ground voltages at the terminals of the unselected cells where the voltages are supposed to be zero. In this case, the cells in
that are not supposed to conduct sneak currents actually conduct a slight sneak current, and they can be treated as resistors connected with the unselected lines in series. For example, as shown in
Figure 7b, two sneak paths serially connected with the cell of
in
, marked as (i) and (ii), respectively, can be conceivable. For the sneak path (i), we can get the Equation (
5):
As the resistance of
decreases from HRS to LRS, the node voltage of
will increase, as a result of which the sneak current of
will be suppressed. For the sneak path (ii), we can get the Equation (
6):
Similarly, as the resistance of decreases from HRS to LRS, the node voltage of will increase, which will also hinder the sneak current of in return. Therefore, as increases, the equivalent resistance of with cells connected in parallel would decrease rapidly, thus facilitating the rising of the node voltages at the WL terminals of the bit-complement cells () and the BL terminals of the word-complement cells (), respectively, hindering the shunting effect of the complement cells. Moreover, when the node voltages at the WL terminals of the bit-complement cells are above those of their BL terminals, extra sneak currents would be injected into the selected BL.
Figure 8 shows the simulated
associated with different array sizes, data probabilities,
k, and
r for the three different crossbar array regions (the data for
exhibit the same trends and are not shown here). The sensed current decreases as the crossbar array size increases because this change leads to a larger current degradation along the selected WL and BL. As
k and
r decrease, the current degradation is more obvious. This effect can be explained from the fact that deceasing the value of LRS and on–off resistance ratio decreases the memory cell resistance, which is detrimental for mitigating the parasitic sneak leakage and lowering the current decay caused by the interconnection resistances. It is also worth noting that the sensing current decreases as
and
increase but slightly increases as
increases.
To verify the validity of the above analysis, we also investigated the dependence of the sensed
and
on the data probability of each group (i.e.,
) while keeping the other two groups in LRS (i.e.,
) for various array sizes, as shown in
Figure 9. For
, the data-dependence exhibits a similar trend as shown in the previous simulation. However, for
, the data-dependence shows much more complicated behavior. When the crossbar array size is small, the sensing current degrades as
and
increase, but slightly increases as
increases. On the other hand, when the array size is larger, the sensing current would be enhanced as
,
, and
increase. The simulated
associated with different array sizes,
k,
r, and data probabilities of
is shown in
Figure 10 (the data associated with the data probabilities of
and
exhibit the same trends and are not shown here).
The existence of two different data-dependences of
on
and
with respect to the array size is the result of two competing mechanisms arising from the memory cell resistance. On the one hand, a higher HRS can help to suppress parasitic sneak leakages. When the dependence of
on the data probability of
or
is investigated with the other two groups in HRS, the sneak currents injection into the selected BL is dominantly prohibited by the large value of HRS. The shunting effect of the unselected WLs/BLs prevails over the parasitic sneak currents injection. Hence, with the data probability increasing, the current would bypass the selected BL and choose shorter pathways throughout the crossbar array, as is previously shown in
Figure 8. On the other hand, the small value of LRS is detrimental for suppressing parasitic sneak currents. When we investigate the dependence of
on the data probability of
or
with the rest two groups in LRS, the sneak currents injection into the selected BL could be prohibited by the interconnection resistances reluctantly within a small array size. In this case, as the data probability increases, the shunting effect of the corresponding complement cells would be enhanced, causing the sensing current degradation as well (
Figure 10a, marked (i)). However, as the array size increases, the total resistance of the array decreases rapidly, which will make the current throughout the whole crossbar array significantly improved. Large amounts of parasitic sneak currents would be injected into the selected BL inevitably as the data probability increases (
Figure 10a, marked (ii)). As the array size continues to increase, the sneak currents injection would be damped and shunted by the interconnection resistances and shorter pathways (
Figure 10a, marked (iii)).
In addition, there are two other trends worth mentioning. Firstly, as
k increases, the sneak currents injection into
tends to occur at a larger array size (
Figure 10a–c). This is probably because, with a larger value of
k at a specific value of
r, the memory cell resistance is much larger as well. Thus, the total resistance of the crossbar array could only decrease at a larger size. Secondly, the effect of sneak currents injection is also dependent on
r. The larger the value of
r is, the smaller array size the sneak currents injection occurs at, and the more significantly the sneak currents would inject (
Figure 10d–f). This is because that with a larger on–off ratio at a specific LRS,
is much more sensitive to the sneak currents injection. A threshold array size (
) for sneak currents tending to inject into
is roughly presented in
Figure 11, which could be more accurately depicted with more detailed simulation parameters.
From the analysis above, we can conclude that is dominantly determined by the trade-off between the shunting effect of sneak paths and the current injection effect of parasitic leakages. When the crossbar array size is small (e.g., <), the shunting effect prevails. Thus, as the probability of HRS in and increases, large amounts of the current bypassing the selected BL and choosing the shorter pathways throughout the crossbar array would be prohibited. Due to the non-zero interconnection resistance, as the probability of LRS in increases, the shunting effect would be slightly suppressed further. Therefore, the worst-case data pattern for HRS reading corresponds to all complement cells ( and ) being in HRS, and the remaining unselected cells () being in LRS. When the array size increases (e.g., >), sneak currents would significantly inject into the selected BL, interfering with the shunting effect of parasitic sneak paths. As the probability of LRS increases in the whole crossbar array, the sensing current would be enhanced. Thus, the worst-case data pattern occurs when all unselected cells are in LRS.
For
, we notice that a similar trade-off occurs in our simulation as well, but manifests at a much larger threshold array size, which could be simply deduced by setting
in
Figure 11, with the sensing current significantly degraded. Therefore, the current injection effect of the parasitic leakage is almost negligible. It is reasonable for us to simply consider that
is dominantly interfered by the shunting effect of the parasitic sneak paths. In this case, the worst-case data pattern for LRS reading occurs when the complement cells (
and
) are in LRS, and the remaining unselected cells (
) are in HRS.
The overall discussion in this paper is based on the GND read scheme for its complicated parasitic sneak paths. However, the analysis method can also employed to the other two read bias schemes, known as the V/2 and V/3 read schemes. In the V/2 scheme, all unselected WLs and BLs are biased at . In the V/3 scheme, all unselected WLs are biased at , while all unselected BLs are biased at . Since all of the unselected WLs and BLs are biased with voltage sources, the current throughout the whole crossbar array is eventually injected into the selected BL. Thus, all the unselected cells can be regarded as part of the parasitic sneak paths in parallel with the selected cell. Therefore, the worst-case data pattern for V/2 and V/3 read schemes occurs in the following case: (i) when reading LRS, all unselected cells are in HRS; and (ii) when reading HRS, all unselected cells are in LRS.