Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

Abstract

Multiple supply voltage is the most prevalent method for low power reduction in the design of modern Integrated circuits. Floorplanning process in this design performs positioning of functional blocks in the layout satisfying both fixed outline and voltage island constraints. The floorplans while satisfying these two significant constraints causes significant rise in wirelength and congestion. In this paper, a congestion and wirelength aware floorplanning algorithm is proposed which allows effective placement of functional blocks in the layout to satisfying fixed outline and voltage island constraints simultaneously. To perform voltage island floorplanning, the proposed algorithm uses Skewed binary tree representation scheme to operate the functional blocks in its predefined voltage level. The proposed methodology determines the feasible dimensions of the functional blocks in the representation which aids the placement process for the reduction of congestion and wirelength. With these optimal dimensions of the functional blocks, floorplanning is also performed for the layouts of aspect 1:1, 2:1, and 3:1, to evaluate the ability of proposed algorithm for satisfying the fixed outline constraint. The proposed methodology is implemented in the layout of InternationalWorkshop on Logic and Synthesis (IWLS) benchmarks circuits for experimental purpose. The resulting floorplans were iteratively optimized for optimal reduction of wirelength and congestion. Experimental results show that the proposed methodology outperforms existing state-of-the-art approaches in wirelength reduction by about 18.65% and in congestion reduction by around 63%, while delivering the 30.35% power consumption.

1. Introduction

Design of low power integrated circuits (IC) has become a challenging problem due to the continuous technology scaling. In the design of chips for modern applications like solar [1,2], motor control [3,4] and smart energy systems [5], power consumption plays a significant role. Comparatively, the contribution of dynamic power due to the frequent switching action of more number of transistors is more pronounced in these ICs to static power dissipation. Deployment of multiple supply voltages in the ICs is one of the best-known technique for the reduction of dynamic power consumption [6]. In this technique, the modules in the chip operate at different voltages, in addition to the chip level voltage [7]. Even though it helps in power savings, this introduces a lot of new challenges in the physical design process. Electronic design automation industries follow a unique design flow to reduces the complexities of the design process. The Figure 1 depicts the state-of-art design flow for multiple supply voltages (MSV) designs. It involves three essential phases (a) voltage assignment, (b) insertion of level shifters, and (c) floorplanning [8,9].

To meet the demand on miniature ICs, the researchers focuses on fixed-outline floorplanning considering reduction of wirelength [10]. Increase in number of voltage islands increases the routing source and complicates power planning [11]. Among the various methods, voltage island-based floorplanning provides a better solution with minimization is power routing resource in the layout [12]. In this method, the floorplanner places the modules of similar operating voltage in a region, named as voltage island. Usually, this voltage island constraint-based floorplanning appears either in post floorplanning/placement stage. The voltage assignment phase determines the suitable operating voltage of the modules in the layout by examining the delay and power characteristic for the predefined set of voltages [13,14,15,16,17,18,19,20,21,22,23,24]. In some cases, the decision making for the selection of appropriate become tough due to the best performance of modules in a group of voltage levels. Lee et al. presents a method which considers reconvergence fan-out for optimal voltage assignment [8]. As the modification, this work, many papers focus provides a solution for voltage assignment and floorplanning. Sengupta et al. proposed an algorithm for core-based designs and contributed a power state model approach which aids for voltage assignment based on IDLE, ON, OFF states of the cores in the chip. Some of the papers give a significant contribution to the place of level shifters to satisfy the timing constraint [25].

After the process of voltage assignment, these algorithms perform floorplanning using a data structures available for single supply voltages. The methodologies present in the literature follows the implementation of algorithms either in Gigascale Systems Research Center (GSRC) or Microelectronics Center of North Carolina(MCNC) benchmarks. These algorithms mainly consider wirelength and time complexity as the Figure of merit for evaluating the effectiveness of the methodology. The academic floorplanners use structures like B* tree [26], Normalized polish expression (NPE) [27,28], Transitive closure graph (TCG) [29], Sequence pair (SP) [30], and Skewed binary tree (SKB) [31] to represent the modules in the initial floorplan. Further, upon perturbations and using packaging methodologies for compactness results in a reduction of dead space and wire length. For fast convergence and accurate results, simulated annealing framework is employed with a cost function, consisting of wirelength and deadspace. Some of the other approaches include perturbation of modules in the layout and random positioning and legalization using mathematical formulations. Quadratic and second-cone programming methodologies provide a notable reduction in wirelength in these MSV designs [32]. Even though these academic benchmarks show betters results in GSRC and MCNC circuits, their performance becomes typical after implementation is commercial Electronic design automation (EDA) tools like CADENCE, SYNOPSYS, etc.

Some of the notable facts after implementation of academic floorplanners are:

• In the design of small size chips for various applications, the floorplanning processes require positioning of modules in the layout within the predefined application-specific aspect ratio. After implication of an application specific aspect ratio in an industry tool, the synthesis process it comparatively changes dimensions of the blocks inside the chip from its default area. This transformation is due to the high-level synthesis process involved in the EDA tool and results in the availability of unplaced modules outside the core region of the layout.
• Increase in geometric violations while performing design rule check.
• Avoids setup and hold time conditions.
• Fails to consider the placement of standard cells and other challenges in the physical design after detailed routing.

In addition, conventional design MSV flow shown in Figure 1 is completely different in a EDA tool. The Figure 2 shows design flow for MSV design in Cadence Innovus software for digital designs.

This paper devotes to overcome the challenges as mentioned above while implementing MSV design floorplanning algorithm in an EDA tool. The main contributions in this paper are listed below:

• Solution to industrial floorplanning: This paper implements the conventional SKB tree meant for academic benchmarks in industrial EDA environment. While implementation of conventional SKB methodology for different aspect ratios, some of the modules are unable to position inside the core area of chip. This is paper overcomes this problem using the proposed algorithm through finding the optimal dimensions of modules in the design.
• Elimination of cluster constraint: While fixed-outline floorplanning for various aspect ratios of the chip, there are more number of unplaced modules outside the core area of the layout. The proposed algorithm places those modules inside the core area of the floorplan with short wirelength and reduces the percentage of congestion.
• Avoiding re-voltage assignment: This paper performs iterative improvement in positioning of modules inside the voltage island, this results in reduction of wirelength, congestion and power. The conventional SKB tree performs exchange of modules both intra and inter voltage island modes. This process leads to change of assigned voltage to modules and increases wirelength. Since the proposed algorithm accommodates all its modules inside the voltage island, the perturbations were performed within the voltage island. Through iterative improvement, the proposed algorithm reduces wirelength and congestion.
• Unoccupied space for post-floorplanning stages: Unlike the previous works, the proposed algorithm performs concurrent fixed-outline floorplanning and voltage island floorplanning for the minimization of wirelength and power consumption under various aspect ratio. The results show a notable contribution to power saving and wirelength compared to state-of-art methods.

The rest of this paper is organized as follows: Section 2 presents the existing SKB tree methodology for floorplanning with voltage island and fixed outline constraints. Section 3 gives the proposed algorithm and a placement methodology to formulate the problem while floorplanning in EDA tool. Section 4 reports the experimental reports. Finally, Section 5 concludes this paper.

2. Preliminaries

This paper proposes a algorithmic method which is based on the existing the Skewed Binary (SKB) representation in [31]. Hence this section first reviews floorplanning topology using SKB and Section 3 presents proposed floorplanning methodology to manage fixed outline and voltage island floorplanning.

2.1. Floorplanning Representation

Consider the tree structure shown in Figure 3. Modules operating at similar voltage levels are placed at the parent node, one after another, in the left side of every node in a branch. Thus, they form a voltage island. Each node contains modules on the right side of the parent node. The parent node in the tree structure is placed in the left-corner of the voltage island. Every parent node of the branch is connected to the root node due to its inter connectivity. Thus, each branch will have modules at different operating voltages.

Figure 3b illustrates a typical SKB tree representation and Figure 3a shows the floorplan of a circuit consisting of 10 modules. Modules $\{n_1,n_2,n_3,n_4\}$ operate at voltage level-1 and $\{n_5,n_6,n_7\}$ at voltage level-2. Similarly, $\{n_8,n_9,n_{10}\}$ modules work at voltage level-3. $n_1$ is considered as a parent node at level-0 since it needs to be placed in the left corner of the floorplan. Similarly, modules $n_5$ and $n_8$ represents the parent node for levels 1 and 2, and they are placed in the left corner of their power domain.

In this way, SKB tree helps the designer with the placement of modules in the core area of a chip. In the event of tree traversal, the time complexity is reduced for the placement of modules in the core area of the chip.

2.2. Placement Process

Consider a chip, with N number of modules in its design. Let $N=\{n_1,n_2,\dots ,n_i\}$, where $n_1,n_2,n_3,\dots ,n_i$ are the modules in the design and $M=\{m_1,m_2,m_3,\dots ,m_j\}$ is a set containing voltage islands in N. With the dimension of modules in width and height, the tree structure in Figure 3 is used to allocate a space in the floorplan, based upon its operating voltage. Using the conventional depth first search algorithm, the modules are filled in the voltage island region one after another. The  width of the power domain is calculated as

$$W_i=\frac{a_i}{a_t}{W}_c(1+\gamma )$$

(1)

In the above Equation (1), $a_i$ refers to the total area of modules in the power domain, $a_t$ refers to the total area of the chip, $W_c$ refers to the width of the chip and $\gamma$ refers to the allowable dead-space.

Before a module is placed in a voltage island region, the algorithm determines the fitness of a module in the allotted width of the voltage island $W_i$. If the module width $ni(wi)$ is greater than $Wi$, the algorithm pushes in the $n_i$ queue and traverses the tree for the insertion of the next module $n(i+1)$ in the $m_j$ region. Before the placement of module $n(i+2)$ of $m_j$, the algorithm prioritizes the modules in the queue. If the module fails to fill the region, several modules would be combined as a merged block to fill up the region. For the successful placement of that merged module, a contour is drawn, unlike in [26], to estimate the feasible placement of the module. This procedure is iterative, until all the modules in the queue and voltage islands are placed in its region of $mj$.

Figure 4 depicts the placement process of modules inside the voltage island. In Figure 4, the width of the module b4 is greater than the width of voltage island W1. This can be avoided through merging the modules b4, b5, as illustrated in Figure 5.

To avoid the congestion and aforementioned merging of modules, cluster constraint is introduced which serves as an upper bound on the density of modules in the voltage island. Thus, the algorithm limits the number of modules in voltage islands and produces a compact floorplan.

2.3. Our Contributions

This paper proposes a floorplanning methodology based on SKB tree representation and performs voltage island floorplanning eliminating the cluster constraint in the conventional SKB tree methodology. Unlike the conventional SKB tree, the proposed methodology also predetermines the width of voltage island using the Equation (1). For tight packing of modules within this pre-estimated island width, this paper proposes an algorithm which determines the optimal dimensions of modules. Placement of these modules with their optimal dimensions positions all the modules of voltage island inside this width. However, for the reduction of power, congestion and wirelength, this procedure repeated iteratively. Different from conventional SKB methodology, the proposed methodology is implemented in Cadence EDA tool for the synthesized netlist of IWLS benchmarks to provide solutions to the industrial floorplanning problems. In addition to this voltage island floorplanning, proposed algorithm is also performed for fixed outline floorplanning, and simultaneous fixed and voltage island floorplanning.

Simulations were on both conventional SKB and proposed floorplanning methods using Cadence EDA tool. To compare the effectiveness of the proposed algorithm, four different experiments were performed in this paper. In first experiment for floorplanning with zero deadspace, the proposed methodology gives 18% of reduction in wirelength while satisfying the fixed outline constraint. Second experiment is performed for floorplanning with 15% deadspace on various aspect ratios of chips. The results reveals that the proposed floorplanning method gives average reduction of 29.3% and 63% in wirelength and congestion. In third experiment the proposed algorithm performs voltage island floorplanning with 38.7% reduction of power. Different from conventional SKB method, we perform an experiment to test ability of proposed algorithm to satisfy both fixed and voltage island floorplanning simultaneously. The results show that proposed algorithm provides reduces 22% of power consumption and increases the percentage of power saving compared with conventional SKB tree method.

3. Proposed Methodology

3.1. Step 1: Initial Floorplan

Given the dimensions of modules-in-chip in width and height as well as the operating voltage, we assign the modules in each node of the SKB tree structure. Our proposed floorplanning algorithm overcomes the drawbacks in the SKB tree algorithm for the multiple supply voltage (MSV) design of voltage island floorplanning, without any change in the area of the module.

Table 1. Parameter description in Algorithms 1 and 2.

Parameter	Description
T	tree structure as shown in Figure 3b
level	levels in T
M	set containing all the modules in the design
$m_i,m_j$	two consecutive modules in a level
$w_i,h_i$	width and height of module $m_i$
$w_j,h_j$	width and height of module $m_j$

presents the parameters used in our proposed Algorithms 1 and 2.

Given a module-based design, with all its module dimensions in width and height, and its operating voltage, a tree structure is obtained from the initial floorplan as shown in Figure 3. Modules are arranged in tree structure T, as explained in the Section 2.1.

3.2. Step 2: Optimal Dimension of Modules

After the arrangement of modules in the tree structure, the optimal dimensions of modules are estimated to fit all the modules in its voltage island. The optimal dimension is obtained using the Algorithms 1 and 2.

Given a tree structure, T, with nodes representing modules, M, and levels of the tree representing voltage levels, we obtain the optimal dimensions for the modules $m_i$ and $m_j$, using the procedure $Opt\_dimension(m_i,m_j)$, where $m_i,m_j\in M$. Finally, after obtaining the optimal dimensions, it is updated to the existing dimensions of $m_i$ and $m_j$.

The Algorithm 2 describes the procedure to find the optimal dimensions of the modules. Lines (3–14) in the algorithm aims to find the optimal dimension of $m_i$ and $m_j$. Stock–Meyer’s equation for vertical bisection used for non-slicing methodology is used to find the optimal dimensions of $m_i$ and $m_j$. It computes the list of possible dimensions, for a given module size in width and height.

Consider the two modules $m_i$ and $m_j$ with dimensions $(w_i,h_i)$ and $(w_j,h_j)$ present in a voltage island. The proposed algorithm in this paper determines the optimal dimensions of the modules without changing the area of the module. Hence, the algorithm assumes duplicate dimensions of modules $m_i$ and $m_j$ as $t_1$ and $t_2$. The dimension of $t_1$ is assumed as $t_1\left(w_i\right)=h_i$ for width which is height of module $m_i$ while $t_1\left(h_i\right)=w_i$ for height which is actually the width of module $m_i$. Similarly, for module $m_j$ its duplicate is assumed as $t_2\left(w_j\right)=h_j$ and $t_2\left(h_j\right)=w_j$. The proposed algorithm finds the optimal area required to floorplan the modules $m_i$ and $m_j$, both width-wise and breath-wise, using the Equations (2)–(7). The Equation (2) helps to determine the optimal dimension required to floorplan two modules with its original dimensions $(w_i,h_i)$ and $(w_j,h_j)$. In this Equation (2), u denotes the optimal width and v denotes optimal height after merging the modules $m_i$ and $m_j$.

$$(u,v)=[w_i+w_j,max\{h_i,h_j\}]$$

(2)

For minimum area floorplan, the algorithm compares value of u and v. If the value of u is greater that v, optimal dimension is determined using duplicate dimensions of module mi. It is given by the Equation (3),

$$(u,v)=[t_1\left(h_i\right)+h_j,max\{t_1\left(w_i\right),h_j\}]$$

(3)

Algorithm 1 $Initialize\left(T\right)$

1 A Tree T, with nodes representing modules in the design, 2 $level\leftarrow 1$, where $level\in T$ 3 for$level$do 4     $M\in T$; $m_i{m}_j\in M$; 5     Choose $m_i$ and $m_j$; 6     $Opt\_dimension(m_i,m_j)$; 7     update $m_i$ and $m_j$; 8 end for

Algorithm 2 Opt_dimension(mi,mj)

1 $S=\varnothing ;P=\varnothing ;$ // initialize the set S and P;  2 top:  3 while$m_i,m_j$do // for module $m_i,m_j$ find the optimal dimensions length-wise;  4     $(u,v)=[w_i+w_j,max\{h_i,h_j\}];$ //compute the dimension after merging;  5     $S+=(u,v);$ // store all the resulting dimensions in set S;  6     if $u>v$ then  7         $(u,v)=[t_1\left(h_i\right)+h_j,max\{t_1\left(w_i\right),h_j\}];$ // Compute the new dimensions using $t_1$;  8         $S+=(u,v);$// store all the resulting dimensions in set S;  9     else 10         $(u,v)=[t_2\left(h_j\right)+h_i,max\{t_2\left(w_j\right),h_i\}];$ // Compute the new dimensions using $t_1$; 11         $S+=(u,v);$ //store all the resulting dimensions in set S; 12     end if 13 end while 14 find minimum of S; // Find the minimum dimension in set S; 15 while$m_i,m_j$do// for module $m_i,m_j$ find the optimal dimensions width-wise; 16     $(u,v)=[max\{m_i\left(w_i\right),m_j\left(w_j\right)\},m_i\left(h_i\right)+m_j\left(h_j\right)];$ // compute the dimension after merging; 17     $P+=(u,v);$ // store all the resulting dimensions in set S; 18     if $u>v$ then 19         $(u,v)=[max\{t_1\left(h_i\right),m_j\left(h_j\right)\},t_1\left(w_i\right)+m_j\left(h_j\right)];$ // Compute the new dimensions using $t_1$; 20         $P+=(u,v);$ 21     else 22         $(u,v)=[max\{t_2\left(h_j\right),m_i\left(h_i\right)\},t_2\left(w_j\right)+m_i\left(h_i\right)];$ // Compute the new dimensions using $t_2$; 23         $P+=(u,v);$ 24     end if 25 end while 26 find minimum of P; // Find the minimum dimension in set P; 27 find minimum (S,P); // Find the minimum dimension in set S and P; 28 update minimum area dimension to $m_i,m_j$; // update these optimal dimensions in $m_i,m_j$; 29 $i\leftarrow i+1;$ 30 $j\leftarrow j+1;$ 31 gototop;

For u less than v, Equation (4) is used to find the optimal dimensions to occupy the modules $m_i$ and $m_j$.

$$(u,v)=[t_2\left(h_j\right)+h_i,max\{t_2\left(w_j\right),h_i\}];$$

(4)

The resulting dimensions from Equations (2)–(4) are stored in a set S.

In the above Equation (4), the algorithm finds the possibilities for optimal dimension with duplicate dimensions of module $m_j$. Thus, the algorithm finds the optimal dimension width-wise. In the same way, the algorithm uses the Equations (5)–(7) to find the height-wise optimal dimensions.

$$(u,v)=[max\{w_i,w_j\},h_i+h_j]$$

(5)

$$(u,v)=[max\{t_1\left(h_i\right),h_j\},t_1\left(w_i\right)+h_j]$$

(6)

$$(u,v)=[max\{t_2\left(h_j\right),h_i\},t_2\left(w_j\right)+h_i]$$

(7)

the resulting dimensions from Equations (5)–(7) are stored in a set P.

A minimal area dimension area is chosen from the set S and P and we update the dimensions of modules $m_i$ and $m_j$.

Repeating this process with all the modules in the voltage islands, results in placement of all the modules within pre-estimated width of $W_i$. This helps the proposed algorithm for the placement of modules in the layout eliminating cluster constraint introduced in the conventional SKB tree methodology.

3.3. Example for Determining Optimal Dimensions of Modules

For better understanding of proposed methodology simple illustration is given below for determining optimal dimension of modules in the first level of the SKB tree shown in Figure 6. It constructed for a design with three voltage islands consisting of eight modules.

The nodes in the tree represents the modules in the layout and the levels of the tree represents voltage domains. The dimensions present above every node are the width and height of the modules. The proposed algorithm in this paper performs the following procedure and determines the optimal dimensions of modules in the tree structure.

From the Figure 6, let $N=\{n_1,n_2,n_3,n_4,n_5,n_6,n_7,n_8\}$ are the modules with dimensions (width, height) in micro metres.

The algorithm proceeds with the following steps given below.

1.

Taking the vertices $n_4$ and $n_3$. Let $U=\{(3,5),(5,3)\}$, $V=\{(3,3)\}$.

For the vertical orientation,

(i)

join $u_{11}=(3,5)$ and $v_{11}=(3,3)$, we get $(3+3,max\{5,3\})=(6,5)$. Since the maximum is from U, we join $u_{12}$ and $u_{11}$.

(ii)

join $u_{12}=(5,3)$ and $v_{11}=(3,3)$, we get $(5+3,max\{3,3\})=(8,3)$

The resulting dimensions are $(6,5)=30$ μm² and $(8,3)=24$ μm². The minimum of these is 24 μm².

For the horizontal orientation,

(i)

join $u_{11}=(3,5)$ and $v_{11}=(3,3)$, we get $(max\{3,3\},5+3)=(3,8)$. Since the maximum is from V, we join $u_{12}$ and $u_{11}$.

The resulting dimensions is 24 μm². As a result, the dimensions either $\left[\right(3,5)$ and $(3,3)]$ or $\left[\right(5,3)$ and $(3,3)]$ can be taken for minimum area.

2.

Taking the vertices $\{n_4,n_3\}(3,8)$ and $n_2(1,3)$, Let $U=\{(3,8),(8,3)\}$, $V=\{(1,3),(3,1)\}$. For the vertical orientation,

(i)

join $u_{11}=(3,8)$ and $v_{11}=(1,3)$, we get $(3+1,max\{8,3\})=(4,8)$. Since the maximum is from V, we join $u_{11}$ and $v_{12}$.

(ii)

join $u_{11}=(3,8)$ and $v_{12}=(3,1)$, we get $(3+3,max\{8,1\})=(6,8)$

The resulting dimensions are $(4,8)=32$ μm² and $(6,8)=48$ μm². The minimum of these is 32 μm².

For the horizontal orientation,

(i)

join $u_{11}=(3,8)$ and $v_{11}=(1,3)$, we get $(max\{3,1\},8+3)=(3,11)$. Since the maximum is from V, we join $u_{11}$ and $v_{12}$.

(ii)

join $u_{11}=(3,8)$ and $v_{12}=(3,1)$, we get $(max\{3,3\},8+1)=(3,9)$.

The resulting dimensions are 33 μm² and 27 μm². The minimum of these dimensions is 27 μm². Finally, the minimum of dimensions horizontal 27 μm² and vertical 32 μm² is taken as the dimensions.The minimum of these is, 27 μm². Its co-ordinates are $(3,8)$ and $(3,1)$. The area of the merged modules $\{n_4,n_3\}$ is fixed as $(3,8)$.

3.

Taking the vertices $\{n_4,n_3,n_2\}(3,9)$ and $n_1(2,4)$.

Let $U=\{(3,9),(9,3)\}$, $V=\{(2,4),(4,2)\}$ For the vertical orientation,

(i)

join $u_{11}=(3,9)$ and $v_{11}=(2,4)$, we get $(3+2,max\{9,4\})=(5,9)$. Since the maximum is from V, we join $u_{11}$ and $v_{12}$.

(ii)

join $u_{11}=(3,9)$ and $v_{12}=(4,2)$, we get $(3+4,max\{9,2\})=(7,9)$

The resulting dimensions are $(5,9)=45$ μm² and $(7,9)=63$ μm². The minimum of these is 45 μm².

For the horizontal orientation,

(i)

join $u_{11}=(3,9)$ and $v_{11}=(2,4)$, we get $(max\{3,2\},9+4)=(3,13)$. Since the maximum is from V, we join $u_{11}$ and $v_{12}$.

(ii)

join $u_{11}=(3,9)$ and $v_{12}=(4,2)$, we get $(max\{3,4\},9+2)=(4,11)$.

The resulting dimensions are 39 μm² and 44 μm². The minimum of these dimensions is 39 μm².

From the $(3,13)$ = 39 μm², if $W_P=13$, the procedure given below is followed i.e., the update on the dimensions of the modules is performed, else, a new module is taken from the tree structure and again the procedure for horizontal and vertical orientation is repeated until the resulting merged dimension is equal to $W_P$.

Finally, the minimum of dimensions horizontal 39 μm² and vertical 45 μm² is taken as the dimensions. The minimum of these is, 39 μm². Its co-ordinates are $(3,9)$ and $(2,4)$.

The area of the merged modules $\{n_4,n_3,n_2\}$ is fixed as $(3,9)$. For the modules $\{n_4,n_3\}$ and $n_2$, the updated dimensions are $(3,8)$ and $(3,1)$.

Now, for $(3,8)$, the modules $n_4$ and $n_3$ holds the dimensions as $(3,5)$ and $(3,3)$.

Thus the optimum dimension for voltage island 1 is found to be 39 μm².

3.4. Step 3: Placement

After updating the dimensions in modules for all voltage islands using depth first search, the modules are placed in the core area of layout from the lower left corner within the pre-estimated width. If a module failed to fit in the width $W_i$, it is pushed in a temporary queue and priority is given for the next module. Before the placement of any module inside the voltage island, modules in the queue are prioritized to check the feasibility of placement within the size of $W_i$.

Presence of unoccupied space in the layout support placement of standard cells and offers reduction congestion while routing. However, unoccupied space present after placement and routing increases the silicon cost during manufacturing of chip. Hence, this paper analyses the unoccupied space while floorplanning the modules in the layout. Figure 7 illustrates the proposed methodology for placement of modules with reduction of unoccupied space. In this illustration, the pre-estimated with of voltage island $W_i$ is assumed as 8 units.

Consider the three modules $m_i$(3,8), $m_j$(4,4), and $n_i$(1,3). Figure 7a–d shows the possible placement of modules. Figure 7a shows the placement of module $n_i$ over the module $m_i$. Even though this placement fits inside the width $W_i$ with total occupied area of 63 square units, it increases the unoccupied space. The Figure 7b shows a placement when $n_i$ is vertically placed with respect to module $m_i$. This further increases the unoccupied space compared with placement method in Figure 7a with occupied area of 64 square units. The floorplan in Figure 7c also depicts a notable unoccupied space with placement of module $n_i$ adjacent to module $m_i$ and the module $m_j$ on top it. The total occupied area of module including unoccupied space is 56 square units. Figure 7d show the compact floorplan with reduction in occupied area of 48 square units; this floorplan reduces the silicon cost through allocating space for the placement of the new module after $m_j$. Hence, a unoccupied space analysis is performed in this paper before placement of every module inside voltage island to aid the process in post-floorplanning stages.

In ordered to obtain optimal reduction in wirelength, congestion and power, a cost function is developed in this paper. Every candidate floorplan is evaluated to the cost function given below in Equation (8), where P denotes power in mW, WL denotes wirelength in um and congestion in percentage,

$$Cost\left(F\right)=WL+C+P$$

(8)

To obtain an optimized floorplan, iterative improvement methodology is incorporated in this paper. For every iteration, we alter the positions of node inside the voltage of SKB tree representation. Then, the proposed methodology is implemented on the tree structure which results in optimal dimensions. Based on this optimal dimension, the floorplan is evaluated for reduction in unoccupied space. The conventional physical design flow given in Figure 2 is followed to obtain the total power, wirelength and congestion. This procedure is repeated until the cost function is minimized.

4. Simulation Results

This section presents four experimental results for fixed-outline floorplanning and voltage island floorplanning using proposed methodology. The proposed methodology was implemented using Cadence Innovus system for 45 nm technology. To prove the efficiency proposed methodology, IWLS benchmark circuits with high logically density are chosen. For better comparison, simulations were performed both proposed algorithm and conventional SKB floorplanning.

Table 2. IWLS Benchmark circuit description.

# Circuit	# Function	# Sequential	# inverter	# Buffer	# Logic	# Total
$AES\_core$	AES cipher	530	5589	274	14,402	20,795
$DMA\_core$	DMA Controller	2192	2678	253	13,995	19,118
$RISC\_core$	RISC CPU	7599	7370	126	44,872	59,974
$256tapFIRfilter$	FIR fliter	2520	1789	76	11,175	15,500

details the logical structures of each data set in IWLS benchmarks. The number of blocks in these circuits ranges from 15 to 28, and the number of nets ranges from 19,000 to 60,000, approximately.

4.1. Comparison of Wirelength With Existing Fixed Outline Floorplanners for Zero Deadspace

In this experiment, the proposed floorplanning methodology is implemented with zero dead space as fixed outline constraint. Before implementation of proposed methodology, we first study the performance of conventional SKB tree with results from academic benchmarks circuits towards reduction of wirelength to satisfy fixed outline constraint. The simulations are performed using the design flow given in Figure 8. The

Table 3. Comparison of other floorplanners for fixed outline floorplanning.

Circuit	#blocks/#nets	Parquet [34]	PATOMA [35]	SAFFOA [36]	SKB [31]	Circuit	SKB	Proposed
n30	30/349	166,336	156,921	138,218	102,579	AES_core (n30/1102)	595,000	500,000
n50	50/485	189,121	180,115	165,366	129,916	DMA_core (n50/4174)	910,000	861,000
n10	10/118	50,690	5228	46,207	36,175	256 tap FIR (n10/666)	119,576	96,457
						RISC_core (n18/9756)	484,300	318,200
Average WL ratio		1.51	1.44	1.3	1	Average WL ratio	1.187	1

show comparison results of Analytical floorplanning (A-FP) [33], Parquet 4.0 [34], Partitioning to optimize module arrangement (PATOMA) [35], Simulated Annealing based Fixed-outline Floorplanner with the Optimal Area (SAFFOA) [36] and SKB-tree [31] using GSRC benchmarks with average reduction in wirelength of 41.96%. The results show that SKB tree performs better compared to existing floorplanners. After implementation of conventional SKB tree in EDA environment for circuit netlist of IWLS benchmarks, the results shows that proposed floorplanning methodology gives 18% of reduction in wirelength to satisfy the fixed outline constraint. Even though performance of conventional SKB tree is better with academic benchmarks, results from EDA environment considers placement of standard cells and it requires more routing resources. This increases the total wirelength due to more number of nets. However, simulation results show that proposed methodology gives better results even with this increase in number of nets.

4.2. Comparisons with Conventional Floorplanner for Fixed Outline Floorplanning with 15% Deadspace on Various Aspect Ratios of Chips

This subsection presents experimental results of proposed method for fixed-outline floorplanning with 15% allowable deadspace on aspect ratios 1:1, 2:1, and 3:1 and the

Table 4. Comparisons with conventional floorplanner for fixed outline floorplanning with 15% deadspace on various aspect ratios of chips.

Circuit	#VI	1:1 Aspect Ratio				2:1 Aspect Ratio				3:1 Aspect Ratio
		SKB		Proposed		SKB		Proposed		SKB		Proposed
		WL(um)	Cong.%	WL(um)	Cong.%	WL(um)	Cong.%	WL(um)	Cong.%	WL(um)	Cong.%	WL(um)	Cong.%
AES_core	1	595,000	3.245	547,000	2.253	495,000	5.9	390,000	4.431	375,000	8.52	347,000	9.305
	2	558,000	4.065	500,000	3.416	582,000	7.266	429,000	5.124	582,000	12.29	456,000	8.945
DMA_core	1	872,000	2.195	861,000	2.101	982,000	2.75	912,000	2.422	1,982,000	3.039	1,021,000	2.047
	2	910,000	3.825	813,000	2.407	790,000	3.331	578,000	2.921	900,000	5.881	546,000	5.329
256 tap FIR	1	975,499	0.712	964,570	0.45	950,900	0.85	878,340	0.883	1,015,100	1.67	996,210	1.485
	2	915,766	0.536	535,860	0.268	882,000	2.8	643,760	1.748	1,003,100	3.68	822,780	2.591
RISC_core	1	784,436	2.001	457,610	1.187	798,321	7.518	483,863	6.223	882,750	10.284	545,012	9.747
	2	545,660	4.784	446,073	2.653	586,538	7.92	398,593	7.786	660,800	12.785	545,068	10.863
Average ratio		1.201	1.302	1	1	1.28	1.17	1	1	1.401	1.133	1	1

shows simulation results. In this experiment, in addition to wirelength, the percentage of congestion in the layout was measured on these aspect ratios. From the Table 4, it is evident that compared with existing SKB floorplanning technique, our proposed method reduces wirelength by 20%, 28%, and 40% when the aspect ratios of the chips are 1:1, 2:1, and 3:1 respectively. For congestion, the proposed methodology can reduce 30%, 17%, and 13% for the layout with aspect ratios 1:1, 2:1, and 3:1. This reduction in wirelength is mainly due to the iterative positioning of blocks in the layout using the proposed method for determining its optimal dimension and reducing unoccupied space. The Figure 9 and Figure 10 shows the layout of $AES\_core$, $RISC\_core$, and 256 tap FIR filter after proposed algorithm under various aspect ratio.

4.3. Comparisons with Existing Works for Voltage Island Floorplanning

The third set of experiments deals with floorplanning to satisfy, voltage island floorplanning. As in the Section 4.1, we first study the results of various existing methodologies in the literature addressing this problem and the results are tabulated in

Table 5. Comparisons with previous works for Voltage island floorplanning.

Circuit /Nets	#VI	Voltage Island Driven Floorplanning [28]		SKB		Circuit /Nets	#VI	Conventional SKB		Proposed
		Power (mW)	Power Saving %	Power (mW)	Power Saving %			Power (mW)	Power Saving %	Power (mW)	Power Saving %
n30/349	1	469,330	0	469,330	0	AES_core /(n30/1102)	1	3.79	0	3.13	0
	2	312,071	33.51	312,071	33.51		2	3.29	13.19	2.12	32.33
n50/485	1	446,803	0	446,803	0	DMA_core /(n50/4174)	1	7.26	0	6.17	0
	2	265,290	40.62	263,633	40.99		2	6.705	7.71	4.86	21.25
n10/118	1	498,778	0	498,778	0	256 tap FIR /(n10/666)	1	4.37	0	3.23	0
	2	393,660	21.08	352,637	29.3		2	3.36	23.11	2.233	30.86
						RISC_core /(n18/9756)	1	4.776	0	2.375	0
							2	3.975	16.77	1.924	18.98
Average ratio		1.25	0.98	1	1	Average ratio		1.387		1

. The columns (3–6) in this table shows the results of voltage island floorplanning approach and conventional SKB tree techniques with one and two voltage island designs performed on GSRC benchmark circuits. In the Table 5, the columns (9–12) presents the results after implementation of exiting SKB floorplanning and proposed method on IWLS benchmarks. The experiments performed using GSRC benchmarks selects the operating voltage of modules in the floorplan from a set 1.5, 1.3, 1.2, 1.1, 1.0 V randomly, where 1.5 V is the chip level voltage. However, since the proposed methodology is a technology dependent netlist, the best operating voltage is found using the method described in [19]. Thus voltage assignment is performed for the modules in the layout. In the Table 5, column 9 refers to the number of voltage islands. Here VI = 1 refers to operating voltage of 1.1 V for the whole circuit, and VI = 2 refers to two voltage island in the layout, where voltage domain one is operating at 1.1 V while voltage domain two at 0.9 V, considering a chip voltage of 1.1 V. Since most of the ICs used for various applications operates with only two voltage islands, the experiments were performed for only to two voltage, even though an increase in the number of voltage islands will show significant power reduction. The Figure 11 show the skeleton of the common power format used in Cadence Innovus tool to declare the power domains. In the Table 5, power saving % denotes the amount of power reduction due to the increase in voltage island. The results show that voltage island floorplanning consumes 25% power more than conventional SKB tree method while SKB tree gives 98% of power saving. This high percentage of power saving is mainly due to voltage assignment to the modules in the layout and better reduction in wirelength. After implementation in industrial EDA tool the results in the columns (9–12) shows that conventional SKB method consumes 38.7% percentage of power with the proposed method comparatively. Also, the proposed method better power saving with increase in voltage island compared conventional SKB floorplanning. This is due to the application of dynamic programming during voltage assignment to the modules and conditional floorplanning of modules which results in the reduction of wirelength.

4.4. Simultaneous Voltage Island and Fixed-Outline Floorplanning

In this fourth set of experiment, the proposed algorithm is performed for fixed-outline floorplanning with 2:1 and 3:1 aspect ratios of the chip while satisfying the voltage island floorplanning constraint simultaneously. The

Table 6. Comparison of power for simultaneous fixed outline floorplanning and voltage island floorplanning with conventional SKB floorplanning.

Circuit /Nets	#VI	2:1 Aspect Ratio		3:1 Aspect Ratio
		Conventional SKB	Proposed	Conventional SKB	Proposed
AES_core (n30/1102)	1	4.97	2.97	5.13	3.59
	2	4.23	2.58	4.027	2.75
DMA_core (n50/4174)	1	6.21	6.138	9.21	8.762
	2	4.86	5.3	5.986	6.86
256 tap FIR filter (n10/666)	1	3.19	2.278	3.37	2.556
	2	3.13	2.229	3.18	2.114
RISC_core (n18/9756)	1	3.573	2.466	4.124	3.46
	2	3.368	2.465	3.787	2.759
Average ratio		1.22	1	1.146	1

shows the simulation results of IWLS benchmarks both conventional SKB tree and the proposed algorithm. The voltage assignment is performed to the modules in the layouts as in [19]. As mentioned in previous Section 4.3, the layout has 1.1 V as chip level voltage and 0.9 V and 1.1 V for two power domains. Common power format (CPF) file is written based on the voltage assignment and simulations were performed as given in the design flow shown in the Figure 11 for 15% deadspace. For 2:1 aspect ratio, the proposed algorithm provides reduces 22% of power consumption and increases the percentage of power saving compared with conventional SKB tree method. Similarly, the simulations results for 3:1 aspect ratio, reveals that the proposed algorithm reduces the power by 14% compared with conventional SKB tree methodology.

5. Conclusions

In this paper, a new paradigm has been presented for industrial floorplanning to satisfy both fixed outline and voltage island constraint. Since the proposed methodology shows better results towards power saving and reducing wirelength, the experiment is extended for simultaneous optimization of both constraints. The experimental results demonstrates that the proposed algorithm in this paper is effective in solving industrial floorplanning under various fixed outline and voltage island conditions.

For future SOCs designs, three-dimensional structures are preferred due to its ability to place these two-dimensional layouts in stack-based structures and more integration of modules in the chip. Since fixed outline and voltage island floorplanning is challenging problem, there exist few works considering this issue. The proposed methodology requires dedicated voltage assignment and floorplanning, which will be considered as future work.