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Article

Multi-Port Current Source Inverter for Smart Microgrid Applications: A Cyber Physical Paradigm

by
Karthikrajan Senthilnathan
and
Iyswarya Annapoorani
*
School of Electrical Engineering, Vellore Institute of Technology, Chennai 600127, India
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(1), 1; https://doi.org/10.3390/electronics8010001
Submission received: 19 October 2018 / Revised: 29 November 2018 / Accepted: 10 December 2018 / Published: 20 December 2018
(This article belongs to the Special Issue Cyber-Physical Systems)

Abstract

:
This paper presents a configuration of dual output single-phase current source inverter with six-switches for microgrid applications. The inverter is capable of delivering power to two independent set of loads of equal voltages or different voltages at the load end. The control strategy is based on integral sliding mode control (ISMC). The cyber twin model-based test bench is developed to analyze the performance of the inverter. The cyber twin is a virtual model of the physical system to simulate behaviours. The performance of the inverter is analyzed with a cyber twin model and monitored through the remote system. Also, the inverter is analyzed with different voltage conditions.

1. Introduction

The distributed generation (DG) with photovoltaic, wind energy, fuel cell, and battery, termed as microgrid, can supply for low- and medium-voltage applications. The DC microgrid is capable of supplying both DC loads and AC loads with the inverter. The inverters for microgrid discussed in [1,2] are capable of supplying a single output. The inverters with reduced semiconductor switches and dual output are capable of feeding dual loads and less complexity in implementation. This enables the feeding of different types of loads using an inverter. The development of inverter with reduced power semiconductor devices makes the system economical and compact. The dual output inverters reduce the number of switches in a system and supplies energy to two AC autonomous loads. A four-switch inverter [3] is initially proposed with the reduced number of switches by replacing split capacitors for sharing between power converters. The dual output voltage source inverters discussed by Yu, Strake et al. [4] are dual phase single DC bus inverter with four-switches, three wire single-phase inverter with six-switches, dual phase dual DC bus inverter with four-switch, dual phase with four-switch and transformer. The inverter models discussed in [4] has the capability of operating only in half bridge configuration. The dual output single-phase inverter based on voltage source inverters (VSI) is proposed by Fatemi, et al. [5] explains about the half-bridge dual output inverter with the split capacitor as a sharing leg for both outputs and for the full bridge dual output with six-switches; the switch leg is common of for both outputs by sharing a row of switches for upper and lower outputs. The six-switch voltage source inverter delivers equal voltage at the output with open loop operation. The six-switch dual output with buck structure delivers dual output with the equal voltage at both output and operated in open loop is presented by Nguyen, et al. [6]. The dual output inverter with sharing of switch legs will results in the reduction of semiconductor switches by 25 % .
From the literature, most of the researchers concentrate on dual output voltage source inverter rather than the dual output current source inverter. The current source inverters (CSI) have inherent short circuit protection owing to the presence of a dc link reactor which results in the low harmonic distortion and better load voltage regulations [7,8]. The control of CSI is difficult compared to VSI due to the simultaneous regulation of DC link current and output voltage. The dynamic response of CSI is studied using a current controller [9] and continuous time-based control strategy is employed [10]. The sliding mode control (SMC) [8,11,12] provides a dynamic response to the nonlinear systems with the property of hysteresis. It offers stability to variations in system parameters and easy implementations. The sliding surface is created with reference to error variable of inductor current and capacitor voltage for single-phase single output CSI is proposed by Komurcugil, et al. [13]. The sliding mode control for voltage source inverter-based shunt active filter is presented in [14] for power quality improvements in the power system. The control of y source boost DC–DC converter controlled by cascaded sliding mode control is proposed by Ahmadzadeh et al. [15]. The control of power electronics equipment using sliding mode control is presented in the various literature for multi-terminal HVDC [16], induction motor control [17], h6 inverter [18], and modular multilevel converter [19]. The SMC [20] based control strategies are applied widely to single output inverters [1,2] rather than dual output inverters from the literature. To implement continuous time-based control strategies processors with high-speed data processing is required. Reconfigurable Input/Output (RIO) based processors are utilized effectively for these types of controllers [21].
The interfacing of the power electronics circuits to the smart environment [22,23] makes the system more efficient and controllable. This provides two-way communication between the target and the users (man to machine and vice versa) and results in cyber–physical systems (CPS) [24]. The CPS implementation will result in smart grids [25,26,27] and remote laboratories for educational purposes. The definition of CPS given by E.A. Lee [28] is that the integration of physical process with embedded computation, controlling and network monitoring along with the feedback loops for computations. In another way, CPS is defined as a controllable, credible and scalable network with the physical system. The CPS is stated as 3 C s (Computations, Communications, and Control). The basic concepts, method, and implementation of CPS is explained briefly by Liu, et al. [29]. CPS implementation for conveyor belt block pickup with application and platform level reconfiguration is in case of faults is presented by Andalam, et al. [30]. The CPS-based optimal power flow management in electric grid with energy demand management is proposed by Nguyen, et al. [31]. The remote monitoring of microgrid using LabVIEW and PLC has proposed in [32]. The researchers developed various CPS models for the physical systems with the utilization of wireless sensor network (WSN), radio frequency identification (RFID), Zigbee, CAN protocols [33,34,35,36,37]. The WSN can only sense signal but not capable of identifying the specific one from more sensors. Similarly, RFID also senses the data based on the perception of data. RFID is widely used in the Internet-of-Things (IoT). While IoT only has the perception of sensing alone, but CPS has the ability of the robust control to the target. The comparison of CPS for various applications is given in Table 1.
As the growth in the CPS, the cyber twin (digital twin) [38] approach is introduced to realize the behaviour of the physical system with a virtual model. In the cyber twin approach, a virtual model realizes the behaviour of the physical system to predict the dynamic changes and respond to the system for better operation. The cyber twin approach has been proposed by various researchers; Kazi et al. [39] proposed fuzzy-based vehicle CPS system for driving assistance. To increase the feasibility in furniture production line Hao Zhang et al. [40] introduced the cyber twin approach. The comparison of cyber twin and big data for Industry 4.0 is anticipated by Qinglin et al. [41] to identify the possibilities and advantages of cyber twin for Industry 4.0.
In this paper, the modeling of dual output current source inverter with the capability of operating in equal voltage and different voltage modes at the output end for microgrid applications. The sliding mode control (SMC) strategies are introduced to control the dual output inverter and performance analysis of sliding mode and integral sliding mode control (ISMC) is performed. The comparative analysis of SMC and ISMC reveal the performance and better controller for a dual output current source inverter. The main advantages of ISMC are robustness of large variations, stability, and fast dynamic response. The integration of power electronics devices and cyber–physical systems (CPS) is introduced. The cyber twin model of the inverter is developed with LabVIEW and Multisim packages. The cyber twin model is the virtual model of the physical system; it operates by sensing the raw data for the analysis and control of the physical system. The cyber–physical test bench is developed with cyber twin model of the inverter. In literature for implementing cyber–physical test bench utilizing multidomain programming is given in Table 1. To avoid the complexity by utilizing the multidomain program, LabVIEW based single domain programming is used. The integration of this heterogeneous frame is needed to deploy on the single platform to reduce the data exchange error which occurs while using a different platform for each section. The cyber–physical test bench is developed based on LabVIEW, MyRIO, C-DAQ and NI-Web services. The interaction of cyber twin model by cyber integration layer with the physical device is needed for effective control of the system. The performance of the physical device is monitored by web services.

2. A Cyber Perspective Model

The Reconfigurable Input/Output (RIO)-based design of cyber–physical system RCP evaluation test bench is created for the evaluation of two switch dual output inverter with ISMC control. The experimental setup consists of three sections Physical layer, cyber–physical integration layer, and cyber layer. The CPS architecture consists of three layers: Physical layer, cyber–physical integration layer, and Cyber layer. Physical layer comprises of the physical device (target) which needs to be controlled and monitored by CPS. The cyber–physical integration layer has the sensors, controllers and software technologies with a host computer to collect the data from the physical device and to control the device based on the responses. In this layer the integration of cyber twin with physical model is initiated.
Cyber twin approach for power electronics systems is introduced and with cyber infrastructure. The virtual model of the physical model is developed to simulate the real behaviour and analyze the system. The Figure 1 displays the block diagram of the proposed cyber twin approach. The virtual model is developed in LabVIEW-Multisim packages. The physical device (inverter) voltage and current are sensed through data acquisition and analyzed with the virtual model in the host computer.
The data observed from this layer is monitored and the physical device is controlled by the control center through the internet. The data transfer between the physical device and control center is executed by cyber layer. Figure 2 shows the configuration of the proposed RCP evaluation of the inverter.

Generalised CPS Model

The physical layer consists of the devices which are needed to monitor and control through CPS. Here the physical layer considered is inverter prototype with source and load. The generalised physical model is represented by Mulit-Input-Multi-Output (MIMO),
x ˙ ( t ) = A x ( t ) + B u ( t )
Y ( t ) = C x ( t )
where, A is the system matrix, B is the input matrix, C is the output matrix, x(t) is the state vector, u ( t ) is the control vector, Y ( t ) is the observation vector.cyber–physical integration layer makes the interconnection between the physical layer and cyber layer. The devices which employed for integration are voltage/current sensor, driver circuits with an optocoupler, data acquisition system, and host computer. The control structure is given by,
u ( t ) = K x ( t )
where, K R n c x n s is the connection structure between controller and sensor. K i j is non zero and shows the connection between controller ( i c ) and sensor (j). The system with closed loop is given by,
x ˙ ( t ) = A ˜ x ( t )
Closed loop matrix ( A ˜ ) = A B K
The dynamics of the system with delay between sensor and controller is represented by,
x ˙ ( t ) A ˜ x ( t )
Matrix with delay ( A ˜ ) = ( I B D i c j K ) ( A + B K )
Delay Matrix D i c j = 1 if j & i c are conncected 0 if j & i c are not conncected
The switching function of the system is given by,
x ˙ = A n x + B n u ; t n 1 t < t n
To design the controller with the capabilities of cyber twin, the Sliding Mode Control (SMC) is identified due to modelling of control strategy based on mathematical model of the system.

3. Physical Layer: Dual Output Current Source Inverter

The microgrid schematic with proposed dual output inverter is shown in Figure 3. The proposed inverter is compared with the family of dual output inverters and given in Table 2. The configuration of the proposed dual output current source inverter is shown in Figure 2.
It consists of a DC link reactor with six semiconductor switches. The inverter has two legs with three semiconductor switches and a sharing row of switches for upper and lower output. The inverter is capable of operating at equal voltages (EV) and different voltages (DV).

3.1. Equal Voltage (EV) Mode of Operation

In this mode, the two AC outputs voltages are independent and equal. The inverter works similar to a full bridge with two parallel loads. The gate signals for upper ( S 1 , S 4 ) and lower ( S 3 , S 6 ) switches are generated by the control strategy. The control signals for sharing switches ( S 2 , S 5 ) is generated by the logical XOR of the upper and lower signals. The instantaneous output voltage ( v o n ) of the dual output inverter are same when it operates at EV mode is expressed in (10).
v o n = v o U = v o L = n = 1 , 3 , 5 4 V D C n π s i n ( n ω t )

3.2. Different Voltage (DV) Mode of Operation

In this operating condition, the inverter is capable of delivering different voltage magnitude. The upper side will act as a full bridge and lower will act as a half bridge. The DV mode is in existence due to the presence of a DC link reactor. It will protect the inverter from short circuit and floating modes. If the inverter is operated at different voltage mode, the upper side voltage ( v o U ) will be in full bridge mode as expressed in Equation (11) and the lower side ( v o L ) will be in half bridge mode. The output equations for the half bridge are given by (11).
v o U = n = 1 , 3 , 5 4 V D C n π s i n ( n ω t ) , v o L = n = 1 , 3 , 5 2 V D C n π s i n ( n ω t )

3.3. System Modelling

The dual output inverter is modeled based on CSI topology. It comprises the source voltage ( V S ), a DC link reactor (L), IGBT switches, output capacitive filter (C) and a resistive load (R). The equation of the CSI is written as,
L d i D C d t + r i D C = V S V D C
C d v o d t = i o v o R
where, u is the switching function, V D C = u v o is the input DC voltage, i o = u i D C is the output AC current, and r i d c the internal resistance of DC link reactor. In order to reduce the computational parameters of dual output inverter, it is assumed that C = C 1 f = C 2 f as dual output capacitive filter and v o = v o U = v o L as the dual output voltage. The state space for the system operation is described in matrix form is given by (14),
v o ˙ i o ˙ = r i d c / L 1 / L 1 / C 1 / R C v o i o + 1 / L 0 u + 0 1 v o i o
The transfer function for the system operation is represented in (15),
G ( s ) = 1 L C S 2 S L + R C ( r i d c ) R C L + ( r i d c R C L ) L C + R C L R C 2 L 2

4. Cyber–Physical Integration Layer: Cyber Twin Model, C-DAQ, RIO with Sliding Mode Controllers

Cyber–physical integration layer in a CPS incorporates the algorithm to gather sensor information and issue control signals through actuators to the physical device. This layer has software and hardware coordination in-order to control and monitor the physical device. The cyber twin model of the inverter is developed for the integration with the physical device. The CPS should behave as, (A) Intelligent: To predict and understand the behaviour of the system using LabVIEW environment, (B) Real-Time: To gather the real-time data from physical device C-DAQ-9174 is utilised, (C) Adaptive & Predictive control: To respond and anticipate the changes in the physical systems the ISMC based control strategy is implemented in MyRIO-1900.

4.1. Sliding Mode Control (SMC)

The Sliding Mode Control (SMC) is an effective controller with switching nature of inverter derived from the system model. The advantages of SMC are, it has a better dynamic response, stability against the variations of the load and easy implementation. It consists of inner and outer control loops. The input inductor current and output capacitor voltage is considered as the state variables for controlling. The error variables are given by,
Error Variables = x 1 = i D C I D C x 2 = V o V r e f
The sliding surface (S) of SMC is expressed by (17),
S = α 1 x 1 + α 2 x 2
where, α 1 and α 2 are the sliding coefficients. The additional variable x 3 accumulates directly to the steady-state errors of x 1 and x 2 . The time derivative of (17) is,
S ˙ = α 1 x 1 ˙ + α 2 x 2 ˙
The derivatives of x 1 and x 2 is given by (19) and (20),
x 1 ˙ = 1 L V s r i d c i D C u v o d I D C d t
x 2 ˙ = 1 C u i D C v o R d V r e f d t
By substituting (19) and (20) in time derivative Equation (18) gives (21),
S ˙ = u α 1 L α 2 R C v o + α 1 r i d c L + α 2 u C i D C + A
where A is given by (22),
A = α 1 V s L d I D C α 1 d t α 2 d V r e f d t
The condition for stability S S ˙ < 0 should be satisfied and the control variable is given by,
u = s i g n u m ( S )
To satisfy the stability condition, u = 1 and u = 1 is incorporated to Equation (21).
i f , S < 0 S ˙ > 0 u = 1
( S < 0 ) ( S ˙ > 0 ) α 1 L α 2 R C v o + α 1 r i d c L + α 2 C i D C + A > 0
i f , S > 0 S ˙ < 0 u = 1
( S > 0 ) ( S ˙ < 0 ) α 1 L α 2 R C v o + α 1 r i d c L α 2 C i D C + A < 0
From Equations (24) and (25) the simplified condition for stability is given by (26),
0 < α 1 C + α 2 L R v o + α 2 L + α 1 r i d c C i D C L C A < 2 α 2 L i D C α 1 C v o
The equivalent continuous control variable u e q is given by (27),
u e q = L C v o C α 1 α 2 L α 2 v o R C i D C α 1 r i d c L + A
The u e q maintains the error variables of the systems. The problem with u e q is complicated while implementing in analog controllers. For the easy implementation of sliding mode control instead of direct implementation of u e q , the switching relay function is used. The switch relay function is given by (28),
u e q = sign ( S ) = + 1 i f S < 0 1 i f S > 0
The switching function is realized by signum function and direct implementation of this function results in uncontrolled switching frequency and no steady-state errors. Operating of CSI in this condition leads to system failure in practical conditions. To operate CSI with limited frequency and controllable, hysteresis band with boundary layer is utilized. The hysteresis band is implemented instead of signum function and the function is given by (29),
u = + 1 i f S < h 1 i f S > h
The hysteresis bandwidth in S is used to control the dual output CSI with switching frequency, inductor current, and capacitor voltage. If S = 0, CSI cannot be controlled. To control dual output CSI, the switching should lie in S = ± h . The performance plot for both inductor current and capacitor output voltage is given in Figure 4a,b. The parameters considered are L = 10 mH, C = 20 μ F, R = 50 Ω , α 1 = 0.0002 , α 2 = 0.2 and α 3 = 50 and are simulated with Matlab.

4.2. Integral Sliding Mode Control (ISMC)

The SMC-based control has steady-state errors in both capacitor output voltage and inductor current. It is observed from Figure 4b, that the capacitor output voltage is not tracked with the reference voltage and has a steady-state error of 10%. The steady-state error of the inductor current is about 5% as observed from Figure 4a. As a method to suppress the steady-state error of the inductor current and output voltage, an additional integral term of the state variables x 1 and x 2 are introduced to the sliding surface. The additional integral term of error variable is introduced into SMC as an additional control variable and stated as an integral sliding mode controller (ISMC). The additional variable x 3 is considered and it is obtained by integrating the state variables x 1 and x 2 is given by (16),
Error Variable = x 3 = ( x 1 + x 2 ) d t
The sliding surface (S) of ISMC is expressed by (31),
S = α 1 x 1 + α 2 x 2 + α 3 x 3
where, α 1 , α 2 and α 3 are the sliding coefficients. The additional variable x 3 accumulates directly to the steady-state errors of x 1 and x 2 . The time derivative of (31) is,
S ˙ = α 1 x 1 ˙ + α 2 x 2 ˙ + α 3 x 3 ˙
x 3 ˙ = x 1 + x 2
The derivatives of x 1 , x 2 and x 3 is given by (34)–(36),
x 1 ˙ = 1 L V s r i d c i D C u v o d I D C d t
x 2 ˙ = 1 C u i D C v o R d V r e f d t
x 3 ˙ = i D C I D C + v o V r e f
By substituting (34)–(36) in time derivative Equation (32) gives (37),
S ˙ = u α 1 L α 2 R C + α 3 v o + α 1 r i d c L + α 2 u C + α 3 i D C + B
where B is given by (38),
B = α 1 V s L d I D C α 1 d t α 2 d V r e f d t α 3 I D C α 3 V r e f
The condition for stability S S ˙ < 0 should be satisfied and the control variable is given by,
u = s i g n u m ( S )
To satisfy the stability condition, u = 1 and u = 1 is incorporated to Equation (38).
i f , S < 0 S ˙ > 0 u = 1
( S < 0 ) ( S ˙ > 0 ) = α 1 L α 2 R C + α 3 v o + α 1 r i d c L + α 2 C + α 3 i D C + B > 0
i f , S > 0 S ˙ < 0 u = 1
( S > 0 ) ( S ˙ < 0 ) = α 1 L α 2 R C + α 3 v o + α 1 r i d c L α 2 C + α 3 i D C + B < 0
From Equations (40) and (41) the simplified condition for stability is given by (42),
0 < α 1 C + α 2 L R α 3 L C v o + α 3 L C + α 2 L + α 1 r i d c C i D C L C B < 2 α 2 L i D C α 1 C v o
The equivalent continuous control variable u e q is given by (43),
u e q = L C v o C α 1 α 2 L α 2 v o R C + v o α 3 i D C α 1 r i d c L + i D C α 3 + B
The information about the sliding mode is given by (42). In the proposed ISMC, the condition for stability in (42) is tested by the numerical computations of the sliding coefficients ( α 1 , α 2 and α 3 ). The stability is tested along with i D C and v o minimum and maximum values, and from (42) Equation (44) can be obtained based on the numerical computations.
2 α 2 L i D C α 1 C v o > 0
Due to the stability requirement the sliding coefficients ( α 1 , α 2 and α 3 ) will be positive. In steady-state condition i D C = I D C . The condition for v o is given by,
α 2 α 1 > C v o L i D C
The sliding coefficient ( α 3 ) will be determined regardless of ( α 1 and α 2 ) by fine-tuning to obtain the desired response. The block diagram for ISMC is shown in Figure 2. The switching function is defined by the hysteresis (h) block in the controller design. The hysteresis switching function has three levels ( 1 , 0 , + 1 ). Hysteresis band is fixed based on the reference output voltage ( v o ). In general, the hysteresis band (h) will be fixed between 5–10%. The instantaneous hysteresis band is calculated based on the frequency (f) and expressed as (46),
Hysteresis band = 1 8 f L V D C 4 v o 2 V D C
In three-level hysteresis, for + v e operation voltage is + V D C when error reaches the lower hysteresis band ( h l o w e r , h ) and ‘0’ when reaches lower then ‘ h ’. For v e operation voltage is V D C when error reaches the upper hysteresis band ( h u p p e r , + h ) and ‘0’ when reaches higher than ‘+h’. In two-level hysteresis, the no existence of dead band ( t d ) due to the direct transition of + v e to v e The excursion of sliding surface (S) beyond the hysteresis band (h) results in a dead band ( t d ) for semiconductor switches. In three-level hysteresis, the ‘0’ level existence will result in the dead time for semiconductor switches and has less distortion in output voltage. The switching frequency ( f s w ) for three-level hysteresis function [11] is calculated based on (47),
f s w = ω o 2 V D C h + t d ω o 2 V D C 2 π m 1 2 m 2
where, ω o = 2 π f , f is the line frequency, m is the amplitude of disturbance. The instantaneous switching frequency ( f i n ) is based on the transition between h u p p e r to h l o w e r . The average switching frequency is calculated with the dead-band of 3 μ s and hysteresis width of 0.05 V μ s resulted in the average switching frequency of 2.9 kHz and the line frequency is 50 Hz. The switching function for the inverter model shown in Figure 2 is given by (48),
u 1 , 2 = + 1 i f S < h 0 i f S > 0 u 4 , 5 = 1 i f S > + h 0 i f S < 0 u 2 , 3 = + 1 i f S < h 0 i f S > 0 u 5 , 6 = 1 i f S > + h 0 i f S < 0
The sliding surface (S) is the input to the Schmitt trigger (hysteresis switching). The schmitt trigger is designed to operate as per the switching conditions (48) for generating control signals. The ISMC respond better than SMC and minimized the steady-state errors. The ISMC based control strategy is implemented for the dual output single-phase inverter. The controller is designed in reconfigurable input/output (RIO) processor. The experimental test bench is created and the performance of the inverter with the ISMC is analyzed. The performance of the SMC and ISMC is analyzed and shown in Figure 4a,b. The inner current control is analyzed by fixing the reference of 5 A and changing the input signal of 6 A, 4.5 A, 1.5 A, and 6 A. It is inferred from Figure 4a, the settling time for SMC is 0.01 s with a steady-state error of 10% and ISMC has 0.05 s with tracking to reference and alleviates the steady-state error in the inductor current. From Figure 4, it is observed that the SMC has the high steady-state error compared to ISMC. For the outer voltage control loop analysis, the reference voltage is 120 V. It is inferred from Figure 4b, then the steady-state error of SMC is 10% and not tracking the reference voltage and ISMC alleviates the steady-state error in the voltage and settles at 0.005 s with oscillations. The control based on SMC has higher steady-state error compared to ISMC. The host computer with LabVIEW, C-DAQ, and MyRIO comprises a cyber–physical integration layer as shown in Figure 2.

4.3. Cyber Physical Test Bench

The LabVIEW is a graphical programming tool with seamless integration of hardware for both data acquisition and controlling physical devices. The source voltage ( V A B C ), source current ( i D C ), output voltage ( V o ), output current ( i o ) is sensed from the physical device using the NI C-DAQ 9174 with voltage (NI-9225) and current (NI-9227) sensor. The voltage and current data collected from the physical layer are processed in LabVIEW. The acquired signals are monitored in the front panel. the control algorithm for inverter based on ISMC is modeled and block diagram is shown in Figure 2.
The controller (actuator) is based on NI-1900 MyRIO (Reconfigurable Input/Output) which has Xilinx Zynq-7010 with a combination of Artix-7 FPGA processor, dual-core ARM Cortex-A9 real-time processor and, onboard WIFI. As an advantage of RIO architecture and WIFI, the physical equipment at a remote location is easily controlled. The terminals are reconfigurable as per the requirements. This leads this test bench to be utilized for all power electronics prototype testing. The control algorithm is programmed in NI-My RIO 1900 and connected to the physical device gate driver TI SM72295. The experimental setup is shown in Figure 5.

5. Cyber Layer—LabVIEW Based CPS

The combination of the physical layer and the cyber–physical layer is integrated into the cyber layer. The cyber layer has a host computer with server and monitoring station (control center). The data transmission and security is the major concern in the cyber layer. The traditional data transmission is not sufficient to transfer large data in CPS. In order to satisfy the needs, the CPS must have the inbuilt transmission systems. The MyRIO has inbuilt Wi-Fi for data exchange between the host and target. While considering the security of the connection, It utilizes the TCP protocol with SSL.x.509 secured layer to enhance the security. The host computer with LabVIEW has the web service management tool for creating the secured URL. The URL mapping is given by https://localhost:portaddress/webservice.html. The LabVIEW has the inbuilt server for the data exchange with a secured network. The collected data from the target is monitored and controlled through the web browser. This method has good live data support, good interaction between the client and user. The network monitoring and active devices monitoring across the network is tracked using the total network monitor. Figure 6 depicts the network map of the system.

6. Results and Discussions

The performance of the proposed dual output inverter with ISMC control strategy is tested and monitored through the CPS system. The analysis was performed under various test conditions like equal output voltage at both the upper and lower side, the different output voltage in upper and lower side and inverter analyzed with and without load variations. The control strategy is implemented using a reconfigurable input/output (RIO) processor. The hardware prototype is fabricated to demonstrate the proposed inverter. The prototype specifications are given in Table 3.

6.1. Steady State Performance

The steady-state performance of the dual output current source inverter is analyzed with an ISMC-based control strategy. The tracking performance of ISMC is discussed in Section 4.2 and performance the comparison of SMC with ISMC is plotted in Figure 4a,b. The IMSC alleviates the steady-state error and settles at 0.05 s. Figure 7 shows the performance of dual output inverter with ISMC.
The DC voltage ( V d c ) and current ( I d c ) are shown in Figure 7a. Due to the current source inverter configuration, the DC link inductor limits the sudden changes in the current and the distortion will get reduced. Figure 7b depicts the dual output voltage and current for 50 Hz operation at EV mode. The dual output current source inverter delivers 83 V at both loads ends ( V o U , V o L ) due to the DC link of 120 V. The upper load current ( I o U ) 3.60 A is observed and lower output current ( I o L ) is 2.65 A. The dual output CSI can deliver different voltages (DV mode). In this mode, the upper output voltage is similar to full bridge inverter and lower output voltage similar to a half bridge inverter.
Figure 7c shows the upper output voltage ( V o U ) as 83 V and lower voltage ( V o L ) as 38.4 V. The upper load current ( I o U ) observed is 3.80 A and lower load current ( I o L ) observed is 1.68 A. The inverter is operated at both EV and DV mode with ISMC.

6.2. Response to Load Variations

Figure 7d depicts the step change in both upper and lower load of the dual output current source inverter when it operates in EV mode. The inverter operates at 50 Hz, the output voltage of upper ( V o U ) and lower voltage ( V o L ) is 83 V. The IMSC has a robust response to the load variation and maintains the voltage at the desired level. Figure 7e,f represent the dual output current source inverter waveforms when a sudden step change in upper or lower load. Figure 7e shows the upper ( V o U ) and lower voltage ( V o L ) respectively. The change in upper load ( I o U ) and current observed is 1.24 A and lower load current ( I o L ) results in 597 mA and waveforms shows the change in load. From Figure 7f the EV mode operation with a step change in upper load is observed with 83 V in upper and lower. The load current is 1.24 A and 2.51 A respectively.
In Figure 7g, the performance of the inverter with ISMC is shown. The resultant waveform sohws the operation of the inverter at a different voltage (DV mode) with variations in load current. Figure 7g shows the upper voltage ( V o U ) 83 V and lower voltage ( V o L ) 38 V with variations in upper load current ( I o U ) and lower load current ( I o L ).
In Figure 7h, the performance of inverter in DV mode with a step change in upper load is analyzed and corresponding upper load current ( I o U ) is 269 mA. The lower load current ( I o L ) inferred is 1.22 A. The overall observations from Figure 7 shows that dual output current source inverter has the capability of supplying two independent loads of same (EV mode) and different voltage (DV mode). The dual output current source inverter has the capability of supplying two independent loads of equal (EV mode) and different voltage (DV mode). The dual output inverter can be used in renewable applications to simultaneously feed power to the grid and to the stand-alone load. In electric drive applications to operate two different machines of the same or different voltage level. The selection of DC link inductor should be concentrated more to obtain the maximum performance of the inverter. Gate pulse generation of the middle switches is critical due to dual operation.

6.3. Harmonic Analysis

The performance of the inverter is analyzed with a single-phase power quality analyzer (Fluke analyzer). The harmonic analysis is performed at EV and DV mode. The THD is tabulated in Table 4.
Figure 8 depicts the output voltage and current of the Inverter in EV mode. From Figure 8a, the upper voltage ( V o U ) and upper current ( I o U ) are observed. Figure 8b shows the lower voltage ( V o L ) and lower current ( I o L ). The total harmonic distortion (THD) of upper load voltage and current is observed from Figure 8. Figure 8c depicts the THD of upper voltage ( V o U ) is 4.7% and from Figure 8d it is observed that THD of upper current ( I o U ) is 4.4%. The total harmonic distortion (THD) of lower load voltage and current is observed from Figure 8. From Figure 8e the THD of lower voltage ( V o L ) observed is 5.3%. Figure 8f depicts the THD of lower current ( I o L ) is 4.3%. The THD observed from the results depicts that the THD is under the acceptable limit as per standards IEEE519-2014.
Figure 9 depicts the output voltage and current of the Inverter in DV mode. From Figure 9a the upper voltage ( V o U ) and upper current ( I o U ) is observed. Figure 9b shows the lower voltage ( V o L ) and lower current ( I o L ). The total harmonic distortion (THD) of upper load voltage and current is observed from Figure 9. Figure 9c depicts the THD of upper voltage ( V o U ) is 4.7% and from Figure 9d it is observed that THD of upper current ( I o U ) is 5.4%. The total harmonic distortion (THD) of lower load voltage and current is observed from Figure 9. From Figure 9e the THD of lower voltage ( V o L ) observed is 4.3%. Figure 9f depicts the THD of lower current ( I o L ) is 4.8%. The THD observed from the results depicts that the THD is under the acceptable limit as per standards IEEE519-2014.

6.4. Voltage Stress

The inverter model has six-switches S 1 to S 2 . The voltage stress of the switches calculated by the peak voltage across the collector and emitter terminals. The voltage stress V S w 1 6 is given by,
V S w 1 6 = V D C 2

6.5. Loss Analysis

The total power loss ( P l o s s ) of the IGBT is given by,
P l o s s = P O N H + P O N l + P S W
where, P O N H is the conduction loss of IGBT at high side, P O N L is the conduction loss of IGBT at low side, P S W is the switching loss of IGBT.

6.5.1. IGBT Conduction Loss

The conduction loss occurs when the IGBT or free wheeling diode is in ON state. The conduction loss on high side P O N H of the inverter is given by,
P O N H = I o 2 × R O N H × V o V D C
The conduction loss on low side P O N H is given by,
P O N L = I o 2 × R O N L × 1 V o V D C
where, the R O N H and R O N L is the resistance of IGBT for high and low side respectively.

6.5.2. IGBT Switching Loss

The power loss occurred during the transition and based on switching frequency. The switching loss P S W is calculated by,
P S W = 1 2 × V D C × I o × t r + t f × f s w
where, t r and t f is the high time and fall time of IGBT. f s w is the switching frequency.
The total loss compared to a conventional current source inverter (CSI) is tabulated in Table 5. The total loss calculated for two conventional inverters to deliver dual loads is 22.064 W and proposed dual output CSI has 16.548 W. The proposed dual output CSI has the ability to supply two aindependent loads with the reduced number of semiconductor switches.

6.6. Online Monitoring

The CPS design is implemented to evaluate the performance of CSI dual output inverter. The control and monitoring of the target device are done through the internet browser. The connection is based on TCP protocol and SSL.x.509 secured layer is used to ensure the webpage security.
From Figure 10 the online monitoring of dual output CSC inverter performance is displayed. The resilient cyber infrastructure designed using single domain has the advantage of lower transport delay and easy implementation compared to other methods. The network monitoring of server and client is monitored by Total Network Monitor as shown in Figure 6. The incorporation of CPS in the inverter model leads to the development of smart grids, smart manufacturing in industries for controlling inverters in drives and smart learning with decentralized control of multiple systems.

7. Conclusions

The dual output current source inverter topology operating in two different voltage modes is presented. A significant advantage of this topology is that it can supply power simultaneously to two different loads of equal (EV mode) and/or different (DV mode) voltages for microgrid applications. The control strategy based on sliding mode controllers is analyzed. The conventional sliding function has the steady-state error of 10% for voltage control and 5% for current control. To alleviate the steady-state error, an additional integral term is introduced and integral sliding mode control is derived for the dual output current source inverter. The cyber twin approach for the control of power electronics circuits is introduced and notable results are achieved. Reconfigurable Input/Output processors (MyRIO-1900) with cyber physical test bench is developed to implement continuous time-based control strategies, processors with high speed data processing is required. The development the cyber physical system for an inverter leads to the development of virtual laboratories and smart grids.

Author Contributions

Conceptualization, K.S. and I.A.; Methodology, K.S. and I.A.; Supervision, I.A.

Funding

This research received no external funding.

Acknowledgments

The authors like to thanks the smart grid laboratory, power electronics laboratory and advanced drives laboratory, School of Electrical Engineering, Vellore Institute of Technology(VIT), Chennai for carrying out this project.

Conflicts of Interest

The authors declare that they have no conflict of interest.

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Figure 1. Block diagram of cyber twin.
Figure 1. Block diagram of cyber twin.
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Figure 2. System Configuration.
Figure 2. System Configuration.
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Figure 3. Schematic of Mircogrid.
Figure 3. Schematic of Mircogrid.
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Figure 4. Performance comparision of SMC and ISMC: (a) Input current, (b) Output Voltage.
Figure 4. Performance comparision of SMC and ISMC: (a) Input current, (b) Output Voltage.
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Figure 5. Experimental Setup.
Figure 5. Experimental Setup.
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Figure 6. Network Monitor.
Figure 6. Network Monitor.
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Figure 7. Prototype Results: (a) DC voltage and current, (b) EV mode output voltage and load current, (c) DV mode output voltage and load current, (d) EV mode output voltage and load current with step change, (e) EV mode output voltage and load current with step change in lower load, (f) EV mode output voltage and load current with step changes in upper load, (g) DV mode output voltage and load current with step changes in load, (h) DV mode output voltage and load current with step change in upper load.
Figure 7. Prototype Results: (a) DC voltage and current, (b) EV mode output voltage and load current, (c) DV mode output voltage and load current, (d) EV mode output voltage and load current with step change, (e) EV mode output voltage and load current with step change in lower load, (f) EV mode output voltage and load current with step changes in upper load, (g) DV mode output voltage and load current with step changes in load, (h) DV mode output voltage and load current with step change in upper load.
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Figure 8. Prototype Results: (a) Upper output voltage and load current, (b) Lower output voltage and load current, (c) Upper output voltage THD, (d) Lower output voltage THD, (e) Upper Current THD, (f) Lower Current THD.
Figure 8. Prototype Results: (a) Upper output voltage and load current, (b) Lower output voltage and load current, (c) Upper output voltage THD, (d) Lower output voltage THD, (e) Upper Current THD, (f) Lower Current THD.
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Figure 9. Prototype Results: (a) Upper output voltage and load current, (b) Lower output voltage and load current, (c) Upper output voltage THD, (d) Lower output voltage THD, (e) Upper Current THD, (f) Lower Current THD.
Figure 9. Prototype Results: (a) Upper output voltage and load current, (b) Lower output voltage and load current, (c) Upper output voltage THD, (d) Lower output voltage THD, (e) Upper Current THD, (f) Lower Current THD.
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Figure 10. Monitoring Screen.
Figure 10. Monitoring Screen.
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Table 1. CPS comparison.
Table 1. CPS comparison.
Ref.Sensors
Type
ModeNetwork/
Monitoring
Programming
Platform
[33]RFID TagZigbee,
CAN,
RFID
XMLMulti domain
[34]RTUWSNCC studio,
SCADA/HMI
Multi domain
[35]SenseLab
Sensor
WSNCooja network
simulator
Multi domain
[36]Sensor nodes
Green orbs
WSN,
Zigbee
Green orbs
host computer
Multi domain
[32]Sensors
PLC
WIFILabVIEW
JIL server
Multi domain
ProposedNI Sensors
MyRIO
WIFILabVIEW
VI Server
Single domain
Table 2. Comparison of Inverters.
Table 2. Comparison of Inverters.
Inverter TypeSwitchesSource TypeEVDV
Dual phase with single DC
bus with split Capacitor
4VoltageYesNo
Dual phase with three wire6VoltageYesNo
Dual phase dual DC bus4VoltageYesNo
Dual phase with transformer4VoltageYesNo
Dual output VSI6VoltageYesNo
Single port conventional CSI4CurrentYesNo
Proposed6CurrentYesYes
Table 3. System Parameters.
Table 3. System Parameters.
ParametersValues (Units)
Maximum Rated Power1 kW
DC Voltage ( V D C ) 120 V
Inductor10 mH
IGBTIRG4BC30S
ControllerNI myRIO 1900
Data Acquisition SystemsNI C-DAQ 9174
Driver CircuitTexas Instruments SM72295
ServerNI web server
Network MonitoringTotal Network Manager (TNM)
OscilloscopeTextronix TPS 2024B four channel
Table 4. THD.
Table 4. THD.
THDUpper Side
THD %
Lower Side
THD %
EVDVEVDV
Voltage THD4.74.75.34.3
Current THD4.45.44.34.8
Table 5. Loss comparison.
Table 5. Loss comparison.
Inverter TypeNo of OutputsNo of SwitchesTotal Loss
(w)
Conventional CSI1411.032
Two conventional CSI2822.064
Proposed dual output CSI2616.548

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Senthilnathan, K.; Annapoorani, I. Multi-Port Current Source Inverter for Smart Microgrid Applications: A Cyber Physical Paradigm. Electronics 2019, 8, 1. https://doi.org/10.3390/electronics8010001

AMA Style

Senthilnathan K, Annapoorani I. Multi-Port Current Source Inverter for Smart Microgrid Applications: A Cyber Physical Paradigm. Electronics. 2019; 8(1):1. https://doi.org/10.3390/electronics8010001

Chicago/Turabian Style

Senthilnathan, Karthikrajan, and Iyswarya Annapoorani. 2019. "Multi-Port Current Source Inverter for Smart Microgrid Applications: A Cyber Physical Paradigm" Electronics 8, no. 1: 1. https://doi.org/10.3390/electronics8010001

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